STW12NK95Z STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 1.1 Protection features of gate-to-source zener diodes
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

N-channel 950V - 0.69Ω - 10A - TO-247 Zener - Protected SuperMESH™ PowerMOSFET General features ■ Gate charge minimized ■ 100% avalanche tested ■ Extremely high dv/dt capability

Description

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications.

Applications

■ Switching application Internal schematic diagram Type VDSS (@Tjmax) RDS(on) ID PW STW12NK95Z 950 V < 0.90 Ω 10 A 230W TO-247 Order codes Part number Marking Package Packaging STW12NK95Z W12NK95Z TO-247 Tube

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Pulse width limited by safe operating area
  2. ISD ≤ 10A, di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

Table 2. Thermal data Table 3. Avalanche characteristics

1.1 Protection features of gate-to-source zener diodes

integrity. These integrated Zener diodes thus avoid the usage of external components. Table 4. Gate-source zener diode

2 Electrical characteristics

Table 5. On/off states Table 6. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%
  2. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

Table 7. Switching times

Table 8. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

Figure 13. Maximum avalanche

3 Test circuit

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test Figure 18. Unclamped inductive wavefo rm Figure 19. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 0.620 e5 . 4 5 0 . 2 1 4 L 14.20 14.80 0.560 0.582 L1 3.70 4.30 0.14 0.17 L2 18.50 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S5 . 5 0 0 . 2 1 6 TO-247 MECHANICAL DATA

5 Revision history

Table 9. Revision history 16-Jan-2006 1 Initial release.