STW12NB60 STMICROELECTRONICS | Alldatasheet
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Technical content
N-CHANNEL 600V - 0.5Ω - 12A TO-247 PowerMesh™II MOSFET ■ TYPICAL R DS (on) = 0.5Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ VERY LOW INTRINSIC CAPACITANCES ■ GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an ad- vanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termi- nation structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteris- tics.
APPLICATIONS
■ SWITCH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS TYPE V DSS R DS(on) ID STW12NB60 600V < 0.6 Ω 12 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 600 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 600 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 12 A ID Drain Current (continuos) at TC = 100°C 7.56 A IDM (● ) Drain Current (pulsed) 48 A PTOT Total Dissipation at TC = 25°C 190 W Derating Factor 1.52 W/°C dv/dt(1) Peak Diode Recovery voltage slope 4 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤12A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. TO-247 INTERNAL SCHEMATIC DIAGRAM
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 0.658 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 12 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 450 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 600 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250 µA 234V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 5.5A 0.5 0.60 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 5.5A C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2200 pF C oss Output Capacitance 285 pF C rss Reverse Transfer Capacitance 30 pF
Safe Operating Area Thermal Impedance ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time Rise Time VDD = 300V, ID = 5.5 A R G = 4.7Ω , VGS = 10V (see test circuit, Figure 3) 27 ns tr 12 ns Q g Total Gate Charge VDD = 480V, ID = 11 A, VGS = 10V, RG =4 . 7Ω 54 70 nC Q gs Gate-Source Charge 17 nC Q gd Gate-Drain Charge 23 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 480V, ID = 11 A, R G = 4.7Ω, VGS = 10V (see test circuit, Figure 5) 20 ns tf Fall Time 15 ns tc Cross-over Time 32 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 12 A ISDM (2) Source-drain Current (pulsed) 48 A VSD (1) Forward On Voltage ISD = 12 A, VGS = 0 1.6 V trr Reverse Recovery Time ISD = 11 A, di/dt = 100 A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 600 ns Q rr Reverse Recovery Charge 6.5 µC IRRM Reverse Recovery Current 20.5 A
Gate Charge vs Gate-source Voltage Capacitance Variations Transconductance Static Drain-source On Resistance Transfer CharacteristicsOutput Characteristics
Source-drain Diode Forward Characteristics Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load
DIM. mm inch A 4.7 5.3 0.185 0.209 D 2.2 2.6 0.087 0.102 E 0.4 0.8 0.016 0.031 F 1 1.4 0.039 0.055 F3 2 2.4 0.079 0.094 F4 3 3.4 0.118 0.134 G 10.9 0.429 H 15.3 15.9 0.602 0.626 L 19.7 20.3 0.776 0.779 L3 14.2 14.8 0.559 0.582 L4 34.6 1.362 L5 5.5 0.217 M 2 3 0.079 0.118 P025P TO-247 MECHANICAL DATA
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