STW10NC70Z STMICROELECTRONICS | Alldatasheet
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Technical content
N-CHANNEL 700V - 0.58 Ω - 10.6A TO-247 Zener-Protected PowerMESH™III MOSFET ■ TYPICAL R DS (on) = 0.58 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY GATE- TO-SOURCE ZENER DIODES ■ 100% AVALANCHE TESTED ■ VERY LOW INTRINSIC CAPACITANCES ■ GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH OVERLAY™ Power MOSFETs for very high voltage exhibits unsur- passed on-resistance per unit area while integrating back-to-back Zener diodes between gate and source. Such arrangement gives extra ESD capabil- ity with higher ruggedness performance as request- ed by a large variety of single-switch applications.
APPLICATIONS
■ SINGLE-ENDED SMPS IN MONITORS, COMPUTER AND INDUSTRIAL APPLICATION ■ WELDING EQUIPMENT ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area (1)ISD ≤10.6A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. (*)Limited only by maximum temperature allowed TYPE V DSS R DS(on) ID STW10NC70Z 700 V < 0.75 Ω 10.6 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 700 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 700 V VGS Gate- source Voltage ±25 V ID Drain Current (continuos) at TC = 25°C 10.6 A ID Drain Current (continuos) at TC = 100°C 6.7 A IDM (● ) Drain Current (pulsed) 42 A PTOT Total Dissipation at TC = 25°C 190 W Derating Factor 1.51 W/°C IGS Gate-source Current (*) ±50 mA VESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ) 4K V dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C TO-247
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.1 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 10.6 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 380 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 700 V ΔBV DSS /Δ TJ Breakdown Voltage Temp. Coefficient ID = 1 mA, VGS = 0 0.8 V/°C IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±20V ±10 µA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250 µA 345V R DS(on) Static Drain-source On Resistance VGS = 10 V, ID = 5.3 A 0.58 0.75 Ω ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS =1 0 V 10.6 A Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max, ID =5.3A 13 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 3550 pF C oss Output Capacitance 250 pF C rss Reverse Transfer Capacitance 30 pF
ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON (RESISTIVE LOAD) SWITCHING OFF (INDUCTIVE LOAD) SOURCE DRAIN DIODE GATE-SOURCE ZENER DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. ΔVBV = α T (25°-T) BVGSO (25°) PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 350V, ID = 5.3A R G = 4.7Ω VGS = 10V (see test circuit, Figure 3) 36 ns tr Rise Time 12 ns Q g Total Gate Charge VDD = 560V, ID = 10.6 A, VGS = 10V 72 100 nC Q gs Gate-Source Charge 19 nC Q gd Gate-Drain Charge 24 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 560V, ID = 10.6 A, R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 5) 36 ns tf Fall Time 36 ns tc Cross-over Time 77 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 10.6 A ISDM (2) Source-drain Current (pulsed) 42 A VSD (1) Forward On Voltage ISD = 10.6 A, VGS = 0 1.6 V trr Reverse Recovery Time ISD = 10.6 A, di/dt = 100A/µs, VDD = 50V, Tj = 150°C (see test circuit, Figure 5) 660 ns Q rr Reverse Recovery Charge 8.7 µC IRRM Reverse Recovery Current 26 A Symbol Parameter Test Conditions Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 25 V α T Voltage Thermal Coefficient T=25°C Note(3) 1.3 10-4/°C Rz Dynamic Resistance IGS = 50 mA 90 Ω
Transconductance Static Drain-source On Resistance Thermal ImpedanceSafe Operating Area Output Characteristics Transfer Characteristics
Gate Charge vs Gate-source Voltage Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature Capacitance Variations Normalized Gate Threshold Voltage vs Temp.
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuits For Resistive Load
DIM. mm inch A 4.7 5.3 0.185 0.209 D 2.2 2.6 0.087 0.102 E 0.4 0.8 0.016 0.031 F 1 1.4 0.039 0.055 F3 2 2.4 0.079 0.094 F4 3 3.4 0.118 0.134 G 10.9 0.429 H 15.3 15.9 0.602 0.626 L 19.7 20.3 0.776 0.779 L3 14.2 14.8 0.559 0.582 L4 34.6 1.362 L5 5.5 0.217 M 2 3 0.079 0.118 P025P TO-247 MECHANICAL DATA
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