STVM100 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Device overview
  • 2 Device operation
  • 2.1.1 Bus not busy
  • 2.1.2 Start data transfer
  • 2.1.3 Stop data transfer
  • 2.1.4 Data valid
  • 2.1.5 Acknowledge
  • 2.2 Read mode
  • 2.3 Write mode
  • 2.4 V DD power supply ramp-up
  • 3 Application information
  • 4 Maximum rating
  • 5 DC and AC parameters
  • 6 Typical operating char acteristics
  • 7 Package mechanical
  • 8 Part numbering
  • 9 Revision history

Features

■ I2C interface, slave address: 1001111 ■ 7-bit adjustable sink current output ■ 2.25V to 3.6V logic supply voltage VDD ■ AVDD operating voltages – 4.5V to 20V for V DD from 2.6V to 3.6V – 4.5V to 13V for V DD from 2.25V to 3.6V ■ EEPROM for storing the optimum VCOM setting ■ Guaranteed monotonic output over operating range ■ 400kHz maximum interface bus speed ■ Operating temperature: –40°C to 85°C ■ Available in an 8-pin 3mm x 3mm TDFN8 or 3mm x 3mm TSSOP8 Package

Applications

■ TFT-LCD panels

Description

The STVM100 is a programmable VCOM adjust- ment solution for thin-film transistor (TFT) liquid- crystal displays (LCDs) to remove “flickers”. It can replace a mechanical potentiometer, so that the factory operator can physically view the front screen when performing the VCOM adjustment. This significantly reduces labor costs, increases reliability, and enables automation. STVM100 provides a digital I 2C interface to con- trol the sink current output (IOUT). This output drives an external resistive voltage divider, which can then be applied to an external V COM buffer. Three external resistors R1, R2, and RSET deter- mine the highest and lowest value of the VCOM. An increase in the output sink current will lower the voltage on the external divider so that the V COM can be adjusted by 128 steps within this range. Once the desired VCOM setting is achieved, it can be stored in the internal EEPROM that will be automatically recalled dur- ing each power-up. STVM100 is available in an 8-pin, 3mm x 3mm TDFN8 or 3mm x 3mm TSSOP8 package. TDFN8 (3mm x 3mm) (DC) TSSOP8 (3mm x 3mm) (DS) Table 1. Device summary

1 Device overview

Figure 1. Logic diagram Table 2. Pin names and functions See Section 3: Application information on page 11.

  1. See SET pin function in this table for the maximum adjustable sink current setting.

AVDD Supply High-voltage analog supply. Bypass to GND with a 0.1µF capacitor. VDD Supply System power supply input. Bypass to GND with a 0.1µF capacitor. SDA In/Out I 2C serial data input/output. SCL Input I 2C serial clock input. Maximum sink current adjustment point. DD /20 divided by RSET (see Figure 4 on page 6).

Figure 2. Connections diagram Figure 3. Block diagram Figure 4. Hardware hookup

7 SET

2 Device operation

The STVM100 operates as a slave device on the serial bus. Access is obtained by implementing a Start condition, followed by the 7-bit slave address (1001111), and the eighth bit for READ/WRITE identification. The volatile DAC register and non-volatile EEPROM values can be read out or written in. 2.1 2-wire bus characteristics and conditions This bus is intended for communication between different ICs. It consists of two lines:

  • a bi-directional data signal (SDA).
  • a clock signal (SCL). The SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocols have been defined:
  • Data transfer may be initiated only when the bus is not busy.
  • During data transfer, the data line must remain stable whenever the clock line is high.
  • Changes in the data line while the clock line is high will be interpreted as control signals.

2.1.1 Bus not busy

Both data and clock lines remain High.

2.1.2 Start data transfer

A change in the data line state from high-to-low while the clock is high indicate the Start condition.

2.1.3 Stop data transfer

A change in the data line state from low-to-high while the clock is high indicates the Stop condition.

2.1.4 Data valid

(see Figure 5). The data on the line may be changed during the clock signal low period. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is not limited. “master”. The devices controlled by the master are called “slave” devices. Figure 5. Serial bus data transfer sequence

2.1.5 Acknowledge

clocked out of the slave transmitter. Figure 6. Acknowledgement sequence

2.2 Read mode

In READ mode, after the Start condition, the master sets the slave address (see Figure 7). READ mode, the valid data is the first 7 bits and the P bit (the eight bit) is don’t care.

2.3 Write mode

operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing. slave will not acknowledge any WRITE operation. The bit P values in both READ and WRITE modes are shown in Table 3. Figure 7. Read/write mode sequence

2.4 V DD power supply ramp-up

correct value is read from the EEPROM. Table 3. Bit P read and write mode values

1 DAC register WRITE

0 EEPROM WRITE

3 Application information

external resistive voltage divider, which can then be applied to an external VCOM buffer. connection is shown in Figure 8. through RSET. This current must be less than 120µA (see ISET value in Table 7 on page 15). Figure 8. R 1, R2, and RSET connection Note: “D” is a user-selected value, an integer ranging from 0 to 127. The VCOM value can be obtained in Equation 2.

If the user-selected value is 0 (zero scale), the minimum current is sunk. The maximum VCOM value is obtained in Equation 3. Equation 3 If the user-selected value is 127 (full scale), the maximum current is sunk and the minimum VCOM value is obtained in Equation 4. Equation 4 During operation, the VCOM(max) and VCOM(min) range is set, based on different TFT -LCD processes.The R1 value is given based on the acceptable power loss from the AVDD supply rail. Using Equation 3 and Equation 4, the R2 and RSET values can be calculated. If RSET is put into Equation 1 on page 11 and maximum IOUT ≥ 120µA, then R1 should be increased. VCOM max() ⎛⎞⋅= VCOM min() ⎛⎞⋅=

4 Maximum rating

Program and other relevant quality documents. Table 4. Absolute maximum ratings

  1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C

for between 90 to 150 seconds).

5 DC and AC parameters

Table 5. Operating and AC measurement conditions Table 6. Capacitances

  1. Effective capacitance measured with power supply at 3V. Sampled only, not 100% tested.

Table 7. DC and AC characteristics

  1. Valid for ambient operating temperature: T A = –40 to 85°C; VDD = 3V; AVDD = 10V; typical TA = 25°C;

OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted).

  1. Simulated maximum current draw when Progra mming EEPROM is 23mA; should be considered when
  2. A typical Current of 20µA is calculated using AV DD = 10V and RSET = 24.9kΩ. The maximum suggested

SET current should be 120µA.

  1. Simulated and determined via design and NOT directly tested.

20 V/V

Figure 9. Bus timing requirements sequence Table 8. AC characteristics

  1. Valid for ambient operating temperature: T A = –40 to 85°C; VDD = 3.0V to 3.6V; AVDD = 10V;

OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted, see Figure 9).

6 Typical operating characteristics

OUT = 1/2AVDD, and RSET = 24.9kΩ except where noted. Figure 10. V DD supply current v’s VDD Figure 11. AV DD supply current v’s AVDD

Figure 20. Full scale-down response

7 Package mechanical

conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data Table 9. MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data

Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data Note: Drawing is not to scale. Table 10. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data

8 Part numbering

Table 11. Ordering information scheme ST sales office nearest you.

9 Revision history

Table 12. Revision history 09-May-2006 1 Initial release. information in Figure 21, Table 9, and Table 10. 20-Apr-2007 5 Value added in Section 2.3: Write mode. 24-Jul-2007 6 Document status upgraded to full datasheet.