STV9118

STV9118 STMICROELECTRONICS | Alldatasheet

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Technical content

LOW-COST I 2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR DATASHEET

FEATURES

■ ADVANCED I 2C BUS CONTROLLED DEFLECTION PROCESSOR DEDICATED FOR HIGH-END CRT MONITORS ■ SINGLE SUPPLY VOLTAGE 12V ■ VERY LOW JITTER ■ DC/DC CONVERTER CONTROLLER ■ ADVANCED EW DRIVE ■ ADVANCED ASYMMETRY CORRECTIONS ■ AUTOMATIC MULTISTANDARD SYNCHRONIZATION ■ VERTICAL DYNAMIC CORRECTION WAVEFORM OUTPUT ■ X-RAY PROTECTION AND SOFT-START & STOP ON HORIZONTAL AND DC/DC DRIVE OUTPUTS ■ I2C BUS STATUS REGISTER Horizontal section ■ 100 kHz maximum frequency ■ Corrections of geometric asymmetry: Pin cushion asymmetry, Parallelogram ■ Tracking of asymmetry corrections with vertical size and position ■ Fully integrated internal horizontal moiré cancellation and moiré cancellation output Vertical section ■ 200 Hz maximum frequency ■ Vertical ramp for DC-coupled output stage with adjustments of: C-correction, S-correction for super-flat CRT, Vertical size, Vertical position ■ Vertical moiré cancellation through vertical ramp waveform ■ Compensation of vertical breathing with EHT variation EW section ■ Symmetrical geometry corrections: Pin cushion, Keystone, Top/Bottom corners separately ■ Horizontal size adjustment ■ Tracking of EW waveform with Vertical size and position and adaptation to frequency ■ Compensation of horizontal breathing through EW waveform Dynamic correction section ■ Output with vertical dynamic correction waveform for dynamic corrections like focus, brightness uniformity, ... ■ Fixed on screen by means of tracking system DC/DC controller section ■ N-MOS transistor drive ■ External sawtooth configuration ■ Bus-controlled output voltage ■ Synchronization on hor. frequency with phase selection

DESCRIPTION

The STV9118 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combined with the powerful geometry correction block, makes the STV9118 suitable for very high performance mon- itors, using few external components. Combined with other ST components dedicated for CRT monitors (microcontroller, video preampli- fier, video amplifier, OSD controller) the STV9118 allows fully I 2C bus-controlled computer display monitors to be built with a reduced number of ex- ternal components. SHRINK 32 (Plastic Package) ORDER CODE: STV9118

10.1.2 -I

ACK ACK nowledge bit of I2C-bus transfer AGC A utomatic G ain C ontrol COMP COMP arator CRT C athode R ay Tube DC D irect C urrent EHT E xtra H igh Voltage EW E ast-W est H/W H ardW are HOT H orizontal O utput Transistor I2CI nter-Integrated C ircuit IIC I nter-Integrated C ircuit MCU M icro-C ontroller U nit NAND N egated AND (logic operation) NPN N egative-Positive-N egative OSC OSC illator PLL P hase-Locked Loop PNP P ositive-N egative-Positive REF REF erence RS, R-S R eset-Set S/W S oftW are TTL T ransistor Transistor Logic VCO V oltage-C ontrolled O scillator

HMoiré HFly RefOut BComp BRegIn BISense HOscF HEHTIn VEHTIn VOscF VAGCCap VGND VCap VOut EWOut XRay HOut GND BOut Vcc SCL SDA VDyCor

comparatorHorizontal position Lock detection PLL1 V-sync detection Input selection Polarity handling Vertical oscillator with AGC S-correctionC-correction PLL2 Phase comparator Phase shifter H duty controllerPin cushion asymm.ParallelogramHor. duty cycle H-drive buffer Int./Ext. H-moiré H-moir é amplitude V-sync extraction & detection Geometry tracking V-dynamic correction (focus, bright.)VDyCor amplitude H-sync detection Polarity handling V-blank H-lock 3HLckVBk Safety processor

25 XRay

11 HMoiré

26 HOut

B+ ref.

28 BOut

16 BISense

15 BRegIn

14 BComp

Tracking EHTVertical sizeVertical positionVertical moir é VEHTIn VOut HEHTIn EW generator Pin cushionKeystoneTop cornersBottom corners

24 EWOut

ref. : Functions controlled via I 2C Bus H size Control voltage level

4 - PIN FUNCTION REFERENCE Pin Name Function 1 H/HVSyn TTL compatible H orizontal / H orizontal and Vertical Syn c. input 2 VSyn TTL compatible Vertical Syn c. input

3 HLckVBk H orizontal PLL1 Lock detection and Vertical early B lanking composite output

4 HOscF High H orizontal Osc illator sawtooth threshold level Filter input

5 HPLL2C H orizontal PLL2 loop C apacitive filter input

6 CO Horizontal O scillator C apacitor input

7 HGND H orizontal section G rouND

8 RO Horizontal O scillator R esistor input

9 HPLL1F H orizontal PLL1 loop Filter input

10 HPosF H orizontal Pos ition Filter and soft-start time constant capacitor input

11 HMoiré H orizontal M oiré output

12 HFly H orizontal Flyback input

13 RefOut Reference voltage Output

14 BComp B + DC/DC error amplifier (Comp arator) output

15 BRegIn Reg ulation feedback Input of the B + DC/DC converter controller

16 BISense B + DC/DC converter current (I) Sense input

17 HEHTIn Input for compensation of H orizontal amplitude versus EHT variation

18 VEHTIn Input for compensation of Vertical amplitude versus EHT variation

19 VOscF Vertical Osc illator sawtooth low threshold Filter (capacitor to be connected to VGND)

20 VAGCCap Input for storage Cap acitor for A utomatic G ain C ontrol loop in Vertical oscillator

21 VGND Vertical section G rouND

22 VCap Vertical sawtooth generator Cap acitor

23 VOut Vertical deflection drive Output for a DC-coupled output stage

24 EWOut E/W Output

25 XRay X-Ray protection input

26 HOut H orizontal drive Output

27 GND Main G rouND

28 BOut B + DC/DC converter controller Output

29 Vcc Supply voltage

30 SCL I

2C bus S erial CL ock Input

31 SDA I 2C bus S erial DA ta input/output

32 VDyCor Vertical Dy namic Correction output

Application category Mid-range Means of control/Maximum clock frequency I 2C bus/400 kHz EW drive Yes DC/DC converter controller Yes Adjustable DC level output No Horizontal section Frequency range 15 to 100 kHz Autosync frequency ratio (can be enlarged in application) 4.28 Positive/Negative polarity of horizontal sync signal/Automatic adaptation Yes/Yes/Yes Duty cycle range of the drive signal 30 to 65 % Position adjustment range with respect to H period ±10 % Soft start/Soft stop feature Yes/Yes Hardware/Software PLL lock indication Yes/Yes Parallelogram Yes Pin cushion asymmetry correction (also called Side pin balance) Yes Top/Bottom/Common corner asymmetry correction No/No/No Tracking of asymmetry corrections with vertical size & position Yes Horizontal moiré cancellation (int./ext.) for Combined/Separated architecture Yes/Yes Vertical section Frequency range 35 to 200 Hz Autosync frequency range (150nF at VCap and 470nF at VAGCCap) 50 to 180 Hz Positive/Negative polarity of vertical sync signa/Automatic adaptationl Yes/Yes/Yes S-correction/C-correction/Super-flat tube characteristic Yes/Yes/Yes Vertical size/Vertical position adjustment Yes/Yes Vertical moiré cancellation (internal) Yes Vertical breathing compensation Yes EW section Pin cushion correction Yes Keystone correction Yes Top/Bottom/Common corner correction Yes/Yes/No Horizontal size adjustment Yes Tracking of EW waveform with Frequency/Vertical size & position Yes/Yes Breathing compensation on EW waveform Yes Vertical dynamic correction output Yes Horizontal dynamic correction output No Composite HV dynamic correction output No Tracking of vertical waveform with V. size & position Yes DC/DC controller section Step-up/Step-down conversion mode Yes/Yes(ext) Internal/External sawtooth configuration No/Yes Bus-controlled output voltage Yes Soft start/Soft stop feature Yes/Yes Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal Yes/No

6 - ABSOLUTE MAXIMUM RATINGS All voltages are given with respect to ground. Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. The value ranges must be absolutely respected, any excess thereof may cause permanent damage to the device. Symbol Parameter Value UnitMin Max VCC Supply voltage (pin Vcc) -0.4 13.5 V V(pin) Pins HEHTIn, VEHTIn, XRay, HOut, BOut Pins H/HVSyn, VSyn, SCL, SDA Pins HLckVBk, CO, RO, HPLL1F, HPosF, HMoiré, BRegIn, BI- Sense, VAGCCap , VCap, VDyCor, HOscF, VOscF Pin HPLL2C Pin HFly -0.4 -0.4 -0.4 -0.4 -0.4 VCC 5.5 V RefO VRefO/2 V RefO V V V V V I(pin) Pin HMoiré Pins other than HMoiré -200 -200 100 200 mA mA VESD ESD susceptibility (human body model: discharge of 100pF through 1.5kΩ ) -2000 2000 V Tstg Storage temperature -40 150 °C Tj Junction temperature 150 °C

7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS The medium (middle) value of an I2C Bus control or adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". The minimum value is the one with all bits at 0, maximum value is the one with all at "1". Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. T H is the period of horizontal deflection. 7.1 - THERMAL DATA 7.2 - SUPPLY AND REFERENCE VOLTAGES Tamb = 25°C 7.3 - SYNCHRONIZATION INPUTS Vcc = 12V, Tamb = 25°C Symbol Parameter Value UnitMin. Typ. Max. Tamb Operating ambient temperature 0 70 °C R th(j-a) Junction-ambience thermal resistance 65 °C/W Symbol Parameter Test Conditions Value Units Min. Typ. Max. VCC Supply voltage at Vcc pin 10.8 12 13.2 V ICC Supply current to Vcc pin VCC = 12V 65 mA VRefO Reference output voltage at RefOut pin VCC = 12V, IRefO= -2mA 7.65 7.9 8.2 V IRefO Current sourced by RefOut output -5 0 mA Symbol Parameter Test Conditions Value Units Min. Typ. Max. VLoH/HVSyn LOW level voltage on H/HVSyn 0 0.8 V VHiH/HVSyn HIGH level voltage on H/HVSyn 2.2 5 V VLoVSyn LOW level voltage on VSyn 0 0.8 V VHiVSyn HIGH level voltage on VSyn 2.2 5 V R PdSyn Internal pull-down on H/HVSyn, VSyn 100 175 250 k Ω tPulseHSyn H sync. pulse duration on H/HVSyn pin 0.5 µs tPulseHSyn/TH Proportion of H sync pulse to H period Pin H/HVSyn 0.2 tPulseVSyn V sync. pulse duration Pins H/HVSyn, VSyn 0.5 750 µs tPulseVSyn/TV Proportion of V sync pulse to V period Pins H/HVSyn, VSyn 0.15 textrV/TH Proportion of sync pulse length to H peri- od for extraction as V sync pulse Pin H/HVSyn, cap. on pin CO = 820pF 0.21 0.3 tHPolDet Polarity detection time (after change) Pin H/HVSyn 0.75 ms

7.4 - HORIZONTAL SECTION Vcc = 12V, Tamb = 25°C Symbol Parameter Test Conditions Value Units Min. Typ. Max. PLL1 IRO Current load on RO pin 1.5 mA C CO Capacitance on CO pin 390 pF fHO Frequency of hor. oscillator 100 kHz fHOCapt Hor. PLL1 capture frequency (4) fHO(0) = 28.5kHz 29 122 kHz Temperature drift of free-running freq. (3) -150 ppm/°C ΔfHO /ΔVHO Average horizontal oscillator sensitivityfHO(0) = 28.5kHz 19.6 kHz/V VHO H. oscill. control voltage on pin HPLL1F VRefO=8V 1.4 6.0 V VHOThrfr Threshold on H. oscill. control voltage on HPLL1F pin for tracking of EW with freq.VRefO=8V 5.0 V VHPosF Control voltage on HPosF pin HPOS (Sad01): 1111111xb 1000000xb 0000000xb 2.8 3.4 4.0 V V V VHOThrLo Bottom of hor. oscillator sawtooth(6) 1.6 V VHOThrHi Top of hor. oscillator sawtooth(6) 6.4 V PLL2 R In(HFly) Input impedance on HFly input V (HFly) >V ThrHFly (2) 300 500 700 Ω IInHFly Current into HFly input At top of H flyback pulse 5 mA VThrHFly Voltage threshold on HFly input 0.6 0.7 V VS(0) H flyback lock middle point(6) No PLL2 phase modula- tion 4.0 V VBotHPLL2C Low clamping voltage on HPLL2C pin(5) 1.6 V VTopHPLL2C High clamping voltage on HPLL2C pin(5) 4.0 V tph(min)/TH Min. advance of H-drive OFF before middle of H flyback(7) Null asym. correction 0 % tph(max)/TH Max. advance of H-drive OFF before middle of H flyback(8) Null asym. correction 44 % H-drive output on pin HOut IHOut Current into HOut output Output driven LOW 30 mA tHoff/TH Duty cycle of H-drive signal HDUTY (Sad00): x1111111b x0000000b Soft-start/Soft-stop value Picture geometry corrections through PLL1 & PLL2 tHph /TH H-flyback (center) static phase vs. sync signal (via PLL1), see Figure 7 HPOS (Sad01): 1111111xb 0000000xb +11 -11 fHO 0()Δ

Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. The application must consider the spread of values of real electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate the free-running frequency is fHO(0)=0.12125/(RRO CCO ) Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of about 500Ω and a resistance to ground of about 20kΩ. Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit. Note 4: This capture range can be enlarged by external circuitry. Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state. Note 6: Internal threshold. See Figure 10. Note 7: The tph(min)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C high clamping level by waveform on pin HPLL2C . Also refer to Note 5 and Figure 10. Note 8: The tph(max)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C low clamping level by waveform on pin HPLL2C . Also refer to Note 5 and Figure 10 . Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions. 7.5 - VERTICAL SECTION VCC = 12V, Tamb = 25°C tPCAC /TH Contribution of pin cushion asymmetry correction to phase of H-drive vs. static phase (via PLL2), measured in corners PCAC (Sad11h) full span (9) VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum ±1.0 ±1.8 ±2.8 tParalC/TH Contribution of parallelogram correction to phase of H-drive vs. static phase (via PLL2), measured in corners PARAL (Sad12h) full span (9) VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum VPOS at max. or min. VSIZE at minimum ±1.75 ±2.2 ±2.8 ±1.75 Symbol Parameter Test Conditions Value Units Min. Typ. Max. Symbol Parameter Test Conditions Value Units Min. Typ. Max. AGC-controlled vertical oscillator sawtooth; VRefO = 8V R L(VAGCCap) Ext. load resistance on VAGCCap pin(10) ΔVamp /Vamp (R=∞ ) ≤1% 65 M Ω VVOB Sawtooth bottom voltage on VCap pin(11) No load on VOscF pin(11) 2V VVOT Sawtooth top voltage on VCap pin AGC loop stabilized V sync present No V sync 4.9 V V

Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc., for less than 1% of Vamp change. Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will influence the value of VVOB . Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null SCOR (Sad09 at x0000000b) and null CCOR (Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin. Note 13: Maximum SCOR (Sad09 at x1111111b), null CCOR (Sad0A at x1000000b). Note 14: Null SCOR (Sad09 at x0000000b). Note 15: "tVR " is time from the beginning of vertical ramp of V-drive signal on VOut pin. "TVR " is duration of this ramp, see chapter TYPICAL OUTPUT WAVEFORMS and Figure 13. Note 16: VVOamp = VVOT -VVOB Note 17: The same rate applies to V-drive signal on VOut pin. Note 18: Informative, not tested on each unit. tVODis Sawtooth Discharge time C VCap =150nF 80 µs fVO(0) Free-running frequency C VCap =150nF 100 Hz fVOCapt AGC loop capture frequency C VCap =150nF 50 185 Hz Sawtooth non-linearity(12) AGC loop stabilized, (12) 0.5 % S-correction range AGC loop stabilized, (13) tVR =1/4 TVR (15) tVR =3/4 TVR C-correction range AGC loop stabilized, (14) tVR =1/2 TVR (15) CCOR (Sad0A): x0000000b x1000000b x1111111b Frequency drift of sawtooth amplitude(17)(18) AGC loop stabilized fVOCapt (min)≤fVO ≤fVOCapt (max) 200 ppm/ Hz Vertical output drive signal (on pin VOut);VRefO = 8V Vmid(VOut) Middle point on VOut sawtooth VPOS (Sad08): x0000000b x1000000b x1111111b 3.65 3.2 3.5 3.8 3.3 V V V V amp Amplitude of VOut sawtooth (peak-to-peak voltage) VSIZE (Sad07): x0000000b x1000000b x1111111b 3.5 2.25 3.0 3.75 2.5 V V V V offVOut Level on VOut pin at V-drive "off" I2Cbit VOutEn at 0 3.8 V IVOut Current delivered by VOut out- put -5 5 mA VVEHT Control input voltage range on VEHTIn pin 1 VRefO V Breathing compensation VVEHT >VRefO VVEHT (min)≤VVEHT ≤VRefO 2.5 %/V %/V Symbol Parameter Test Conditions Value Units Min. Typ. Max. V VOdevΔ V VOamp 16() V VOS cor–Δ VVOamp VVOC cor–Δ VVOamp V VOampΔ VampΔ

7.6 - EW DRIVE SECTION VCC = 12V, Tamb = 25°C Symbol Parameter Test Conditions Value Units Min. Typ. Max. VEW Output voltage on EWOut pin 1.8 6.5 V IEWOut Current sourced by EWOut out- put -1.5 TBD mA VHEHT Control voltage range on HEH- TIn pin 1 VRefO V VEW-DC DC component of the EW-drive signal on EWOut pin (19)(22)(23)(30) tVR =1/2 TVR (15) HSIZE (Sad10h): 0000000xb 1000000xb 1111111xb 3.25 4.5 V V V Breathing compensation on VEW-DC (19)(20)(21)(22) tVR =1/2 TVR (15) VHEHT >VRefO VHEHT (min)≤VHEHT ≤VRefO -0.125 V/V V/V Temperature drift of DC compo- nent of the EW-drive signal on EWOut pin tVR =1/2 TVR (15) VEW-PCC Pin cushion correction compo- nent of the EW-drive signal on EWOut pin VSIZE at maximum PCC (Sad0C): x0000000b x1000000b x1111111b Tracking with VSIZE : PCC at x1000000b VSIZE (Sad07): x0000000b x1000000b 0.7 1.5 0.25 0.5 V V V V V Tracking of PCC component of the EW-drive signal with vertical position adjustment PCC at x1111111b VPOS (Sad08): x0000000b x1111111b 0.52 1.92 VEW-Key Keystone correction component of the EW-drive signal on EWOut pin KEYST (Sad0D): x0000000b x1111111b 0.4 -0.4 V V VEW-TCor Top corner correction compo- nent of the EW-drive signal on EWOut pin TCC (Sad0E): x0000000b x1000000b x1111111b -1.25 +1.25 V V V VEW-BCor Bottom corner correction compo- nent of the EW-drive signal on EWOut pin BCC (Sad0F): x0000000b x1000000b x1111111b -1.25 +1.25 V V V V EW DC–Δ V EW DC–Δ V EW PCC– tvr 0=[]

Note 19: KEYST at medium (neutral) value. Note 20: TCC at medium (neutral) value. Note 21: BCC at medium (neutral) value. Note 22: PCC at minimum value. Note 23: VPOS at medium (neutral) value. Note 24: HSIZE at minimum value. Note 25: Defined as difference of (voltage at tVR =0) minus (voltage at tVR =1/2 TVR ). Note 26: Defined as difference of (voltage at tVR =TVR ) minus (voltage at tVR =1/2 TVR ). Note 27: VSIZE at maximum value. Note 28: Difference (voltage at tVR =0) minus (voltage at tVR =TVR ). Note 29: Ratio "A/B"of parabola component voltage at tVR =0 versus parabola component voltage at tVR =TVR . Note 30: VHEHT >VRefO , VVEHT >VRefO Note 31: VEW-AC is sum of all components other than VEW-DC (contribution of PCC, keystone correction and corner corrections). Note 32: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by external components on PLL1 pins. VEW [fmax] is the value at condition VHO >V HOThrfr. 7.7 - DYNAMIC CORRECTION OUTPUT SECTION VCC = 12V, Tamb = 25°C Tracking of EW-drive signal with horizontal frequency(32) VHO >VHOThrfr VHO (min)≤VHO ≤VHOThrfr %/V %/V Breathing compensation on VEW-AC (31) (25)(26) VHEHT >VRefO VHEHT (min)≤VHEHT ≤VRefO 1.75 %/V %/V Symbol Parameter Test Conditions Value Units Min. Typ. Max. V EWΔ V EW fmax[] V HOΔ⋅ V EW AC–Δ Symbol Parameter Test Conditions Value Units Min. Typ. Max. Vertical Dynamic Correction output VDyCor IVDyCor Current delivered by VDyCor out- put -1.5 TBD mA VVD-DC DC component of the drive signal on VDyCor output R L(VDyCor)=10kΩ 4V IVVD-V I Amplitude of V-parabola on VDy- Cor output(34) (23) VSIZE at medium VDC-AMP (Sad15h): x0000000b x1000000b x1111111b VDC-AMP at maximum VSIZE (Sad07): x0000000b x1111111b 0.5 0.6 1.6 V V V V V Tracking of V-parabola on VDyCor output with vertical position (33) VDC-AMP at maximum VPOS (Sad08): x0000000b x1111111b 0.52 1.92 V VD V– tvr 0=[]

Note 33: Ratio "A/B"of vertical parabola component voltage at tVR =0 versus vertical parabola component voltage at tVR =TVR . Note 34: Unsigned value. Polarity selection by VDyCorPol I2C Bus bit. Refer to section I2C Bus control register map. 7.8 - DC/DC CONTROLLER SECTION VCC = 12V, Tamb = 25°C Note 35: A current sink is provided by the BComp output while BOut is disabled: Note 36: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is stabilized. Note 37: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On” edge with horizontal flyback signal. Refer to chapter "DC/DC controller" for more details. Note 38: tinh is about 300ns regardless of the H frequency Symbol Parameter Test Conditions Value Units Min. Typ. Max. R B+FB Ext. resistance applied between BComp output and BRegIn input 5k Ω AOLG Open loop gain of error amplifier on BRegIn input Low frequency(18) 100 dB fUGBW Unity gain bandwidth of error am- plifier on BRegIn input (18) 6M H z IRI Bias current delivered by regula- tion input BRegIn -0.2 µA IBComp Output current capability of BComp output. HBOutEn = "Enable" HBOutEn = "Disable" (35) -0.5 0.5 2.0 mA mA ABISense Voltage gain on BISense input 3 VThrBIsCurr Threshold voltage on BISense input corresponding to current limitation TBD 2.1 V IBISense Input current sourced by BISense input -1 µA tBOn Conduction time of the power transistor (38) TH -tinh IBOut Output current capability of BOut output 01 0 m A VBOSat Saturation voltage of the internal output transistor on BOut IBOut=10mA 0.25 V VBReg Regulation reference for BRegIn voltage(36) VRefO=8V BREF (Sad03): x0000000b x1000000b x1111111b 3.8 4.9 6.0 V V V t BTrigDel/TH Delay of BOut “Off-to-On” edge after middle of flyback pulse, as part of TH (37) BOutPh = "0" 16 %

7.9 - MISCELLANEOUS VCC = 12V, Tamb = 25°C Note 39: Current sunk by the pin if the external voltage is higher than one the circuit tries to force. Note 40: The threshold is equal to actual VRefO. Note 41: In the regions of VCC where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on HOut, VOut and BOut pins, resp., are inhibited, the I2C Bus does not accept any data and the XRayAlarm flag is reset. Also see Figure 15 Note 42: See Figure 10 Symbol Parameter Test Conditions Value Units Min. Typ. Max. Vertical blanking and horizontal lock indication composite output HLckVBk ISinkLckBk Sink current to HLckVBk pin (39) TBD µA VOLckBk Output voltage on HLckVBk output 0.1 1.1 V V V V Horizontal moiré canceller Modulation of TH by H-moiré function HMoiMode =0 (internal) HMOIRE (Sad02): x0000000b x1111111b 0.04 VHMoiré H-moiré pulse amplitude on HMoiré pin HMoiMode =1 (external) Rext=10kΩ HMOIRE (Sad02): x0000000b x1111111b 0.1 2.1 V V Vertical moiré canceller VV-moiré Amplitude of modulation of V-drive sig- nal on VOut pin by vertical moiré. VMOIRE (Sad0Bh): x0000000b x1111111b mV mV Protection functions VThrXRay Input threshold on XRay input(40) 7.65 7.9 8.2 V tXRayDelay Delay time between XRay detection event and protection action 2TH VCCEn VCC value for start of operation at VCC ramp-up(41) 8.5 V VCCDis VCC value for stop of operation at VCC ramp-down(41) 6.5 V Control voltages on HPosF pin for Soft start/stop operation(18)(42) VHOn Threshold for start/stop of H-drive sig- nal 1V VBOn Threshold for start/stop of B-drive sig- nal 1.7 V VHBNorm f Threshold for full operational duty cycle of H-drive and B-drive signals 2.4 VHPos Voltage on HPosF pin as function of ad- justment of HPOS register Normal operation HPOS (Sad01) 0000000xb 1111111xb 4.0 2.8 V V V.blank H.lock No Yes Yes Yes No No Yes No THH m o i r e–()Δ TH

8 - TYPICAL OUTPUT WAVEFORMS Note (43) Function Sad Pin Byte Waveform Effect on Screen Vertical Size 07 VOut x0000000 x1111111 Vertical Position 08 VOut x0000000 x1000000 x1111111 S-correction 09 VOut x0000000: Null x1111111: Max. C-correction 0A VOut x0000000 x1000000 : Null x1111111 Vmid(VOut) Vamp(min) Vmid(VOut) Vamp(max) Vmid(VOut) 3.5V Vmid(VOut) 3.5V Vmid(VOut) 3.5V VVOamp VVOS-cor VVOamp tVR0 ¼ TVR ¾ TVR TVR VVOC-cor VVOamp tVR0 ½ TVR TVR VVOamp VVOC-cor VVOamp tVR0 ½ TVR TVR

Vertical moiré amplitude 0B VOut x0000000: Null x1111111: Max. Horizontal size 10h EWOut 0000000x 1111111x Keystone correction 0D EWOut x0000000 x1111111 Pin cushion correction 0C EWOut x0000000 x1111111 Top corner correction 0E EWOut x1111111 x0000000 Bottom corner correction 0F EWOut x1111111 x0000000 Function Sad Pin Byte Waveform Effect on Screen Vamp tnTV (n+1)TV(n-1)TV VV-moiré Vamp tnTV (n+1)TV(n-1)TV tVR0 ½ TVR TVR VEW-DC(min) tVR0 ½ TVR TVR VEW-DC(max) VEW-key VEW-DC VEW-key VEW-DC tVR0 ½ TVR TVR VEW-PCC(min) tVR0 ½ TVR TVR VEW-PCC(max) tVR0 ½ TVR TVR VEW-TCor(max) tVR0 ½ TVR TVR VEW-TCor(min) tVR0 ½ TVR TVR VEW-TBot(max) tVR0 ½ TVR TVR VEW-TBot(min)

Note 43: For any H and V correction component of the waveforms on EWOut and VOut pins and for internal waveform for corrections of H asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram, parabola asymmetry correction, written in corresponding registers). Parallelogram correction 12h x0000000 x1111111 Pin cushion asymmetry correction 11h x0000000 x1111111 Vertical dynamic correction amplitude 15h VDyCor 01111111 Application dependentx0000000 11111111 Function Sad Pin Byte Waveform Effect on Screen Internal tParalC(min) static phase tVR0 ½ TVR TVR tParalC(max) static phase tVR0 ½ TVR TVR Internal tVR0 ½ TVR TVR tPCAC (max) static H-phase tVR0 ½ TVR TVR tPCAC (max) static H-phase tVR0 ½ TVR TVR VVD-V(max) VVD-DC VDyCorPol=0 tVR0 ½ TVR TVR VVD-V(max) VVD-DC tVR0 ½ TVR TVR VVD-V(max) VVD-DC VDyCorPol=1

9 - I2C BUS CONTROL REGISTER MAP The device slave address is 8C in write mode and 8D in read mode. Bold weight denotes default value at Power-On-Reset. I2C Bus data in the adjustment register is buffered and internally applied with discharge of the vertical os- cillator (44). In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0. Sad D7 D6 D5 D4 D3 D2 D1 D0 WRITE MODE (SLAVE ADDRESS = 8C) HDutySyncV 1: Synchro. 0: Asynchro. HDUTY (Horizontal duty cycle) 0 0 0 0 0 0 0 HPOS (Horizontal position) Reserved1 000000 HMoiré 1: Separated 0: Combined HMOIRE (Horizontal moiré amplitude) 0000000

03 B+SyncV

0: Asynchro. BREF (B+reference) 1000000

04 Reserved Reserved

05 Reserved Reserved

06 Reserved Reserved

0: H-flyback 1: H-drive VSIZE (Vertical size) 1000000

08 EWTrHFr

0: No tracking VPOS (Vertical position) 1000000

09 Reserved SCOR (S-correction)

CCOR (C-correction) 1000000 0B Reserved VMOIRE (Vertical moiré amplitude) 0000000 0C Reserved PCC (Pin cushion correction) 1000000 0D Reserved KEYST (Keystone correction) 1000000 0E Reserved TCC (Top corner correction) 1000000 0F Reserved BCC (Bottom corner correction) 1000000

10 HSIZE (Horizontal size) Reserved

11 Reserved

PCAC (Pin cushion asymmetry correction) 1000000

Note 44: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches HDutySyncV and B+SyncV are at 0 respectively. Note 45: In Read Mode, the device always outputs data of the status register, regardless of sub address previously selected. Note 46: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application. Description of I2C Bus switches and flags Write-to bits Sad00/D7 - HDutySyncV Sync hronization of internal application of H ori- zontal Duty cycle data, buffered in I2C Bus latch, with internal discharge of Vertical oscillator 0: Asynchronous mode, new data applied with ACK bit of I2C Bus transfer on this sub address 1: Synchronous mode Sad02/D7 - HMoiré H orizontal Moiré characteristics 0: Adapted to an architecture with EHT gener- ated in deflection section 1: Adapted to an architecture with separated deflection and EHT sections Sad03/D7 - B+SyncV Same as HDutySyncV , applicable for B+ refer- ence data Sad07/D7 - BOutPh Ph ase of start of B+ drive signal on BOut pin 0: Just after horizontal flyback pulse 1: With one of edges of line drive signal on HOut pin, selected by BOHEdge bit Sad08/D7 - EWTrHFr Tracking of all corrections contained in wave- form on pin EWOut with H orizontal Frequency 0: Not active 1: Active Sad15/D7 - VDyCorPol Polarity of Vertical Dy namic Correction wave- form (parabola) 0: Concave (minimum in the middle of the pa- rabola) 1: Convex (maximum in the middle of the pa- rabola) Sad16/D0 - HLockEn Enable of output of H orizontal PLL1 Lock /unlock status signal on pin HLckVBk 0: Disabled, vertical blanking only on the pin HLckVBk 1: Enabled

12 Reserved PARAL (Parallelogram correction)

13 Reserved

14 Reserved

15 VDyCorPol

0: ”∪ " VDC-AMP (Vertical dynamic correction amplitude) 1000000 XRayReset 0: No effect 1: Reset VSyncAuto 1: On VSyncSel 0:Comp 1:Sep SDetReset 0: No effect 1: Reset HMoiMode 0: Internal 1: External PLL1Pump 1: Fast 0: Slow PLL1InhEn 1: On HLockEn 1: On 17 TV 0: Off(46) TH 0: Off(46) TVM 0: Off(46) THM 0: Off(46) BOHEdge 0: Falling HBOutEn 0: Disable VOutEn 0: Disable BlankMode 1: Perm. READ MODE (SLAVE ADDRESS = 8D) XX (45) HLock 0: Locked 1: Not locked VLock 0: Locked 1: Not lock. XRayAlarm 1: On 0: Off Polarity detection Sync detection HVPol 1: Negative VPol 1: Negative VExtrDet 0: Not det. HVDet 0: Not det. VDet 0: Not det. Sad D7 D6 D5 D4 D3 D2 D1 D0

En able of Inhibition of horizontal PLL1 during extracted vertical synchronization pulse 0: Disabled, PLL1 is never inhibited 1: Enabled Sad16/D2 - PLL1Pump Horizontal PLL1 charge Pump current 0: Slow PLL1, low current 1: Fast PLL1, high current Sad16/D3 - HMoiMode H orizontal Moiré Mode . In position “Internal”, the H-moiré signal affects timing of H-drive signal on HOut pin. In position “External”, the H-moiré sig- nal is output on HMoiré pin and has no effect on H-drive. In both cases, the amplitude of H-moiré signal is adjusted through I2C Bus register HMOIRE . 0: Internal 1: External Sad16/D4 - SDetReset Reset to 0 of Synchronization Detection flags VDet, HVDet and VExtrDet of status register ef- fected with ACK bit of I2C Bus data transfer into register containing the SDetReset bit. Also see description of the flags. 0: No effect 1: Reset with automatic return of the bit to 0 Sad16/D5 - VSyncSel Vertical Sync hronization input Selection be- tween the one extracted from composite HV sig- nal on pin H/HVSyn and the one on pin VSyn. No effect if VSyncAuto bit is at 1. 0: V. sync extracted from composite signal on H/HVSyn pin selected 1: V. sync applied on VSyn pin selected Sad16/D6 - VSyncAuto Vertical Sync hronization input selection Auto- matic mode. If enabled, the device automatically selects between the vertical sync extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn, based on detection mecha- nism. If both are present, the one coming first is kept. 0: Disabled, selection done according to bit VSyncSel 1: Enabled, the bit VSyncSel has no effect Sad16/D7 - XRayReset Reset to 0 of XRay flag of status register effect- ed with ACK bit of I 2C Bus data transfer into reg- ister containing the XRayReset bit. Also see de- scription of the flag. 0: No effect 1: Reset with automatic return of the bit to 0 Sad17/D0 - BlankMode Blanking operation Mode 0: Blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge (start of vertical sawtooth ramp on the VOut pin) 1: Permanent blanking - high blanking level in composite signal on pin HLckVBk is per- manent Sad17/D1 - VOutEn Vertical Output En able 0: Disabled, V offVOut on VOut pin (see 7.5 - Vertical section) 1: Enabled, vertical ramp with vertical position offset on VOut pin Sad17/D2 - HBOutEn H orizontal and B + Output En able 0: Disabled, levels corresponding to “power transistor off” on HOut and BOut pins (high for HOut, low for BOut). 1: Enabled, horizontal deflection drive signal on HOut pin providing that it is not inhibited by another internal event (activated XRay protection). B+ drive signal on BOut pin. Programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and of B+ DC/DC convertor if this is in ex- ternal sawtooth configuration. Sad17/D3 - BOHEdge Selection of Edge of H orizontal drive signal to phase B + drive O utput signal on BOut pin. Only applies if the bit BOutPh is set to 1, otherwise BOHEdge has no effect. 0: Falling edge 1: Rising edge Sad17/D4,D5,D6,D7 - THM , TVM , TH , TV Test bits. They must be kept at 0 level by appli- cation S/W. Read-out flags

SadXX/D0 - VDet(47) Flag indicating Detection of V synchronization pulses on VSyn pin. 0: Not detected 1: Detected SadXX/D1 - HVDet (47) Flag indicating Detection of H or HV synchroni- zation pulses applied on H/HVSyn pin. Once the sync pulses are detected, the flag is set and latched. Disappearance of the sync signal will not lead to reset of the flag. 0: Not detected 1: Detected. SadXX/D2 - VExtrDet (47) Flag indicating Detection of Extracted Vertical synchronization signal from composite H+V sig- nal applied on H/HVSyn pin 0: Not detected 1: Detected SadXX/D3 - VPol Flag indicating Polarity of V synchronization pulses applied on VSyn pin with respect to mean level of the sync signal 0: Positive 1: Negative SadXX/D4 - HVPol Flag indicating Polarity of H or HV synchroniza- tion pulses applied on H/HVSyn pin with respect to mean level of the sync signal 0: Positive 1: Negative SadXX/D5 - XRayAlarm Alarm indicating that an event of excessive volt- age has passed on XRay pin. Can only be reset to 0 through I2C Bus bit XRayReset or by power- on reset. 0: No excess since last reset of the bit 1: At least one event of excess appeared since the last reset of the bit, HOut inhibited SadXX/D6 - VLock Status of “Lock ing” or stabilization of Vertical os- cillator amplitude to an internal reference by AGC regulation loop. 0: Locked (amplitude stabilized) 1: Not locked (amplitude non-stabilized) SadXX/D7 - HLock Status of Locking of H orizontal PLL1 0: Locked 1: Not locked Note 47: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last reset (by means of the SDetReset I2C Bus bit). This is to be taken into account by application S/W in a way that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided between reset of the flag through SDetReset bit and validation of information provided in the flag after read- out of status register.

BUS CONTROL REGISTER MAP on page 21). Figure 1. Supply voltage monitoring nals, causing adverse effects like e.g. jitter. signal and the Stop Condition. working on principle of integration, see Figure 3.

and EHT each regulated separately). Figure 10. Control of HOut and BOut at start/stop at nominal Vcc chapter TYPICAL OUTPUT WAVEFORMS ). scF pin in order to allow for further filtration. frequency difference and on the capacitor value. L(VAGCCap) , the lower this difference.

bus control. Vertical moiré is superimposed. mean output value) between particular devices. Figure 11. Vertical section block diagram

2 Synchro

20 VAGCCap

10.5 - EW DRIVE SECTION The goal of the EW drive section is to provide, on pin EWOut , a waveform which, used by an exter- nal DC-coupled power stage, serves to compen- sate for those geometry errors of the picture that are symmetric versus vertical axis across the mid- dle of the picture. The waveform consists of an adjustable DC value, corresponding to horizontal size, a parabola of 2nd order for “pin cushion” correction, a linear for “key- stone” correction and independent half-parabolas of 4th order for top and bottom corner corrections. All of them are adjustable via I 2C bus, see I2C BUS CONTROL REGISTER MAP on page 21 chapter. Refer to Figure 12, Figure 13 and to chapter TYP- ICAL OUTPUT WAVEFORMS . The correction waveforms have no effect in the vertical middle of the screen (if the VPOS control is adjusted to its medium value). As they are summed, the resulting waveform tends to reach its maximum span at top and bottom of the picture. The voltage at the EWOut is top and bottom limited (see parameter V EW ). According to Figure 13, especially the bot- tom limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical since the parabola component must always be applied. As all the components of the resulting correction waveform are generated from the out- put vertical deflection drive waveform, they all track with real vertical amplitude and position (in- cluding breathing compensation), thus being fixed vertically on the screen. They are also affected by C- and S-corrections. The sum of components oth- er than DC is affected by value in HSIZE I2C bus control in reversed sense. Refer to electrical spec- ifications for value. The DC value, adjusted via HSIZE control, is also affected by voltage on HE- HTIn input, thus providing a horizontal breathing compensation (see electrical specifications for val- ue). The resulting waveform is conditionally multi- plied with voltage on HPLL1F, which depends on frequency. Refer to electrical specifications for val- ue and more precision. This tracking with frequen- cy provides a rough compensation of variation of picture geometry with frequency and allows to fix the adjustment ranges of I 2C bus controls through- out the operating range of horizontal frequencies. It can be switched off by EWTrHFr I2C bus bit (off by default). The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is routed to EWOut output, with an internal resistor to ground.

Figure 12. Geometric corrections’ schematic diagram

Figure 13. EWOut output waveforms plication (e.g. dynamic focus). tial interference into the picture. Its operation is similar to that of standard UC3842. sistor open-collector is routed out to the BOut pin.

0 TVR TVR TVR0 0

pulse generated by the monostable trigger. Figure 14. DC/DC converter controller block diagram

10.8 - MISCELLANEOUS 10.8.1 - Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs and X-ray protection. For supply voltage supervision, refer to paragraph Power supply and voltage references on page 25 and Figure 1. A schematic diagram putting togeth- er all safety functions and composite PLL1 lock and V-blanking indication is in Figure 15. 10.8.2 - Soft start and soft stop functions For soft start and soft stop features for H-drive and B-drive signal, refer to paragraph Soft-start and soft-stop on H-drive on page 29 and sub chapter- DC/DC CONTROLLER SECTION on page 34, re- spectively. See also the Figure 10. Regardless why the H-drive or B-drive signal are switched on or off (I2C bus command, power up or down, X-ray protection), the signals always phase-in and phase-out in the way drawn in the figure, the first to phase-in and last to phase-out being the H-drive signal, which is to better protect the power stages at abrupt changes like switch-on and off. The tim- ing of phase-in and phase-out only depends on the capacitance connected to HPosF pin which is virtually unlimited for this function. Yet it has a dual function (see paragraph PLL1 on page 26), so a compromise thereof is to be found. 10.8.3 - X-ray protection The X-ray protection is activated if the voltage lev- el on XRay input exceeds V ThrXRay threshold. As a consequence, the H-drive and B-drive signals on HOut and BOut outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive X-ray condition detec- tion at short parasitic spikes. The XRayAlarm I bus flag is set to 1 to inform the MCU. This protection is latched; it may be reset either by VCC drop or by I2C bus bit XRayReset (see chap- ter I2C BUS CONTROL REGISTER MAP on page 21).

Figure 15. Safety functions - block diagram

levels and the HLckVBk configuration in Figure 16. Figure 16. Levels on HLckVBk composite output

Figure 17. Ground layout recommendations

Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. BISense16 12V 12V

18 VEHTIn

Figure 36. Figure 37. Figure 38. Figure 39.

32 VDyCor

30 SCL

12 - PACKAGE MECHANICAL DATA

32 PINS - PLASTIC SHRINK

Dimensions Millimeters Inches A1 0.508 0.020 e 1.778 0.070 eA 10.16 0.400 eB 12.70 0.500 eA eB E D 32 17 161 Stand-offeB1B AL C

August 2003 Version 1.0 Document created from version 1.1 of TDA9118.

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