STV8267DSX

STV8247 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Rev. 3 Key Features ■ Full-Automatic Multi-Standard Demodulation

• B / G / I / L / M / N / D / K Standards
• Mono AM and FM
• FM 2-Carrier (German and Korean Zweiton) and NICAM ■ Multi-Channel Capability
• 3 I²S digital inputs, S/PDIF (in/out)
• 5.1 analog outputs
• Dolby® Pro Logic®
• Dolby® Pro Logic II® ■ Sound Processing
• ST royalty-free processing: ST WideSurround, ST OmniSurround, ST Dynamic Bass, SRS® WOW™, SRS® TruSurround XT™ which is Virtual Dolby® Surround and Virtual Dolby® Digital compliant
• Independent Volume / Balance for Loudspeakers and Headphone
• Loudspeakers: Smart Volume Control (SVC), 5-band equalizer and loudness
• Headphone: Smart Volume Control (SVC), Bass- Treble, Loudness and SRS® Tr uBass™ ■ Analog Audio Matrix
• 4 stereo inputs
• 3 stereo outputs
• THRU mode ■ Audio Delay for Audio Video Synchronization
• Embedded stereo delay up to 120 ms for lip-sync function (up to 180 ms for tuner input)
• Independent delay on headphone and loudspeaker channels The STV82x7 family, based on audio digital signal processors (DSP), performs high quality and advanced dedicated digital audio processing.These devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for European and Asian terrestrial TV broadcasts. Virtual or true, multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. Starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the STV82x7 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment. Typical Applications
• Analog and digital TV with virtual surround sound
• Analog and digital TV with multi-channel surround sound
• DVD and HDD recorders
• “Palm size” portable TV STV82x7 © 2004 SRS Labs, Inc. All rights reserved, SRS and the SRS logo are registered trademarks of SRS Labs, Inc. “Dolby”, “Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. STV82x7 Digital Audio Decoder/Processor for A2 and NICAM Television/Video Recorders

LS_C LS_SUB Output Analog Audio Matrix Input Analog Audio Matrix Audio A/D I²C Interface Clock Generator Power Supply Management Stereo Audio DAC Headphone Volume, Balance, Loudness, Smart Volume Control, Loudspeakers Volume, Equalizer, Balance, ST WideSurround, ST Dynamic Bass, Loudness,Smart Volume Control, Digital Audio Matrix Pre-scaler I²S InterfaceControl Logic AGC Digital FM/AM NICAM FM 2-carrier IRQ I²S S/PDIF Detection Mono Input SC1_IN_L LS_L Headphone HP_LSS_L SCL SDA SIF In / Out Bass Management, Beeper SRS® WOW™ or TruSurround XT™ Digital Audio Processing Bass/Treble, SRS® Trubass™ Demodulation Stereo Audio DAC Stereo Audio DAC A/D

0.9 VRMS

2 VRMS

MONO_IN SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R Inputs CLK_SEL XTALIN XTALOUT SC1_OUT_L SCART SC1_OUT_R SC2_OUT_L SC2_OUT_R SC3_OUT_L SC3_OUT_R Outputs HP_LSS_R Headphone / Surround LS_R Loudspeakers Dolby® Pro Logic® clocksdata I²C Dolby® Pro Logic II®, ST OmniSurround,

General Description STV82x7

1 General Description

The STV82x7 is a multistandard TV sound demodulator and audio processor which integrates SRS® WOW™, SRS® TruSurround XT™, Dolby® Pro Logic®, Dolby® Pro Logic II®,Virtual Dolby® Surround (VDS) and Virtual Dolby® Digital (VDD) capability. ST advanced algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic Bass are also available in this audio sound processor. ST OmniSurround is a certified Dolby® algorithm for the Virtual Dolby® Digital (VDD) and the Virtual Dolby® Surround (VDS). When using VDD or VDS, either a Dolby® Digital or a Pro Logic® (or Pro Logic II®) decoder is mandatory respectively. This chip performs automatic multistandard analog TV stereo sound identification and demodulation (no specific I²C programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides a cost-effective solution for analog and digital TV designs. The STV82x7 is perfectly suited to current and future digital TV platforms, based on audio/video digital chips (STD2000, (DTV100 platform) and the future WorldWide iDTV one chip) which include an internal digital decoder (MPEG, Dolby® Digital...). In the case where a Dolby® Digital decoder is embedded in the audio/video digital chip, Virtual Dolby® Digital could be obtained. For the CTV100/120 platform, the device is offered as an alternative solution to the first-generation chassis that uses the STV82x6.

STV82x7 General Description Table 1: STV82x7 Version List S T V S T V S T V S T V STV8247 STV8257 STV8267 STV8277 STV8287 S T V D S T V D S X S T V S T V D S T V D S X S T V D S T V D S X S T V S T V D S T V D S X S T V D S T V D S X Demodulation AM/FM - Mono, FM 2-carrier XXXXXXXXXXXXXXXX NICAM X XXXXXXXXXXXXX Multi-Channel Capability 3 x I²S In or 1 I²S Out, S/PDIF (Pass-thru) XXX XXXXX

5.1 Analog Out for Loudspeakers XXXXXXX

Virtual Dolby® Surround XX XXXX XXXX Virtual Dolby® Digital capability1 1. Virtual Dolby Digital capability is obtained with the use of external Dolby Digital decoder (for example STD05x0). XXX XXXXX Dolby® Pro Logic® XX XX Dolby® Pro Logic II® XX Audio Processing SRS® WOW™ XX SRS® TruSurround XT™ XX XX X ST Voice, ST Dynamic Bass, ST WideSurround XXXXXXXXXXXXXXXX ST OmniSurround2 2. When using VDD or VDS with ST OmniSurround or SRS TruSurround XTTM, either a Dolby® Digital or a Pro Logic® (or Pro Logic II®) decoder is mandatory respectively. XXXXXXXXXXXX Figure 1: Package Ordering Information TQFP80 STV82x7 (Tray) STV82x7/T (Tape & Reel) Order Code: For Example: STV8257DSX/T will be delivered in Tape & Reel conditioning

General Description STV82x7

1.1 STV82x7 Overview

1.1.1 Core Features

• Single audio source processing: — IF source and/or analog stereo input (SCART) — one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S)
• SIF input signal with Automatic Gain Control (AGC)
• Digital Demodulator with automatic standard detection and demodulation for AM, FM mono, FM 2 carriers (German or Korean FM 2-carrier) and NICAM
• Audio processor working at 32 kHz, 44.1 kHz or 48 kHz with specific features: — For Loudspeakers (L, R, L S, RS, SubW, C): Dolby® Pro Logic II ® Decoder with Bass Management SRS® WOW™ or TruSurround XT™ including Virtual Dolby® Surround and Virtual Dolby® Digital ST WideSurround ST OmniSurround ST Dynamic Bass 5-band Equalizer or Bass-Treble Loudness Smart Volume Control Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation — For Headphone: SRS® Tr uBass™ Smart Volume Control Bass-Treble Loudness Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation
• Shared outputs for headphone and loudspeakers (surround channels);
• Analog matrix with: — five external inputs: four SCART inputs (2 VRMS capable) one analog mono input (0.5 VRMS) — one internal input from a digital matrix via a DAC — three external outputs (2 V RMS capable) — one internal output for the digital matrix (using an internal ADC)
• Digital matrix with: — three input modes (Demodulator/SCART, SCART only and I²S) — three stereo outputs (Loudspeakers, Headphone and SCART)
• High-end audio DAC
• S/PDIF output for connection with an external amplifier/decoder
• Internal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF output generated by the external decoder of the digital broadcast)

STV82x7 General Description

• Specific stand-by mode (Loop-through)
• Control by I²C bus (two I²C addresses)
• System PLL and Clock Generation using either a single quartz oscillator or a differential clock input

1.1.2 Software Information

The different software combinations are listed in Table 2. Note: In addition to the above sound processing, it is always possible to add ST Voice and also ST Dynamic Bass algorithms. Note: The SRS ® TruSurround® and ST OmniSurround are approved by Dolby as Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD). The SRS® TruSurround XT™ system is composed of:

• SRS® TruSurround®
• SRS® WOW™ The SRS® WOW™ system also includes:
• SRS® Dialog Clarity™
• SRS® TruBass™

1.1.3 Device Input Modes

• Demodulator and SCART Mode (with output fS = 32 kHz)
• SCART Only Mode (with output fS = 48 kHz)
• I²S Mode (with output fS = 32, 44.1 or 48 kHz) Table 2: Input/Output Software Configurations Input (Number of Channels) Output (Number of Channels)

1 ST WideSurround or

SRS® WOW™ 2 (L and R) ST WideSurround or SRS® WOW™ 2 (LT and RT) ST WideSurround or SRS® TruSurround XT™ or ST OmniSurround or Dolby® Pro Logic® + SRS® TruSurround XT™ or Dolby® Pro Logic® + ST OmniSurround Dolby® Pro Logic® 4 (+1) SRS® TruSurround XT™ or ST OmniSurround or Downmix No processing 5 (+1) SRS® TruSurround XT™or ST OmniSurround or Downmix Downmix No processing

General Description STV82x7 — External audio input interface using 3 x I²S (for decoded streams such as Dolby ® Digital and/or standard stereo streams)

1.1.4 Electrical Features

Multi Power Supply: 1.8 V, 3.3 V and 8 V. Power Consumption:

• lower than 1 W in Functional mode (full features)
• 200 mW in Loop-through mode corresponding to Switch-off of all digital blocks

1.2 Typical Applications

The STV82x7 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 2, Figure 3, Figure 4 and Figure 5). The main considerations are:

• all necessary connections between devices can be provided through the TV set,
• pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF ,
• possible application compatibility with STV82x6 (TQFP80 package) TV design,
• pin-to-pin compatibility with STV82x8 (TQFP80 package) TV design. The STV82x7 is used to process a single audio source (analog or digital). However, it is possible to process two audio sources simultaneously using an STV82x7 interconnection (two chips can be easily connected). In the case of a single audio source, it is possible to hear and record in the same time: the same audio stream can be simultaneously output on headphone, loudspeakers, S/PDIF and the SCART connectors. Note: Headphone and loudspeakers can be used simultaneously for dual-language purposes or for different sound settings (e.g. volume). In this case, certain restrictions occur (see Section 4.2: Audio Processing). For more connections, the SCART -to-SCART path can be used. The use of these full analog paths implies that the sound is not digitally processed.

STV82x7 General Description Figure 6: STV8217 Typical Application (Digital Recorder) or Tuner STV8217 Multistandard Demodulation Left Right - FM 2-carrier and NICAM MPEG Codec I²S

General Description STV82x7

1.3 Pin Descriptions a nd Application Diagrams

• AP = Analog Power
• DP = Digital Power
• I= I n p u t
• O = Output
• OD = Open-Drain
• B = Bi-Directional
• A = Analog Table 3: TQFP80 Pin Description (Sheet 1 of 3) Pin No. STV82x7 Pin Name Type (STV82x7) Function for STV82x7 (Function for STV82x6 in italic characters) STV82x6 Pin Name

1 SC1_OUT_L A SCART1 Audio Output Left AO1L

2 SC1_OUT_R A SCART1 Audio Output Right AO1R

3 VCC_H AP 8V Power for Audio I/O & ESD Not connected

4 GND_H AP High Current Ground for Audio Outputs Connected to Ground

5 SC3_OUT_L A SCART3 Audio Output Left Not connected

6 SC3_OUT_R A SCART3 Audio Output Right Not connected

7 VCC33_SC AP 3.3V Power for Audio Buffers & DAC / ADC VDDC

8 GND33_SC AP Ground for Audio Buffers & DAC / ADC GNDC

9 SC1_IN_L A SCART1 Audio Input Left AI1L

10 SC1_IN_R A SCART1 Audio Input Right AI1R

11 VREFA A

Audio Bias Voltage Decoupling 1.55V (Switched V REF decoupling pin for Audio Converters (VMCP)) VMC1

12 GND_SA AP Ground for DACs Connected to Ground

13 VBG A Bandgap Voltage Reference Decoupling 1.2V (VREF decoupling pin for Audio Converters (VMC)) VMC2

14 SC2_IN_L A SCART2 Audio Input Left AI2L

15 SC2_IN_R A SCART2 Audio Input Right AI2R

16 VCC33_LS AP 3.3V Power for Audio DACs (3.3V Power Supply for Audio Buffers and SCART) VDDA

17 GND33_LS AP Ground for Audio DACs

(Ground for Audio Buffers and SCART) GNDAH

18 SC2_OUT_L A SCART2 Audio Output Left AO2L

19 SC2_OUT_R A SCART2 Audio Output Right AO2R

20 VCC_NISO AP Polarization of the NISO (connected to 3.3V) (8V / 5V Power supply for SCART & Audio buffers) VDDH 21 VSS33_CONV AP Ground for DAC 1.8 to 3.3V Converters Connected to Ground 22 VDD33_CONV AP 3.3V Power for DAC 1.8 to 3.3V Converters (Voltage Reference for Audio buffers) VREFA

STV82x7 General Description

23 SC3_IN_L A SCART3 Audio Input Left AI3L

24 SC3_IN_R A SCART3 Audio Input Right AI3R

25 SCL_FLT A SCART Filtering Left Not connected

26 SCR_FLT A SCART Filtering Right

(Bandgap Voltage Source Decoupling) BGAP

27 LS_C A Center Output Not connected

28 LS_L A Left Loudspeaker Output LSL

29 LS_R A Right Loudspeaker Output LSR

30 LS_SUB A Subwoofer Output SW

31 HP_LSS_L A Left Headphone Output or Left Surround Output HPL

32 HP_LSS_R A Right Headphone Output or Right Surround Output HPR

33 VSS18_CONV DP Ground for Digital part of the DAC/ADC

(Substrate Analog/Digital Shield) GNDSA 34 VDD18_CONV DP 1.8V Power for Digital part of the DAC/ADC Not connected

35 HP_DET

36 ADR_SEL I Hardware Address selection for I²C Bus ADR

37 VSS18 DP Ground for Digital part Connected to Ground

38 VDD18 DP 1.8V Power for Digital part Not connected

39 SCL OD I²C Clock Input SCL

40 SDA OD I²C Data I/O SDA

41 VSS18 DP Ground for Digital part Connected to Ground

42 VDD18 DP 1.8V Power for Digital part (5V Power Regulator Control) REG

43 RST

44 S/PDIF_IN I Serial Audio Data Input

(System Clock output) SYSCK

45 S/PDIF_OUT O Serial Audio Data Output

(I²S Master Clock output) MCK 46 VDD33_IO1 DP 3.3V Power for Digital part VDD1

47 VSS33_IO1 DP Ground for Digital part GND1

48 CK_TST_CTRL D To be Grounded Not connected

49 VSS18 DP Ground for Digital part GNDSP

50 VDD18 DP 1.8V Power for Digital part Not connected

51 CLK_SEL I Clock Input Format Selection Not connected

52 XTALIN_CLKXTP I Crystal Oscillator Input or Differential Input Positive

(Crystal Oscillator Input) XTI Table 3: TQFP80 Pin Description (Sheet 2 of 3) Pin No. STV82x7 Pin Name Type (STV82x7) Function for STV82x7 (Function for STV82x6 in italic characters) STV82x6 Pin Name

General Description STV82x7

53 XTALOUT_CLKXTM O Crystal Oscillator Output or Differential Input Negative

(Crystal Oscillator Output) XTO 54 VCC18_CLK1 AP 1.8V Power for Clock PLL Analog & Crystal Oscillator 1/2 (3.3V Power supply for Analog PLL Clock) VDDP

55 GND18_CLK1 AP Ground for Clock PLL Analog & Crystal Oscillator 1/2 GNDP

56 GND18_CLK2 AP Ground for Clock PLL Digital 1/2 GND2

57 VCC18_CLK2 DP 1.8V Power for Clock PLL Digital 1/2 (3.3V Power supply for Digital core, DSPs & IO Cells) VDD2

58 VSS33_IO2 DP Ground for Digital IO pins 60 to 69 Connected to Ground

59 VDD33_IO2 DP 3.3V power for Digital IO pins 60 to 69 Not connected

60 I2S_PCM_CLK I/O I²S Slave Clock Input/Output Channel 1, 2 & 3 Not connected

61 I2S_SCLK I/O I²S Clock Input/Output Channel 1, 2 & 3 (I²S bus data

output) SDO

62 I2S_LR_CLK I/O I²S Word Select Input/Output Channel 1,2 & 3

(Stereo Detection output / I²S Bus Data input) ST/SDI

63 I2S_DATA0 I/O I²S Data Input/Output Stereo Channel 1

(I²S Bus Word Select output) WS

64 I2S_DATA1 I I²S Data Input Stereo Channel 2

(I²S Bus Clock output) SCK

65 I2S_DATA2 I I²S Data Input Stereo Channel 3

(Bus Expander Output 1) BUS1 66 VDD18 DP 1.8V Power for Digital Core & I/O Cells Pin Not connected

67 VSS18 DP Ground for Digital Core & I/O Cells Pin Connected to Ground

68 BUS_EXP O Bus Expander Function

(Bus Expander Output 2) BUS0

69 IRQ O Interrupt Request to Microprocessor IRQ

70 GND_PSUB AP Ground Substrate Connection Connected to Ground

71 VDD18_ADC DP VDD 1.8V for ADC (Digital Part) Not connected 72 VSS18_ADC DP Ground to Complement 1.8V VDD for ADC Connected to Ground

73 SIF_P A Sound IF input (positive) SIF

74 SIF_N A Sound IF input (negative) (ADC VTOP Decoupling pin) VTOP

75 GNDPW_IF AP Polarization for the IF block

(Voltage Reference for AGC Decoupling pin) VREFIF 76 VCC18_IF AP 1.8V Power for IF AGC & ADC VDDIF

77 GND18_IF AP Ground for IF AGC & ADC GNDIF

78 MONO_IN A Mono Input (for AM Mono) MONOIN

79 SC4_IN_L A SCART4 Audio Input Left Not connected

80 SC4_IN_R A SCART4 Audio Input Right Not connected

Table 3: TQFP80 Pin Description (Sheet 3 of 3) Pin No. STV82x7 Pin Name Type (STV82x7) Function for STV82x7 (Function for STV82x6 in italic characters) STV82x6 Pin Name

STV82x7 General Description Figure 7: STV82x7 Application Diagram TQFP80 CRYSTAL Address select Reset STV82x7 220 220 220 330pF 330pF 330pF 330pF 220 220 330pF 330pF 220 1.8V +3.3V +1.8V +3.3V +8V +1.8V +1.8V +3.3V 1.8V 1.8V +3.3V 10µH 1µF + 1µF + C23 47µF C75 L10 10µH +C37 1µF 470K 1µF 10µH C10 100nF C47 10µF C64 33nF C19 100nF 1µF XT1 27MHz C34 22nF R4 C70 10µH C35 100pF +C55 10µF + C61 1µF L16 100µH + C59 47µF +C39 10µF + C41 10µF IC1 SC1_OUT_L SC1_OUT_R VCC_H GND_H SC3_OUT_L SC3_OUT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R VREFA GND_SA VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_OUT_L SC2_OUT_R VCC_NISOVSS33_CONV VDD33_CONV SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HL_LSS_R VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R L17 100µH + C9 330µF C32 220nF + C60 1µF C49 10µF L18 100µH C33 100nF C42 100nF C27 100nF L12 10µH C62 33nF +C53 1µF C44 100nF + C17 10µF C13 100nF L13 100µH C57 100nF L15 100µH C36 1µF C26 100nF +C45 1µF C22 27pF 1µF +C40 10µF SL1 C14 100nF C16 470nF C66 33nF C50 100nF 1µF C15 100nF + C51 10µF C63 33nF C72 C21 27pF + C38 1µF C18 100nF C30 100nF 560 10µH +C46 1µF + C48 10µF C67 33nF L14 100µH C52 100nF+C54 1µF +C56 10µF + C43 47µF C65 33nF L11 10µH C69 33nF C74 C73 C58 100nF C71 C68 33nF C12 100nF C25 100nF C29 100nF SC3 IN Right SC1 IN Right SC2 OUT Right HP Right/LS surround Right I2S SCLK SCL I2S LR CLK LS Right I2S DATA 2 Subwoofer SC2 IN Left SC1 OUT Left IRQ I2S PCM CLK SC3 IN Left SIF SC2 IN Right I2S DATA 0 SC2 OUT Left I2S DATA 1 LS Left SC1 OUT Right BUS EXPANDER SDA SC1 IN Left HP Left/LS surround Left SC4 IN Right SC4 IN Left Mono IN SC3 OUT Left SC3 OUT Right LS Center SPDIF IN SPDIF OUT Headphone detection

General Description STV82x7 Figure 8: STV82x6/STV82x7 Compatible Application Electrical Diagram 220 STV82x6 / STV82x7 220 220 220 330pF 330pF CRYSTAL 330pF 330pF 220 Address select 220 330pF TQFP80 Reset 330pF SL3 0 ohm 10µH between 1-2 between 1-2 Not Connected Not Connected between 2-3 10µH between 2-3 10µH 270K 100µH *L13,L14 Not Connected with STV82x6 10µH L15,L16 10µH Not Connected L17,L18 L5,L6 strap Not Connected Part strap 10µH Not Connected strap Not Connected SL2 R11 Not Connected Note : comp onents with * are only mandatory in case of DOLBY certification 100µH * 100µH * R10 330 Not Connected R12 82 Not Connected R13 Not Connected 0 ohm R14 Not Connected R15 Not Connected 0 ohmR16 Not Connected0 ohm 0 ohm Not Connected 0 ohmR17 R18 R19 0 ohm Not Connected Not Connected 0 ohm C9 Not Connected 330 µF C10,C13 Not Connected 100 nF Not ConnectedC15,C18 100 nF C21,C22 22 pF 27 pF C23 Not Connected 47 µF C27,C29 C30 C31 Not Connected Not Connected 100 nF 100 nF 100 nF Not Connected C41 10 µF Not Connected C42 C43 Not Connected Not Connected 100 nF 10 µF C63 100 nF 33 nF C64,C65 Not Connected 33 nF C66,C67 Not Connected 33 nF Not Connected 33 nFC68,C69 C70,C71 Not Connected 330 pF 330 pFNot ConnectedC72,C73 C74,C75 Not Connected 330 pF C76,C77 10 µF Not Connected C78 10 µF Not Connected with STV82x7 C59 10 µF 47 µF C79 10 µF 47 µF C3 Not Connected 1 µF +3.3V +1.8V +8V +3.3V 1.8V +1.8V +3.3V +1.8V +3.3V +8V +8V +8V +1.8V +1.8V +3.3VL6 10µH R15 1µF + C76 10µF + C78 10µF 1µF + C23 47µF C75 10µH +C37 1µF 1µF 470K 10µH SL2 C73 C47 10µF C10 100nF C64 33nF C19 100nF R13 1µF C71 XT1 27MHz C34 22nF + C79 47µF R4 C70 R19 10µH 10µH R18 C35 100pF +C55 10µF + C61 1µF + C59 47µF L16 100µH +C39 10µF C69 33nF R10 330 10µH 270k + C43 10µF IC1 SC1_OUT_L SC1_OUT_R VCC_H GND_H SC3_OUT_L SC3_OUT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R VREFA GND_SA VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_OUT_L SC2_OUT_R VCC_NISO VSS33_CONV VDD33_CONV SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HL_LSS_R VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTA LIN/ CLK XTP X TALOUT/CLKX TM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R C74 C58 100nF + C60 1µF + C9 330µF C32 220nF L17 100µH C63 + C41 10µF C49 10µF C14 100nF L18 100µH C33 100nF C42 100nF C27 100nF 10µH C62 33nF +C53 1µF + C17 10µF C44 100nF C13 100nF L13 100µH C57 100nF L15 100µH C36 1µF C26 100nF +C45 1µF L11 10µH C22 +C40 10µF 1µF SL1 C12 100nF C66 33nF C68 33nF C16 470nF C50 100nF C29 100nF R17 1µF C25 100nF C15 100nF + C51 10µF C72 C21 + C38 1µF C18 100nF R16 + C77 10µF R12 C30 100nF C31 100nF 10µH 560 C65 33nF SL3 +C46 1µF + C48 10µF R11 R14 C67 33nF L14 100µH C52 100nF+C54 1µF +C56 10µF SC2 IN Right SCL SPDIF IN SC2 IN Left SC1 OUT Right SC4 IN Right SIF LS Left I2S SCLK / SDO Subwoofer LS Center HP Left/LS surround Left SC3 IN Left SC3 OUT Right I2S DATA 1 / SCK HP Right/LS surround Right I2S DATA 2 / BUS1 SC3 IN Right SC1 IN Left SC3 OUT Left I2S PCM CLK SC2 OUT Left SC2 OUT Right LS Right Headphone detection SDA Mono IN IRQ I2S DATA 0 / WS I2S LR CLK / SDI SC1 IN Right SPDIF OUT BUS EX PANDER / BUS0 SC4 IN Left SC1 OUT Left

STV82x7 General Description Figure 9: STV82x7/STV82x8 Compatible Application Electrical Diagram (TQFP80) SCL Headphone detection HP Left/LS surround Left LS Right Subwoofer LS Left SIF LS Center SPDIF IN SPDIF OUT IRQ BUS EXPANDER Mono IN I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK SC1 OUT Right SC1 OUT Left SC1 IN Right SC4 IN Right SC1 IN Left SC4 IN Left SC2 IN Right SC2 IN Left SC3 IN Right SC3 IN Left SC2 OUT Right SC3 OUT Left SC3 OUT Right SC2 OUT Left HP Right/LS surround Right SDA +3.3V +1.8V +1.8V +3.3V +1.8V 1.8V +8V +3.3V +3.3V 1.8V 1.8V Reset STV82x7 or STV82x8 Note : components with * are only mandatory in case of Dolby certification TQFP80 CRYSTAL 220 220 220 330pF 330pF 330pF 330pF 220 220 330pF 330pF Address select 220 Table 1 : SL1 configuration STV82x7 : STV82x8 : between 1 and 2 (pin 20 connected to ground) between 2 and 3 (pin 20 connected to 3.3V) L11 10µH L11 10µH C73C73 10µH 10µH +C37 1µF +C37 1µF C32 220nF C32 220nF C67 33nF C67 33nF C68 33nF C68 33nF R4R4 L16 100µH L16 100µH C57 100nF C57 100nF C66 33nF C66 33nF 1µF+ 1µF + C9 330µF + C9 330µF 1µF+ 1µF 470K 470K 1µF+ 1µF XT1 27MHz XT1 27MHz L12 10µH L12 10µH C71C71 C64 33nF C64 33nF C70C70 R5R5 C15 100nF C15 100nF SC1_OUT_L 1SC1_OUT_R 2VCC_H 3GND_H 4SC3_OUT_L 5SC3_OUT_R 6VCC33_SC 7GND33_SC 8SC1_IN_L 9SC1_IN_R 10VREFA 11GND_SA 12VBG 13SC2_IN_L 14SC2_IN_R 15VCC33_LS 16GND33_LS 17SC2_OUT_L 18SC2_OUT_R 19VCC_NISO 20 VSS33_CONV21 VDD33_CONV22 SC3_IN_L23 SC3_IN_R24 SCL_FLT25 SCR_FLT26 LS_C27 LS_L28 LS_R29 LS_SUB30 HP_LSS_L31 HL_LSS_R32 VSS18_CONV33 VDD18_CONV34 HP_DET35 ADR_SEL36 VSS1837 VDD1838 SCL39 SDA40 VSS1841 VDD1842 RST_N43 SPDIF_IN44 SPDIF_OUT45 VDD33_IO46 VSS33_IO47 CK_TST_CTRL48 VSS1849 VDD1850 CLK_SEL51 XTALIN/CLKXTP52 XTALOUT/CLKXTM53 VCC18_CLK154 GND18_CLK155 GND18_CLK256 VCC18_CLK257 VSS33_IO58 VDD33_IO59 I2S_PCM_CLK60 I2S_SCLK61 I2S_LR_CLK62 I2S_DATA063 I2S_DATA164 I2S_DATA265 VDD1866 VSS1867 BUS_EXP68 IRQ 69 GND_PSUB70 VDD18_ADC71 VSS18_ADC72 SIF_P73 SIF_N74 GND_PWIF75 VCC18_IF76 GND18_IF77 MONO_IN78 SC4_IN_L79 SC4_IN_R80 IC1IC1 R6R6 C33 100nF C33 100nF C34 22nF C34 22nF L10 10µH L10 10µH L17 100µH L17 100µH C14 100nF C14 100nF C22 27pF C22 27pF + C61 1µF + C61 1µF C25 100nF C25 100nF C50 100nF C50 100nF L14 100µH L14 100µH + C60 1µF + C60 1µF C58 100nF C58 100nF C18 100nF C18 100nF + C48 10µF + C48 10µF 10µH 10µH +C56 10µF +C56 10µF C30 100nF C30 100nF SL1SL1 + C23 47µF + C23 47µF +C39 10µF +C39 10µF C62 33nF C62 33nF C69 33nF C69 33nF + C17 10µF + C17 10µF C63 33nF C63 33nF R9R9 C26 100nF C26 100nF + C43 47µF + C43 47µF +C55 10µF +C55 10µF 10µH 10µH 560 560 R7R7 C12 100nF C12 100nF C35 100pF C35 100pF C44 100nF C44 100nF C29 100nF C29 100nF +C45 1µF +C45 1µF C52 100nFC52 100nF + C41 10µF + C41 10µF + C51 10µF + C51 10µF R12 10K R12 10K 1µF+ 1µF +C54 1µF +C54 1µF C75C75 R8R8 C49 10µF C49 10µF L15 100µH L15 100µH SL1 ( see Table 1)SL1 ( see Table 1) C36 1µF C36 1µF L13 100µH L13 100µH C21 27pF C21 27pF C74C74 R11 10K R11 10K C47 10µF C47 10µF C42 100nF C42 100nF +C53 1µF +C53 1µF 1µF+ 1µF C19 100nF C19 100nF + C38 1µF + C38 1µF C65 33nF C65 33nF + C59 47µF + C59 47µF 1µF+ 1µF C13 100nF C13 100nF L18 100µH L18 100µH 10µH 10µH +C46 1µF +C46 1µF C10 100nF C10 100nF +C40 10µF +C40 10µF C72C72 C27 100nF C27 100nF C16 470nF C16 470nF

2 System Clock

The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer can be used in one of two modes:

• In Mode 1, it is used by the demodulator, and the frequecy is 49.152 MHz.
• In Mode 2, it is used by the I²S input and is synchronous with the input frequency (fS = 32, 44.1 or 48 kHz) and the frequency is 49.152 MHz (for fS = 32 or 48 KHz) or 45.1584 MHz (for fS = 44.1 KHz). The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and 150 MHz depending on the application (around 106 MHz at reset value). The default values are designed for a standard 27-MHz reference frequency provided by a stable single crystal or an external differential clock signal (for example, from the STV35x0) depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal, 0 means an external differential clock). The 27-MHz value is the recommended frequency for minimizing potential RF interference in the application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV picture and sound IFs (PIF/SIF) and Band-I RF . Note: A change in the reference frequency is compat ible with other default I²C programming values, including those of the built-in Automatic Standard Recognition System.

STV82x7 Digital Demodulator

3 Digital Demodulator

The Digital Demodulator (see Figure 10) is composed of two channels. The first channel demodulates an FM or an AM signal. The second channel demodulates FM 2-carrier or NICAM signals (stereo demodulation). All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the correct sound standard. Channels can also be programmed manually via the I²C interface for very specific standards not included among the known standards.

3.1 Sound IF Signal

The Analog Sound Carrier IF is connected to the STV82x7 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a gain value allowing for a wide range of SIF input levels and is activated for all standards, except L/L ’. In this particular case, the sound carrier is AM-modulated and an automatic level adjustment would only damage the transmitted audio signal. A preset I²C parameter is provided to define the gain of the AGC used in Manual mode (Registers AGC_CTRL and AGC_GAIN). Note: For optimum AM demodulation performance, it is recommended to use the MONO Input. Figure 10: Demodulator Block Diagram Mixer Mixer DCO2 + Channel Filter FIR1 Channel Filter FIR2 AM Demodulator FM Demodulator FM Demodulator DQPSK Demodulator AUTOSTD AGC Control SIF NICAM Decoder DCO1+ Zweiton A/D NICAM L NICAM R AM/FM Mono AM FML FM Stereo AUTOSTD_CTRL (8Ah) AUTOSTD_STANDARD_DETECT (8Bh) AUTOSTD_STEREO_DETECT (8Ch) AUTOSTD_STATUS (8Eh) DEMOD_STAT(0Dh) ZWT_STAT (42h) NICAM_STAT(3Fh) CAROFFSET1 (22h) CAROFFSET2 (3Ah) Channel 1 = Mono Left Channel 2 = Stereo/Mono Right AGC_CTRL (0Eh) AGC_GAIN (0Fh) (To Sound Preprocessing) (To Sound Preprocessing) (To Sound Preprocessing) Decoder AGC Amp AUTOSTD_TIMERS (8Dh)

Digital Demodulator STV82x7

3.2 Demodulation

The demodulation system operates by default in Automatic mode. In this mode, the STV82x7 is able to identify and demodulate any TV sound standard including NICAM and A2 systems (see Table 4) without any external control via the I²C interface. It consists of the two demodulation channels (Channel 1 = Mono Left and Channel 2 = Mono Right/Stereo) to simultaneously process two sound carriers in order to handle all transmission modes (stereo and up to three mono languages). The built-in Automatic Standard Recognition System (Autostandard) automatically programs the appropriate bits in the I²C registers which are forced to Read-only mode for users (see Section 12.1). The programming is optimized for each standard to be identified and demodulated. Each mono and stereo standard can be removed (or added) from the List of Standards to be recognized by programming registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT, respectively. The identified standard is displayed in register AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag must be reset by re-programming the MSBs of register AUTOSTD_CTRL while checking the detected standard status by reading registers AUTOSTD_STATUS, NICAM_STAT and ZWT_STAT. Moreover, the detection of Stereo mode during demodulation is also flagged in register AUTOSTD_STATUS. Important: L/L ’ and D/K standards cannot be automatically processed because the same frequency is used for the MONO carrier. An exclusive L/DK selection must programmed in register AUTOSTD_CTRL. This may be externally controlled by detecting the RF modulation sign, which is negative for all TV standards except L/L ’. To recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C controls are provided without interfering with the Automatic Standard Recognition System (Autostandard). DK-NICAM Overmodulation Recovery: Four different FM deviation ranges can be selected (via register AUTOSTD_CTRL) for the DK standard while the Autostandard system remains active. The maximum FM deviation is 500 kHz in DK Mono mode and 350 kHz in DK NICAM mode (limited by overlapping FM and NICAM spectrum values). The demodulated signal peak level (proportional to the FM deviation) is detected by the Peak Detector and written to registers PEAK_DET_L and PEAK_DET_R. This value is used to implement Automatic Overmodulation Detection via an external I²C control. Important: Only the selection of the 50 kHz FM deviation standard is compatible with the other DK- A2* standards (DK1, DK2 or DK3). These standards must be removed from the list of standards (registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT) when programming larger FM deviations reserved only for DK-NICAM standards. Table 4: Recognized Standards System Sound Type Type Name Carrier 1 (MHz) Carrier 2 (MHz) FM Deviation De- emphasis Roll -off (%) Pilot Frequency (kHz)Nom. Max. Over B/G FM Mono 5.5 FM/NICAM 5.5 5.850 27 50 80 J17 40 FM 2-Carrier A2 5.5 5.742 27 50 80 50 µs 54.6875 D/K FM Mono 6.5 FM/NICAM 6.5 5.850 27 50 80 J17 40 D/K1 FM 2-Carrier A2* 6.5 6.258 50 µs 54.6875

STV82x7 Digital Demodulator For Chinese TV transmissions (DK-NICAM) which are subject to overmodulation, different FM deviations are proposed for sound demodulation. Sound Carrier Frequency Offset Recovery: Both Mono and Stereo IF Carrier frequencies can be adjusted independently (registers CAROFFSET1 and CAROFFSET2) within a large range (up to 120 kHz for standard mono FM deviations) while the Automatic Standard Recognition System remains active. The frequency offset estimation is written in registers DC_REMOVAL_L and DC_REMOVAL_R (Mono Left / Channel 1 and Mono Right / Channel 2, respectively) and can be used to implement the Automatic Frequency Control (AFC) via an external I²C control. Manual Mode: If required, the Automatic Standard Recognition System system can be disabled (Manual mode) and the user can control all registers including those only controlled by the Automatic Standard Recognition System function when active. Manual mode is selected in register AUTOSTD_STANDARD_DETECT (bit LDK_SCK, I_SCK, BG_SCK and MN_SCK set to 0). D/K2 FM 2-Carrier A2* 6.5 6.742 50 µs 54.6875 D/K3 FM 2-Carrier A2* 6.5 5.742 50 µs 54.6875 I FM Mono 6.0 FM/NICAM 6.0 6.552 27 50 80 J17 100 L AM/NICAM 6.5 5.850 J17 40 M/N FM Mono 4.5 15 27 50 75 µs FM 2-Carrier A2+ 4.5 4.724 15 27 50 75 µs 55.069 Table 4: Recognized Standards (Continued) System Sound Type Type Name Carrier 1 (MHz) Carrier 2 (MHz) FM Deviation De- emphasis Roll -off (%) Pilot Frequency (kHz)Nom. Max. Over

Dedicated Digital Signal Processor (DSP) STV82x7

4 Dedicated Digital Signal Processor (DSP)

A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic.

4.1 Back-end Processing

The “back-end” processing corresponds to the low frequency signal processing (32 kHz or higher frequencies) of the demodulator and other inputs (I²S, ADC). Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with “Demod + SCART” and I²S inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2+1 instead of 5+1. Figure 11: Back-end Audio Processing DC Digital Audio Matrix FM Channel1 FM Channel2 NICAM L De-emphasis Prescale Dematrix Autostandard FMFM FM Removal Prescale I²S I2S in 1 I2S in 2 I2S in 3 DC Prescale NICAM Removal DC Prescale SCART Removal NICAM R Dematrix NICAM SCART L SCART R SRC X2/X4 “I2S” Input Mode “Demod + SCART” or “SCART only” Input Modes DownMix LS2 HP2 SCART2 LS2 to 6 HP2 SCART2 Stereo Peak Detector: 9D, bit 7 = 0Stereo Peak Detector: 9D, bit 7 = 0 (L and R) (L and R) (L and R) (L,R,C,LFE,Ls,Rs) (L and R) (L and R) De-emphasis NICAM Stereo Peak Detector: 9D, bit 7 = 1 Stereo Peak Detector: 9D, bit 7 = 1

STV82x7 Dedicated Digital Signal Processor (DSP) The main features depend on the path:

• FM Channel — DC Removal —P r e s c a l i n g — De-emphasis (50 or 75 us) — Stereo Dematrix
• NICAM Channel — DC Removal —P r e s c a l i n g — De-emphasis (J17) — Dematrix
• Input SCART Channel — DC Removal —P r e s c a l i n g
• Input I²S Channel — I²S Prescaling
• Digital Audio Matrix — Audio Channel Multiplexer between the different sources (IF , I²S, SCART) towards all outputs (S/PDIF , LS, HP or SCART).
• Autostandard management — device configuration depending on the standard to be detected — freeze the device when a standard is detected — once a standard detected, check that there is no change in the detection status — set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection)
• SCART — Downmixing: L T / RT or L0 / R0 (see AC-3 specification) — Soft Mute

4.2 Audio Processing

The following software is provided for main loudspeakers (L, R, C, LS, RS, SubW):

• Downmix
• Dolby® Pro Logic II® Decoder (LT, RT → L, R, C, Ls, Rs, SubW) with Bass Management
• ST WideSurround, ST OmniSurround, SRS® WOW™ or SRS® TruSurround XT® (certified Virtual Dolby® Surround and Virtual Dolby® Digital)
• ST Dynamic Bass
• Smart Volume Control (SVC)
• 5-band Equalizer or Bass-Treble
• Loudness
• Volume with independent channels (Smooth Volume Control)
• Master Volume Control
• Mute/soft-mute

Dedicated Digital Signal Processor (DSP) STV82x7

• Balance
• Beeper
• Pink Noise Generator (used to position the loudspeakers)
• Programmable Delay for each loudspeaker
• Adjustable Delay for “lip sync” up to 120 ms (to compensate audio/video latency) in SCART Only Mode and up to 180 ms in Demodulator and SCART Mode The following software is provided for the headphone or auxiliary output:
• Downmix
• SRS® TruBass™
• Smart Volume Control (SVC)
• Bass/Treble
• Loudness
• Independent Volume for each channel (Smooth Volume Control)
• Soft Mute
• Balance
• Beeper
• Adjustable Delay for “lip sync” up to 120 ms (to compensate audio/video latency) in SCART Only Mode and up to 180 ms in Demodulator and SCART Mode The following software is provided for SCART or S/PDIF outputs:
• Downmix
• Soft Mute

STV82x7 Dedicated Digital Signal Processor (DSP) Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs S/PDIF Output SCART Output Headphone Output LS Output Center Output Subwoofer Output Surround Output Loud- Bass / Loud-Bass/ Treble Treble or 5 bands Equalizer Volume Volume Volume S S Beeper 1to2/2to2 SVC Digital Soft Mute Digital Soft Mute Digital Soft Mute Digital Soft Mute Digital Soft Mute Balance Volume Balance Volume Balance and SVC output Select L R LFE C Ls Rs L HP R HP Bass Mgmt. Volume Digital Soft MuteBalance Digital Soft Mute S/PDIF Select SRS R SCART L SCART Delay Delay ST Wide Surround Dolby SRS Pro Logic Decoder TruSurround Adjustable Adjustable S/PDIF Input XT Pro Logic II or or ST OmniSurnd ness ness ST Dynamic BassTruBass SRS Tr uBass

Dedicated Digital Signal Processor (DSP) STV82x7

4.3 ST WideSurround

STV82x7 offers three preset ST WideSurround Sound effects on the Loudspeakers path:

• Music, a concert hall effect
• Movie, for films on TV
• Simulated Stereo, which generates a pseudo-stereo effect from mono source “ST WideSurround Sound” is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (Autostandard) depending on the detected stereo or mono source. By default, “Movie” is selected for Surround mode. This value may be changed to “Music” by the STSRND_MODE bit in the STSRND_CONTROL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (STSRND_LEVEL) and ST WideSurround Frequency (STSRND_FREQ) registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice Predominancy in Movie mode.

4.4 ST OmniSurround

STV82x7 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers path: “ST OmniSurround” will recreate a multi-channel spatial sound environment using only the Left and Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE). ST Voice will allow you to enhance the voice content of your program to increase the intellegibility and the presence of the sound.

4.5 Dolby Pro Logic II Decoder

Dolby® Pro Logic II® is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of Dolby® Surround program material such as DVD movies and TV shows. It is even possible to decode standard stereo signals like music or non encoded movies. Furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. The Dolby® Pro Logic II® decoder is also able to emulate the former Dolby® Pro Logic® decoder in a specific mode.

4.6 Bass Management

This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and bandwidth. Speakers capable of reproducing the entire frequency range will be referred to as “full range speakers”, then signals sent to full range speaker will be full bandwidth (no filtering).

STV82x7 Dedicated Digital Signal Processor (DSP) Speakers that have limited bass handling capabilities will be referred to as “satellite speakers”, then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82x7, five output configuration modes have been implemented according to “Dolby Digital Consumer Decoder” specifications. They are described below.

4.6.1 Bass Management Configuration 0

In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 13 offers this possibility. Figure 13: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state) R L C Ls Rs LFE L R C Ls Rs SubW+ -15 dB -5 dB

Dedicated Digital Signal Processor (DSP) STV82x7

4.6.2 Bass Management Configuration 1

Configuration 1, shown in Figure 14, assumes that all five speakers are not full range and that all of the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel is attenuated by 5dB to maintain the proper mixing ratio. Figure 14: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state) R L C Ls Rs LFE L R C Ls Rs SubW+-5 dB -15 dB

STV82x7 Dedicated Digital Signal Processor (DSP)

4.6.3 Bass Management Configuration 2

Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the full range speakers (Left, Right). Figure 15: Bass Management Configuration 2 (all switches indicate their reset state) SubW C L R Ls Rs LFE L C R Ls Rs Level Adjustment OFF Switch Subwoofer ON Switch +12 dB -1.5 dB -12 dB +12 dB -12 dB -12 dB -1.5 dB -12 dB -12 dB -15 dB -5 dB

Dedicated Digital Signal Processor (DSP) STV82x7

4.6.4 Bass Management Configuration 3

The third configuration, shown in Figure 16, assumes that all speakers except the center are full range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to provide more flexibility to this configuration, a switch will offer an option which will produce a subwoofer channel by the LFE channel. When the Subwoofer Switch is OFF , the input channels will be attenuated by 8 dB. Configuration 3 is required in certain high-end products. Figure 16: Bass Management Configuration 3 (all switches indicate their reset state) C L R Ls Rs L C R Ls Rs SubWLFE -4dB -4.5dB + + + + -8dB -4dB -8dB -4dB -8dB -4dB -8dB -4dB -8dB -4dB -8dB +10dB +8dB +4dB +8dB +4dB +8dB +4dB +8dB +4dB +8dB +4dB Subwoofer ON Switch Subwoofer ON Switch Level Adjustment OFF Switch

STV82x7 Dedicated Digital Signal Processor (DSP)

4.6.5 Bass Management Configuration 4

This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF . The composite bass information is either summed back into the left and right channels or summed with the LFE channel and sent to the subwoofer output, see Figure 17.

4.7 SRS WOW and TruSurround XT

The SRS® TruSurround XT™ is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. This processing system includes the latest SRS® algorithms:

• SRS® WOW™
• SRS® TruSurround® (Multi-channel signal virtualizer)

4.7.1 SRS TruSurround

The SRS® TruSurround® is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. SRS® TruSurround® uses Head-Related Transfer Function (HRTF) -based frequency tailoring of (L/R) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. These rear channel HRTF curves have much greater peak to valley differences at center frequencies. These were chosen to cause rear channel difference signals to virtualize farther behind the listener and directed to a different virtual position as compared to front channel signals. Information that is equal (L+R) in the rear surround channels Figure 17: Implementation of the Bass Management Configuration 4 (Simplified Configuration) C L R Ls Rs L C R Ls Rs + SubWLFE -5dB -10.5dB+ -4.5dB Subwoofer ON Switch

Dedicated Digital Signal Processor (DSP) STV82x7 is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The SRS® TruSurround® is certified by Dolby Laboratories to be a Virtual Dolby® Digital and Virtual Dolby® Surround.

4.7.2 SRS WOW

The SRS® WOW™ is an a sound processing system including:

• SRS® 3D Mono/Stereo™
• SRS® Dialog Clarity™
• SRS® TruBass™

4.7.2.1 SRS 3D Mono/Stereo

This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs.

4.7.2.2 SRS Dialog Clarity

This system is used to enhance dialog perception.

4.7.2.3 SRS TruBass

The SRS® Tr uBass™ audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. For systems with a subwoofer, TruBass™ complements and enhances bass performance. Psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. By accentuating the second and higher frequency harmonics of the bass portion of a signal, TruBass™ gives the perception of greatly improved bass response. SRS® TruBass™ is implemented on loudspeakers path, headphone path or on both in parallel.

4.8 Smart Volume Control (SVC)

The Smart Volume Control regulates the audio signal level before audio processing. This regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S or SCART), its modulation (AM, FM or NICAM) and annoying volume changes (advertising, etc.). The Smart Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the threshold value. When the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0dB gain). If the input signal is too low, an addition gain of 6 dB can be provided. To personalize the action of the SVC, five parameters are available: 1. Threshold: Maximum quasi-peak level that can be expected on output 2. Peak measurement mode: Select the channe l on which the peak measurement must be performed (Left, Right, Center...) 3. Release time: Gain slope applied to the amplification phase 4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output dynamic range 5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB adjustable gain.

STV82x7 Dedicated Digital Signal Processor (DSP) The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode (L, R, LS, RS, C and SubW).

4.9 ST Dynamic Bass

STV82x7 offers dynamic bass boost processing on the Loudspeakers path: ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. 3 cutoff frequencies (BASS_FREQ) can be chosen, 100Hz, 150Hz and 200Hz to adapt the effect to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt the effect loudness. 4.10 5-Band Audio Equalizer The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the LS_EQ_ON bit in the LS_EQ_BT_CTRL register. The gain value for Band X is programmed in register EQ_BANDX_GAIN. The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register LS_EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the Loudspeakers path. Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.

4.11 Bass/Treble Control

The gain of bass and treble frequency bands for Headphone can be also tuned within a range from -12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by setting the HP_BT_ON bit in the HP_BT_CONTROL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the VOLUME_MODES (D7h) register. Figure 18: Equalizer f1 = 100 Hz, f2 = 316 Hz, f3 = 1 kHz, f4 = 3.16 kHz and f5 = 10 kHz

Dedicated Digital Signal Processor (DSP) STV82x7

4.12 Automatic Loudness Control

As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness) in steps of 0.125 dB. As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The loudness cut-off frequency is 100 Hz.

4.13 Volume/Balance Control

The STV82x7 provides a Volume/Balance Control for all output channels configuration (except for S/PDIF) with different volume level per channel (L, R, C, LS, RS, SubW, SCART). Its wide range (from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio. An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, L S, RS and SubW channels. The Volume/Balance Control can operate in one of two different modes:

• In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeakers or Headphone channels (see Figure 19) and complimentary balance control is used (see Figure 20). Figure 19: Volume Control Output Gain +11.875 dB -116 dB Mute 00h 3FFh I²C Control

STV82x7 Dedicated Digital Signal Processor (DSP)

• In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently.

4.14 Soft Mute Control

The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on output. It is available on all output channels pairs:

• S/PDIF channel (Left/Right)
• SCART channels (Left/Right)
• Loudspeakers channels (Left/Right)
• Center
• Subwoofer
• Headphone/Surround channels (Left/Right) Another soft mute (analog) is also available on each DAC output.

4.15 Beeper

The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. The Beeper operates in one of two modes:

• Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see Figure 21.
• Continuous mode (alarm application): A tone with a programmable long duration is generated. Its start and stop controls must be programmed by I²C, see Figure 22. The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON. Beeper parameters are controlled in register BEEPER_MODE. The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.2 Hz and 8 kHz in steps of 1 octave. Figure 20: Differential Balance Output Gain 100% Mute 200h 1FFh I²C Control (10 bits) 000h Right Channe l Left Channel

Dedicated Digital Signal Processor (DSP) STV82x7 A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs. Figure 21: Pulse Mode Figure 22: Continuous Mode

62.5 Hz < f < 8 kHz

BEEP_ON = 1 BEEP_ON = 0 T predefined 0.1, 0.25, 0.5 and 1.0 s BEEP_ON = 1 BEEP_ON = 0 T defined by I²C write

STV82x7 Analog Audio Matrix (In / Out)

5 Analog Audio Matrix (In / Out)

The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix. The SCART input matrix is an input for the digital matrix (after the ADC) which select which source will be sent to the DSP . The SCART output matrix selects the sound to output, which can be directly a SCART input or the output of the DSP . A mute function is provided to switch off the outputs. A soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix. The particularity of the matrix is to accept input signal of 2 VRMS and to have the capability to output such level. In this case, the power supply must be 8 V. The Mono audio input is able to accept signals with a 0.5 VRMS amplitude. Figure 23: SCART Input Matrix Figure 24: SCART1/2/3 Output Matrix S1in S2in S3in MONO_in Audio ADC Select Digital MatrixS4in S1in S2in S3in Stereo DAC S1out Select or Mute S4in MONO_in Soft mute

I²S Interface (In / Out) STV82x7

6 I²S Interface (In / Out)

The STV82x7 offers three input/output choices: one I²S input, three I²S inputs or one I²S output.

6.1 I²S Inputs

The STV82x7 can interface with a digital sound decoder. In this case, the digital data can be input at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data).In compliance with Dolby® specifications, only the sampling frequency is subject to restrictions. All other requirements are extracted from other various specifications. The PCMCLK (possible clock for upsampling) is provided by the master which is the digital sound decoder. A sample rate conversion (SRC) will be necessary in the second case (STV82x7 slave) in order to have a fixed frequency output from this block (either 32 kHz, 44.1 kHz or 48 kHz). Note: The SRC function is only available in single I²S input mode. The I²S interface is used in two ways depending on the package: 1. The interface with one I²S (I²S_DATA0) connection (only stereo or stereo-coded Dolby® Pro Logic®); 2. One interface with three I²S connections connected to the DSP to allow the processing of a multi-channel signal (maximum of 6 channels). Table 5: I²S Characteristics Sampling Frequency (kHz) 8, 11.025, 12,16, 22.05, 24, 32, 44.1 and 48 Data Size 16, 18*, 20*, 24*, 32 PCMCLK 512 x fS 1. means that the number is the number of effective bits but the transmission is with 32 bits. 2. 512 x f s is used by the DACs if 512 x fs is present. Figure 25: I²S Block Diagram Audio Processing SRC x 2 SRC x 4 I²S_DATA0 I²S_DATA1 I²S_DATA2 fS Input = 8 to 48 kHz fS Input = 32 to 48 kHz fS Input = 32 to 48 kHz

STV82x7 I²S Interface (In / Out) Both standard and non-standard modes are available, see Figure 26.

6.2 I²S Output

A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case the I²S_DATA0 signal and all clock signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency s) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required for the slave interface. Both standard and non-standard modes are available, see Figure 26. Note: The Input and Output modes for I²S are exclusive. Table 6: I²S Frequency Configuration I²S (Max. Number of Channels) fS Input (kHz) fS Output (kHz) after SRC SRC Use 1 (I²S_DATA0) 8 32.0 x 4 1 (I²S_DATA0) 16 32.0 x 2 3 32 32.0 No 1 (I²S_DATA0) 11.025 44.1 x 4 1 (I²S_DATA0) 22.05 44.1 x 2 3 44.1 44.1 No 1 (I²S_DATA0) 12 48.0 x 4 1 (I²S_DATA0) 24 48.0 x 2 3 48 48.0 No Figure 26: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode) I²S_SCLK 1 2 3 23 2422 MSB LSB 12 3 23 2422 MSB LSB 1 2 3 23 2422 MSB LSB 1 2 3 23 2422 MSB LSB 1 2 3 1/fs Lch RchI²S_LR_CLK (= 64fs) I²S_DATAx (standard mode) I²S_DATAx (non-standard mode)

S/PDIF Input/Output STV82x7

7 S/PDIF Input/Output

An S/PDIF output is available for connection with an external decoder/amplifier. An internal multiplexer allows selection of either the internal signal or the external signal connected on the SPDIF input (for example, the signal provided by the external MPEG audio / Dolby Digital decoder). The outputted internal signal can be selected from:

• L/R
• C/Sub
• HP or Surround
• SCART. A mute facility is also provided on the SPDIF output.

STV82x7 Power Supply Management

8 Power Supply Management

A mixed supply voltage environment requires the following voltages:

• 3.3V capable inputs/outputs for digital pins;
• 1.8V digital core;
• 8V capable inputs/outputs for analog audio interfaces (capability to output 2 VRMS for SCART requirements);
• 3.3V for stereo ADC and DAC (analog part);
• 1.8V for stereo ADC and DAC (digital part);
• 1.8V for IF ADC and AGC. These voltages will be delivered by the application with an accuracy of ±5%. For more information, refer to Section 13.3: Power Supply Data. Other specific DC voltages or features are provided:
• Voltage Reference and Biasing Generation (AGC, ADCs, DACs),
• Bandgap reference.

8.1 Standby Mode (Loop-through mode)

The STV82x7 provides a Loop-through mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required. In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H, VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs since the I²C I/O pins (SDA and SCL) of the STV82x7 are forced into a high-impedance configuration.

Additional Controls and Flag STV82x7

9 Additional Controls and Flag

This logic contains:

• the headphone detection,
• the IRQ generation, signal to be output to the MCU,
• the I²C bus expander output pin.

9.1 Headphone Detection

For headphone, the HP_DET input can be used to automatically mute the Loudspeakers and Subwoofer outputs when the HP_LS_MUTE bit is set in register HEADPHONE_CONFIG (active low). When a headphone is detected (the HP_DET pin is set to 0) and the Mute function is enabled. Each change on the HP_DET pin generates an IRQ request to the microprocessor on the IRQ pin.

9.2 IRQ Generation

Four IRQs are generated by the STV82x7. On each IRQ generation, the IRQ pin is set to 1. The pending IRQ status must be read at the I²2S address 81h and the acknowledge is done by writing 0 to this register. The four availables IRQs are: IRQ0: The identified TV sound standard is displayed in register AUTOSTD_STATUS. Each change in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset by re-programming the IRQ bit in register AUTOSTD_CTRL and then checking the detected standard status by reading registers AUTOSTD_STATUS, NICAM_STAT, and ZWT_STAT. IRQ1: This IRQ is enabled only in digital input mode. In case of I2S synchronisation loss, this IRQ is set to 1. IRQ2: This IRQ is set to 1 when the device detects any change on the HP Detection pin (Headphone connection or deconnection). IRQ3: On the STV82x7, same pins are used for both Headphone and Surround loudspeaker signal output. A change in the Headphone configuration (HP active or not active) will lead to a signal switch on those hardware pins. In order to ensure a smooth audio transition, the output is soft muted before the signal is switched. The IRQ3 is then set to 1 to advise the master processor that the signal has been switched and to request a HP/Srnd Ouput Un-Mute.

9.3 I²C Bus Expander

Pin BUS_EXP can be used to control external switchable IF SAW filters or audio switches. This pin can be directly programmed by register RESET.

10 STV82x7 Reset

All STV82x7 features are controlled via the I²C bus. The STV82x7 can be "reset" in 2 ways: 1. By Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers. 2. By Hardware via the RE SET pin: In addition to clearing all synchronous logic, the RESET input (active on the low level) resets all the I²C bus registers to the default values listed below. Table 7: RESET Default Values Function Default mode Demodulation Auto-standard ON Scanned Standards M/N, B/G, I, L/L ’ FM Deviation ± 125 kHz (Max.) Audio Outputs Automatic Mute Mode ON Loudspeaker Source Demodulated Sound Loudspeaker Volume -40 dB, differential mode, muted Loudspeaker L/R Balance L/R = 100% Subwoofer -40 dB / OFF Headphone Source Demodulated Sound Headphone Automatic Detection ON Headphone Volume -40 dB, differential mode, muted Headphone L/R Balance L/R = 100% SCART -1 out Demodulated Sound SCART -2 out SCART1 Source SCART Volume -5.5 dB, independent mode, muted I²S out OFF Audio Processing Loudspeaker/Headphone SVC OFF , 0 dB Reference Value Loudspeaker Surround OFF Loudspeaker 5-Band Equalizer OFF , 0 dB (Flat Band) Loudspeaker Loudness OFF Headphone Bass/Treble OFF , 0 dB (Flat Band) Loudspeaker/Headphone Beeper -40 dB / OFF

I²C Interface STV82x7

11 I²C Interface

11.1 I²C Address and Protocol

The STV82x7 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are used to connect two STV82x7 chips to the same I²C serial bus. The device address pairs are defined by the polarity of the ADR_SEL pin and are listed in the following table: Protocol Description

• Write Protocol
• Read Protocol
• W = Write address,
• R = Read address,
• A = Acknowledge,
• N=N o a c k n o w l e d g e .
• Sub-address is the register address pointer; this value auto-increments for both write and read. Table 8: I²C Read/Write Addresses ADR Write Address (W) Read Address (R) LOW (connected to GND1) 80h 81h HIGH (connected to VDD1) 84h 85h Start W A Sub-address A Data A .... A Data A Stop Start W A Sub-address A Stop Start R A Data A .... A Data N

STV82x7 I²C Interface

11.2 Start-up and Configuration Change Procedure

Figure 27: Flow chart Load Patch File HW_RESET bit = 1 (DSP RUN) (DSP inititialization) Device Configuration Set-up (analog or digital) HOST_RUN bit = 1 (start DSP processing) (change configuration)INIT_MEM bit = 0 (registers 85h to FFh are not reset) Clock PLLs progammation (for Crystal value different than 27 MHz) (FS1 & FS2 registers) (by I²C transfer) (bit 2 in HOST_CMD register) (bit 0 in DSP_STATUS register) HOST_RUN bit = 0 (bit 0 in DSP_RUN register) HOST_NO_INIT bit = 1 (OPTIONAL) (bit 1 in DSP_RUN register) (stop DSP processing) INIT_MEM bit ? Hardware Reset (by pin 43) Power ON NOTE: This HW reset after Power ON is mandatory to avoid bad device configuration

12 Register List

Note: The unused bits (defined as ‘Reserved’) in the I²C registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to be modified if a standard 27 MHz quartz crystal oscillator is used. The default values of the demodulator registers (from address 0Ch to 55h) are for optimum performances and any change is not recommended, except for:

• AGC_GAIN (0Fh) to adjust AGC gain for AM carrier in L/L' standard (AGC used in open loop).
• CAROFFSET1 (22h) and CAROFFSET2 (3Ah) to compensate IF carrier frequency with an out-of-standard offset.
• Soundlevel Prescaling PRESCALE_AM (94h), PRESCALE_FM (95h), PRESCALE_NICAM (96h) and PRESCALE_SCART (97h) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DET_INPUT (9Dh), PEAK_DET_L (9Eh), PEAK_DET_R (9Fh), PEAK_DET_L_R (A0h) can be used to measure internal sound level. Sound source selection for each audio output channel Loudspeakers, Headphone and SCART to be done using AUDIO_MATRIX_INPUT (A2h). In Multi-lingual mode, AUDIO_MATRIX_LANGUAGE (A4h) selects separately the language for each audio output channel. Register AUTOSTD_CTRL (8Ah) is used to select between L/L' or D/K/K1/K2/K3 standard which can be discriminated automatically. To be used also to change maximum FM deviation (125 kHz, by default) in case of wide overmodulation. AUTOSTD_STANDARD_DETECT (8Bh) and AUTOSTD_STEREO_DETECT (8Ch) to define the list of mono and stereo standards to be recognized automatically. Note: () used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format. (*) The field AGC_ERR[4:0] (AGC_GAIN) can be written by user if the bit AGC_CMD (AGC_CTRL) is set to one (by default controlled by Automatic Standard Recognition System). To be used to adjust manually the input gain of analog AGC amplifier for AM carrier (L/L').

12.1 I²C Register Map

By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Table 9. Table 9: List of I²C Registers (Sheet 1 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IC General Control CUT_ID 00h (0000 0001) 0 0 CUT_NUMBER[5:0] RESET 01h 0000 0000 BUS_EXP I²S_OUTPUT 0 EN_STBY 0 SOFT_ LRST2 SOFT_ LRST1 SOFT_RST I2S_STAT 05h (0000 0000) 0 0 0 0 0 0 LR_OFF LOCK_ FLAG I2S_SYNC_OFFSET 06h (0000 0000) RESERVED Clocking 1 SYS_CONFIG 07h 0000 0000 I2S_CH_NB[1:0] INPUT_FREQ[3:0] INPUT_CONFIG[1:0] FS1_DIV 08h 0001 0010 EN_PROG 0 NDIV1[1:0] 0 SDIV1[2:0] FS1_MD 09h 0001 0001 0 0 0 MD1[4:0] FS1_PE_H 0Ah 0011 0110 PE_H1[7:0] FS1_PE_L 0Bh 0000 0000 PE_L1[7:0] Demodulator DEMOD_CTRL 0Ch 0000 0110 0 0 FAR_MODE GAP_MODE AM_SEL DEMOD_MODE[2:0] DEMOD_STAT 0Dh (0000 0000) 0 0 0 QPSK_LK FM2_CAR FM2_SQ FM1_CAR FM1_SQ AGC_CTRL 0Eh 0001 0001 AGC_ CMD 0 0 AGC_REF[2:0] AGC_CST[1:0] AGC_GAIN 0Fh (0000 0000) 0 AGC_ERR[4:0] SIG_OVER SIG_ UNDER DC_ERR_IF 10h (0000 0000) DC_ERR[7:0] Demodulator Channel 1 CARFQ1H 12h 0011 1110 CARFQ1[23:16] CARFQ1M 13h 1000 0000 CARFQ1[15:8] CARFQ1L 14h 0000 0000 CARFQ1[7:0] FIR1C0 15h 0000 0000 FIR1C0[7:0] (S) FIR1C1 16h 1111 1110 FIR1C1[7:0] (S) FIR1C2 17h 1111 1100 FIR1C2[7:0] (S) FIR1C3 18h 1111 1101 FIR1C3[7:0] (S) FIR1C4 19h 0000 0010 FIR1C4[7:0] (S) FIR1C5 1Ah 0000 1101 FIR1C5[7:0] (S) FIR1C6 1Bh 0001 1000 FIR1C6[7:0]6 (S) FIR1C7 1Ch 0001 1111 FIR1C7[7:0] (S) ACOEFF1 1Dh 0010 0011 ACOEFF1[7:0] BCOEFF1 1Eh 0001 0010 BCOEFF1[7:0] CRF1 1Fh (0000 0000) CRF1[7:0] (S) CETH1 20h 0010 0000 CETH1[7:0] SQTH1 21h 0011 1100 SQTH1[7:0]

CAROFFSET1 22h 0000 0000 CAROFFSET1[7:0] (S) Demodulator Channel 2 IAGCR 25h 1000 1000 IAGC_REF[7:0] IAGCC 26h 0000 0011 IAGC_ OFF FAR_FLT_EN MONO_FLT _EN BG_SEL MONO_PRO G IAGC_CST[2:0] IAGCS 27h (0000 0000) IAGC_CTRL[7:0] CARFQ2H 28h 0100 0100 CARFQ2[23:16] CARFQ2M 29h 0100 0000 CARFQ2[15.8] CARFQ2L 2Ah 0000 0000 CARFQ2[7:0] FIR2C0 2Bh 0000 0000 FIR2C0[7:0] (S) FIR2C1 2Ch 0000 0000 FIR2C1[7:0] (S) FIR2C2 2Dh 0000 0000 FIR2C2[7:0] (S) FIR2C3 2Eh 0000 0000 FIR2C3[7:0] (S) FIR2C4 2Fh 1111 1111 FIR2C4[7:0] (S) FIR2C5 30h 0000 0100 FIR2C5[7:0] (S) FIR2C6 31h 0001 0100 FIR2C6[7:0] (S) FIR2C7 32h 0010 0101 FIR2C7[7:0] (S) ACOEFF2 33h 1001 0000 ACOEFF2[7:0] BCOEFF2 34h 1010 1100 BCOEFF2[7:0] SCOEFF 35h 0001 1100 SCOEFF[7:0] SRF 36h (0000 0000) SRF[7:0] (S) CRF2 37h (0000 0000) CRF2[7:0] (S) CETH2 38h 0010 0000 CETH2[7:0] SQTH2 39h 0011 1100 SQTH2[7:0] CAROFFSET2 3Ah 0000 0000 CAROFFSET2[7:0] (S) NICAM NICAM_CTRL 3Dh 0000 0000 0 0 0 0 0 DIF_POL ECT MAE NICAM_BER 3Eh (0000 0000) ERROR[7:0] NICAM_STAT 3Fh (0000 0000) NIC_DET F_MUTE LOA CBI[3:0] NIC_MUTE Stereo FM ZWT_CTRL 40h 0011 0001 LRST_ TONE_OFF STD_MODE THRESH[3:0] TSCTRL[1:0] ZWT_TIME 41h 0000 0100 0 0 0 0 0 ZWT_TIME[2:0] ZWT_STAT 42h (0000 0000) 0 0 0 0 ZW_STAT_ RDY ZW_DET ZW_ST ZW_DM Analog Control ADC_CTRL 56h 0000 1000 I2S_DATA0_CTRL[1:0] 0 0 ADC_ POWER_UP ADC_INPUT_SEL[2:0] SCART1_2_OUTPUT_CTRL 57h 1010 1000 SC2_MUTE SC2_OUTPUT_SEL[2:0] SC1_MUTE SC1_OUTPUT_SEL[2:0] SCART3_OUTPUT_CTRL 58h 0000 1011 0 0 0 0 SC3_MUTE SC3_OUTPUT_SEL[2:0] Clocking 2 Table 9: List of I²C Registers (Sheet 2 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FS2_DIV 5Ah 0001 0001 0 NDIV2[1:0] 0 SDIV2[2:0] FS2_MD 5Bh 0001 0001 0 0 0 MD2[4:0] FS2_PE_H 5Ch 0101 1100 PE_H2[7:0] FS2_PE_L 5Dh 0010 1001 PE_L2[7:0] DSP Control HOST_CMD 80h 0000 0000 IT_IN_DSP 0 0 0 0 HW_RESET IRQ_STATUS 81h 0000 0000 IRQ3 (HP/Srnd unmute ready) IRQ2 (HP detected) IRQ1 (I2S sync lost) IRQ0 (autostd) SOFT_VERSION 82h (0000 0002) SOFT_VERSION[7:0] ONCHIP_ALGOS 83h (0000 0000) 0 PRO_LOGIC _SELECT NICAM I2S_INPUT TRUBASS TRU SURROUND PRO_LOGIC MULTICHANE L DSP_STATUS 84h 0000 0000 0 0 0 0 0 0 0 INIT_MEM DSP_RUN 85h 0000 0000 0 0 HOST_ NO_INIT HOST_RUN I2S_IN_CONFIG 86h 1000 1110 LOCK_ MODE_EN 0 SYNC LRCLK_STA RT LRCLK_ POLARITY SCLK_ POLARITY DATA_CFG I2S_MODE AV_DELAY 89h 0000 0000 DELAY_TIME[6:0] DELAY_ON Automatic Standard Recognition System AUTOSTD_CTRL 8Ah 0000 0001 0 0 0 FORCE_ SQUELCH SINGLE_ SHOT DK_DEV[1:0] LDK_SW AUTOSTD_STANDARD_DETECT 8Bh 0010 1111 0 NICAM_ C4_OFF NICAM_GA P_MODE NICAM_ MONO_IN LDK_SCK I_SCK BG_SCK MN_SCK AUTOSTD_STEREO_DETECT 8Ch 0001 1111 LDK_ZWT3 LDK_ZWT2 LDK_SWT1 LDK_ NICAM I_NICAM BG_ZWT BG_NICAM MN_ZWT AUTOSTD_TIMERS 8Dh 1010 0100 FM_TIME[1:0] NICAM_TIME[2:0] ZWEITON_TIME[2:0] AUTOSTD_STATUS 8Eh (0000 0000) STEREO_ ID STEREO_ OK MONO_ OK AUTOSTD_O N STEREO_SID[1:0] MONO_SID[1:0] Audio Preprocessing & Selection DC_REMOVAL_INPUT 90h 0000 0111 0 0 0 0 0 DC_SCART DC_NICAM DC_ DEMOD DC_REMOVAL_L 91h (0000 0000) DC_REMOVAL_L[7:0] (S) DC_REMOVAL_R 92h (0000 0000) DC_REMOVAL_R[7:0] (S) PRESCALE_SELECT 93h 0000 0000 0 0 0 0 0 0 0 AM_FM_ SELECT PRESCALE_AM 94h 0000 0000 0 PRESCALE_AM[6:0] (S) PRESCALE_FM 95h 0000 1100 0 PRESCALE_FM[6:0] (S) PRESCALE_NICAM 96h 0001 1010 0 PRESCALE_NICAM[6:0] (S) PRESCALE_SCART 97h 0000 0000 0 0 PRESCALE_SCART[5:0] (S) PRESCALE_I2S_0 98h 0000 0000 0 0 PRESCALE_I2S_0[5:0] (S) PRESCALE_I2S_1 99h 0000 0000 0 0 PRESCALE_I2S_1[5:0] (S) PRESCALE_I2S_2 9Ah 0000 0000 0 0 PRESCALE_I2S_2[5:0] (S) DEEMPHASIS_DEMATRIX 9Bh 0000 0000 0 0 NICAM_ DEMATRIX NICAM_ DEEMPH_ BYPASS FM_DEMATRIX[1:0] FM_DEEMPH _BYPASS FM_DEEMPH _SW Table 9: List of I²C Registers (Sheet 3 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PEAK_DET_INPUT 9Dh 0000 0000 PEAK_ LOCATION 0 PEAK_L_R_RANGE PEAK_DET_INPUT[1:0] PEAK_DET_L 9Eh 0(0000 0000) OVERLOAD_L [7:0] PEAK_L[6:0] PEAK_DET_R 9Fh 0(0000 0000) OVERLOAD_ R[7:0] PEAK_R[6:0] PEAK_DET_L_R A0h 0(0000 0000) OVERLOAD_L _R[7:0] PEAK_L_R[6:0 Matrixing AUDIO_MATRIX_INPUT A2h 0000 0000 0 0 0 0 0 SCART_ INPUT_ SOURCE HP_INPUT_ SOURCE LS_INPUT_ SOURCE AUDIO_MATRIX_CONFIG A3h 0000 0000 0 0 0 SCART_ MATRIX DEMOD_MATRIX[3:0] AUDIO_MATRIX_LANGUAGE A4h 0000 0000 MUTE_ STEREO MUTE_ ALL SCART_LANGUAGE[1:0] HP_LANGUAGE[1:0] LS_LANGUAGE[1:0] DOWNMIX_IN_MODE A6h 0000 0010 0 0 0 0 LFE_IN MIX_IN_MODE[2:0] DOWNMIX_OUT_MODE A7h 0100 1010 0 HP_MODE[1:0] SCART_MODE[1:0] MIX_OUT_MODE[2:0] DOWNMIX_DUAL_MODE A8h 0000 0000 0 DUAL_ON LS_DUAL_SELECT[1:0] SCART_DUAL_SELECT [1:0] HP_DUAL_SELECT[1:0] DOWNMIX_CONFIG A9h 0000 0001 0 0 SRND_FACTOR[1:0] CEN TER_FACTOR[1:0] LR_UPMIX NORMALIZE Audio Processing PRO_LOGIC2_CONTROL AAh 0011 1010 PL2_LFE PL2_OUTPUT_DOWNMIX[2:0] PL2_MODES[2:0] PL2_ACTIVE PCM_SRND_DELAY ABh 0000 0000 0 0 0 SNRD_DELAY[4:0] PCM_CENTER_DELAY ACh 0000 0000 0 0 0 0 CENTER_DELAY[3:0] PRO_LOGIC2_CONFIG ADh 0000 0000 0 0 0 PL2_SRND_FILTER PL2_RS_ POLARITY PL2_ PANORAMA PL2_AUTO BALANCE PRO_LOGIC2_DIMENSION AEh 0000 0000 0 PL2_C_WIDTH 0 PL2_DIMENSION PRO_LOGIC2_LEVEL AFh 0000 0000 PL2_LEVEL NOISE_GENERATOR B0h 0000 0000 10_DB_ ATTENUATE SRIGHT_ NOISE SLEFT_ NOISE SUB_ NOISE CENTER_ NOISE RIGHT_ NOISE LEFT_ NOISE NOISE_ON TRUSRND_CONTROL B1h 0000 0000 0 TRUSRND_ MONO_ SRND TRUSRND_INPUT_MODE[3:0] TRUSRND_ MODE TRUSRND_ ON TRUSRND_INPUT_GAIN B6h 0000 0000 TRUSRND_INPUT_GAIN[7:0] TRUSRND_HP_DCL B7h 0000 0000 0 0 0 0 0 DIALOG_ CLARITY_ON HEADPHONE _ON 0 TRUSRND_DC_ELEVATION B8h 0000 1100 TRUSRND_DC_ELEVATION[7:0] TRUBASS_LS_CONTROL BAh 0000 0110 0 0 0 TRUBASS_LS_SIZE[3:0] TRUBASS_ LS_ON TRUBASS_LS_LEVEL BBh 00001 1001 TRUBASS_LS_LEVEL[7:0] TRUBASS_HP_CONTROL BCh 0000 0110 0 0 0 TRUBASS_HP_SIZE[3:0] TRUBASS_ HP_ON TRUBASS_HP_LEVEL BDh 0000 1001 TRUBASS_HP_LEVEL[7:0] SVC_LS_CONTROL BEh 0000 0010 0 0 0 0 SVC_LS_INPUT[1:0] SVC_ LS_AMP SVC_ LS_ON SVC_LS_TIME_TH BFh 1001 1000 SVC_LS_TIME[2:0] SVC_LS_THRESHOLD[4:0] SVC_HP_CONTROL C0h 0000 0010 0 0 0 0 0 0 SVC_ LHP_AMP SVC_ HP_ON Table 9: List of I²C Registers (Sheet 4 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SVC_HP_TIME_TH C1h 1001 1000 SVC_HP_TIME[2:0] SVC_HP_THRESHOLD[4:0] SVC_LS_GAIN C2h 0000 0000 0 0 0 SVC_LS_MAKE_UP_GAIN[4:0] SVC_HP_GAIN C3h 0000 0000 0 0 0 SVC_HP_MAKE_UP_GAIN[4:0] STSRND_CONTROL C4h 0000 0000 STSRND_ STEREO STSRND_ MODE STSRND_ ON STSRND_FREQ C5h 0001 0101 0 0 STSRND_BASS[1:0] STSRND_MEDIUM[1:0] STSRND_TREBLE[1:0] STSRND_LEVEL C6h 1000 0000 STSRND_GAIN[7:0] OMNISURROUND_CONTROL C7h 0000 0000 ST_VOICE OMNISRND_INPUT_MODE OMNISRND_ ON ST_DYNAMIC_BASS C8h 0000 0000 BASS_LEVEL BASS_FREQ DYN_BASS_ ON LS_EQ_BT_CTRL C9h 0000 0000 0 0 0 0 0 0 LS_EQ_BT_ SW LS_EQ_ON LS_EQ_BAND1 CAh 0000 0000 EQ_BAND1[7:0] (S) LS_EQ_BAND2 CBh 0000 0000 EQ_BAND2[7:0] (S) LS_EQ_BAND3 CCh 0000 0000 EQ_BAND3[7:0] (S) LS_EQ_BAND4 CDh 0000 0000 EQ_BAND4[7:0] (S) LS_EQ_BAND5 CEh 0000 0000 EQ_BAND5[7:0] (S) LS_BASS_GAIN CFh 0000 0000 LS_BASS[7:0] (S) LS_TREBLE_GAIN D0h 0000 0000 LS_TREBLE[7:0] (S) HP_BT_CONTROL D1h 0000 0000 0 0 0 0 0 0 0 HP_BT_ON HP_BASS_GAIN D2h 0000 0000 HP_BASS[7:0] (S) HP_TREBLE_GAIN D3h 0000 0000 HP_TREBLE[7:0] (S) OUTPUT_BASS_MNGT D4h 0000 0000 BASS_ MANAGE_ON 0 SUB_ ACTIVE GAIN_ SWITCH 0 OCFG_NUM[2:0] LS_LOUDNESS D5h 0000 0100 0 LS_LOUD_THRESHOLD[2:0] LS_LOUD_GAIN_HR[2:0] LS_ LOUD_ON HP_LOUDNESS D6h 0000 0100 0 HP_LOUD_THRESHOLD[2:0] HP_LOUD_GAIN_HR[2:0] HP_ LOUD_ON Volume VOLUME_MODES D7h 1100 0111 ANTCLIP_HP _VOL_CLAMP ANTICLIP_ LS_VOL_ CLAMP SCART_ VOLUME_ MODE SRND_ VOLUME_ MODE HP_ VOLUME_ MODE LS_ VOLUME_ MODE LS_L_VOLUME_MSB D8h 1001 1000 LS_L_VOLUME_MSB[7:0] LS_L_VOLUME_LSB D9h 0000 0000 0 0 0 0 0 0 LS_L_VOLUME_LSB[1:0] LS_R_VOLUME_MSB DAh 0000 0000 LS_R_VOLUME_MSB[7:0] LS_R_VOLUME_LSB DBh 0000 0000 0 0 0 0 0 0 LS_R_VOLUME_LSB[1:0] LS_C_VOLUME_MSB DCh 1001 1000 LS_C_VOLUME_MSB[7:0] LS_C_VOLUME_LSB DDh 0000 0000 0 0 0 0 0 0 LS_C_VOLUME_LSB[1:0] LS_SUB_VOLUME_MSB DEh 1001 1000 LS_SUB_VOLUME_MSB[7:0] LS_SUB_VOLUME_LSB DFh 0000 0000 0 0 0 0 0 0 LS_SUB_VOLUME_LSB[1:0] LS_SL_VOLUME_MSB E0h 1001 1000 LS_SL_VOLUME_MSB[7:0] LS_SL_VOLUME_LSB E1h 0000 0000 0 0 0 0 0 0 LS_SL_VOLUME_LSB[1:0] LS_SR_VOLUME_MSB E2h 0000 0000 LS_SR_VOLUME_MSB[7:0] Table 9: List of I²C Registers (Sheet 5 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LS_SR_VOLUME_LSB E3h 0000 0000 0 0 0 0 0 0 LS_SR_VOLUME_LSB[1:0] LS_MASTER_VOLUME_MSB E4h 1110 1000 LS_MASTER_VOLUME_MSB[7:0] LS_MASTER_VOLUME_LSB E5h 0000 0000 0 0 0 0 0 0 LS_MASTER_VOLUME_ LSB[1:0] HP_L_VOLUME_MSB E6h 1001 1000 HP_L_VOLUME_MSB[7:0] HP_L_VOLUME_LSB E7h 0000 0000 0 0 0 0 0 0 HP_L_VOLUME_LSB[1:0] HP_R_VOLUME_MSB E8h 0000 0000 HP_R_VOLUME_MSB[7:0] HP_R_VOLUME_LSB E9h 0000 0000 0 0 0 0 0 0 HP_R_VOLUME_ LSB[1:0] SCART_L_VOLUME_MSB EAh 1101 1101 SCART_L_VOLUME_MSB[7:0] SCART_L_VOLUME_LSB EBh 0000 0000 0 0 0 0 0 0 SCART_L_VOLUME_ LSB[1:0] SCART_R_VOLUME_MSB ECh 1101 1101 SCART_R_VOLUME_MSB[7:0] SCART_R_VOLUME_LSB EDh 0000 0000 0 0 0 0 0 0 SCART_R_VOLUME_ LSB[1:0] Beeper BEEPER_ON EEh 0000 0000 0 0 0 0 0 0 0 BEEPER_ ON BEEPER_MODE EFh 0000 0011 0 0 0 BEEPER_DURATION[1:0] BEEPER_ PULSE BEEPER_PATH[1:0] BEEPER_FREQ_VOL F0h 0111 0000 BEEPER_FREQ[2:0] BEEPER_VOLUME[4:0] Mute MUTE_DIGITAL F1h 1001 1111 AUTOSTD_ MUTE_ON 00 SCART_ D_MUTE SRND_HP_ D_MUTE SUB_ D_MUTE D_MUTE LS_ D_MUTE S/PDIF S/PDIF_OUT_CONFIG F2h 0000 0100 0 0 0 0 0 SPDIF_OUT_ MUTE S/PDIF_OUT_SELECT[2:0] Headphone Configuration HEADPHONE_CONFIG F3h 0000 001(0) 0 0 0 0 HP_FORCE HP_LS_ MUTE HP_DET_ ACTIVE HP_ DETECTED DAC Control DAC_CONTROL F4h 0001 1111 0 0 S/PDIF_ MUX DAC_SCART _MUTE DAC_SHP_ MUTE DAC_CSUB_ MUTE DAC_LSLR_ MUTE POWER_ UP SPDIF_CHANNEL_STATUS F9h 0000 0000 CHANNEL_STATUS EMPHASIS COPYRIGHT NON_AUDIO PRO_CON AutoStandard Coefficients Settings AUTOSTD_COEFF_CTRL FBh 0000 0001 0 0 0 0 0 0 AUTOSTD_COEFF_ CTRL[1:0] AUTOSTD_COEFF_INDEX_MSB FCh 0000 0000 0 0 0 0 0 0 0 AUTOSTD_ COEFF_ INDEX_MSB AUTOSTD_COEFF_INDEX_LSB FDh 0000 0000 AUTOSTD_COEFF_INDEX_LSB[7:0] AUTOSTD_COEFF_VALUE FEh 0000 0000 AUTOSTD_COEFF_VALUE[7:0] Table 9: List of I²C Registers (Sheet 6 of 6) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

12.2 STV82x7 General Control Registers

CUT_ID Version Identification RESET Software Reset Register

Description

The built-in Automatic Standard Recognition System (Autostandard) can be disabled. In this case, the Software Reset function (bits SOFT_LRST1 and SOFT_LRST2) can be used to implement the Automatic Standard Recognition by I²C Software. This is not required if the built-in Automatic Standard Recognition System function is used (default). Address: 00h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 CUT_NUMBER[5:0] Bit Name Reset Function Bits[7:6] 00 Reserved CUT_NUMBER[5:0] 000001 Dice Version Identification Address: 01h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BUS_EXP I²S_OUTPUT 0 EN_STBY 0 SOFT_LRST2 SOFT_LRST1 SOFT_RST Bit Name Reset Function BUS_EXP 0 Static control by I2C of hardware pin BUS_EXP I²S_OUTPUT 0 0 = I²S Input (I²S out put will be provided on I2S_DATA0 pin) 1 = I²S Output (512 x fs will be provided on I2S_PCM_CLK pin) Bit[5] 0 Reserved. EN_STBY 0 Standby mode enabling 0: Normal mode 1: To lock the digital signals before to settle the device in standby mode Bit 3 0 Reserved. SOFT_LRST2 0 Softreset (active high) of Channel 2 detectors only. SOFT_LRST1 0 Softreset (active high) of Channel 1 detectors only. SOFTR_RST 0 General softreset (active high) to reset all hardware registers except for I²C data.

I2S_CTRL I 2S Synchronization Control Register I2S_STAT I²S Synchronization Status Register I2S_SYNC_OFFSET I²S Synchronization Offset Frequency Register

12.3 Clocking 1

A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the frequency recommended for reducing potential RF interference in the application. However, if Address: 04h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L R _ O F F L O C K _ F L A G

Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 05h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 06h Type: R/W

necessary, the PLL Clock can be re-programmed for other quartz crystal frequencies within a range from 23 to 30 MHz. Other quartz crystal frequencies can be programmed on your demand. Note: A Crystal Frequency change is compatible with other default I²C programming including the built-in Automatic Standard Recognition System. SYS_CONFIG System Configuration Control Register FS1_DIV FS1 I/O Divider Programming Register Address: 07h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_CH_NB[1:0] INPUT_FREQ[3:0] INPUT_CONFIG[1:0] Bit Name Reset Function I2S_CH_NB[1:0] 00 Number of I2S channels input 00: N/A 01: 2 channels 10: 4 channels 11: 6 channels INPUT_FREQ[3:0] 0000 I2S Input frequency 0000 : 32 kHz 0001: 44.1 kHz 0010: 48 kHz 0011: 8 kHz (I2S input, 2 channels only) 0100 : 11.025 kHz (I2S input, 2 channels only) 0101 : 12 kHz (I2S input, 2 channels only) 0110 : 16 kHz (I2S input, 2 channels only) 0111 : 22.05 kHz (I2S input, 2 channels only) 1000 : 24 kHz (I2S input, 2 channels only) INPUT_CONFIG[1:0] 0 Input stream to process 0 : SIF & SCART input (32 kHz) 1 : SCART input only (48 kHz) 2 : I2S input only Address: 08h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN_PROG 0 NDIV1[1:0] 0 SDIV1[2:0] Bit Name Reset Function EN_PROG 0 FS1 programmation enable 0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by SYS-CONFIG register (normal use with standard quartz of 27 MHz) 1: FS1 I2C registers programmation used by system - FS1 pre-programmation by SYS-CONFIG desactivated (to be used in case of no standard quartz, different from 27 MHz)

FS1_MD FS1 Coarse Selection Register FS1_PE_H FS1 Fine Selection Register (MSBs) FS1_PE_L FS1 Fine Selection Register (LSBs) Bit 6 0 Reserved. NDIV1[1:0] 01 FS1 Input clock divider selection Bit 3 0 Reserved. SDIV1[2:0] 010 FS1 Output clock divider selection Address: 09h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000 M D 1 [ 4 : 0 ]

Bits[7:5] 000 Reserved. MD1[4:0] 10001 FS1 Coarse Selection Address: 0Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PE_H1[7:0] Bit Name Reset Function PE_H1[7:0] 0011 0110 FS1 Fine Selection (MSBs) Address: 0Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PE_L1[7:0] Bit Name Reset Function

12.4 Demodulator

DEMOD_CTRL Demodulator Control Register DEMOD_STAT Demodulator Detection Status Register Bit Name Reset Function PE_L1[7:0] 0000 0000 FS1 Fine Selection (LSBs) Address: 0Ch Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 FAR_MODE GAP_MODE AM_SEL DEMOD_MODE[2:0] Bit Name Reset Function bit [7:6] 000 Reserved FAR_MODE 0 1: Farrow and Mono filter for NICAM active GAP_MODE 0 Defines the clock gapping mode of the demodulator 0: (default), the FS1 freq is controlled by stl-error (clock-pll mode) to align the instantaneous value of the internal clock with respect to the received NICAM clock 1: the FS1 freq is fixed and the mean value of the internal clock is aligned by variable gapping (src-error) with respect to the received NICAM clock AM_SEL 0 Demodulator Configuration Select 0: FM configuration of demodulator (Default) 1: AM configuration of demodulator DEMOD_MODE[2:0] 110 Demodulator Mode Select CH1 FM CH2 FM/QPSK 000: Normal FM Normal 001: Wide FM Wide 010: Normal QPSK System B/G/L/D/K 011: Wide QPSK System B/G/L/D/K 100: Normal FM Wide 101: Wide FM Normal 110: Normal QPSK System I 111: Wide QPSK System I Address: 0Dh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 QPSK_LK FM2_CAR FM2_SQ FM1_CAR FM1_SQ

Note: These registers allow direct access to the demodulator signal detectors. AGC_CTRL IF AGC Control Register Bit Name Reset Function Bit [7:5] 000 Reserved. QPSK_LK 0 QPSK Lock Detection Flag 0: Not detected 1: Detected FM2_CAR 0 Channel 2 FM/AM Carrier Detection Flag 0: Not detected 1: Detected FM2_SQ 0 Channel 2 FM Squelch Detection Flag 0: Not detected 1: Detected FM1_CAR 0 Channel 1 FM/AM Carrier Detection Flag 0: Not detected 1: Detected FM1_SQ 0 Channel 1 FM Squelch Detection Flag 0: Not detected 1: Detected Address: 0Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AGC_CMD 0 0 AGC_REF[2:0] AGC_CST[1:0] Bit Name Reset Function AGC_CMD 0 Automatic Gain Control Command Mode Normally set to 0 enabling automatic mode. For L/L ’ standards, the AGC should be switched off due to the presence of the AM sound carrier. In this case, a fixed gain value should be set using the AGCS register. 0: Automatic mode. AGC controlled by the Autostandard function. (Default) 1: Manual/Forced mode Bits[6:5] 00 Reserved. AGC_REF[2:0] 100 This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale range of the ADC. The default setting gives a ratio of 1/256. Clipping Ratio Clipping Ratio 000: 1/16 (Single carrier) 100: 1/256 (Default) 001: 1/32 101: 1/512 010: 1/64 110: 1/1024 011: 1/128 111: 1/2048 (Multiple carriers)

AGC_GAIN IF AGC Control and Status Register Note: When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written to -- presetting the AGC level which will then adjust itself to the final value. When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC amplifier gain. Reading AGC_ERR just confirms the fixed value. AGC_CST[1:0] 01 AGC Time Constant This is the time constant between each step of 1.5 dB by the AGC. Step Duration (ms) 00 1.33 01 2.66 10 5.33 11 10.66 Address: 0Fh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 AGC_ERR[4:0] SIG_OVER SIG_UNDER

Bit 7 0 Reserved. AGC_ERR[4:0] 00000 Amplifier Gain Control This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see Note below). 00000: Gain-min 10100: Gain-min + 30db 11111: Gain-min + 30db SIG_OVER 0 AGC Input SIgnal Upper Threshold 0: Normal signal 1: Signal too large and AGC is overloaded SIG_UNDER 0 AGC Input SIgnal Lower Threshold 0: Normal signal 1: Signal too small and AGC is underloaded When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting the STV82x7 SIF input level. Bit Name Reset Function

DC_ERR_IF DC Offset Status for IF ADC

12.5 Demodulator Channel 1

CARFQ1H, CARFQ1M, CARFQ1L Channel 1 Carrier DCO Frequency Note: Carrier Freq: CARFQ1(dec).f S / 224 with fS = 24.576 MHz (crystal oscillator frequency independent) Address: 10h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_ERR[7:0] Bit Name Reset Function DC_ERR[7:0] 00000000 DC offset error of IF ADC output Address: 12h to 14h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0] Bit Name Reset Function CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] 00111110 10000000 00000000 Channel 1 DCO Carrier Frequency (8 MSBs) Channel 1 DCO Carrier Frequency Channel 1 DCO Carrier Frequency (8 LSBs), see Table 10. Table 10: Mono Carrier Frequencies by System System Mono Carrier Freq. (MHz) CARFQ1[23:0] (dec) CARFQ1[23:0] M/N 4.5 3072000 2EE000h B/G 5.5 3754667 394AABh I 6.0 4096000 3E8000h L 6.5 4453717 43F555h D/K/K1/K2 6.5 4437333 43B555h

FIR1C[0:7] Channel 1 FIR Coefficients ACOEFF1 Channel 1 Baseband PLL Loop Filter Proportional Coefficient Address: 15h to 1Ch Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR1C0[7:0] to FIR1C7[7:0] Table 11: Channel 1 FIR Coefficients Bitfield (reset state) FM 27 kHz FM 50 kHz FM 200 kHz FM 350 kHz FM 500 kHz AM FIR1C0[7:0] FFh 00h 00h 02h 01h 00h FIR1C1[7:0] FEh FEh 01h 01h 00h FEh FIR1C2[7:0] FEh FCh 01h FCh 04h FDh FIR1C3[7:0] 00h FDh FCh 03h FAh FEh FIR1C4[7:0] 06h 02h 08h 04h 05h 04h FIR1C5[7:0] 0Eh 0Dh F6h F2h 00h 0Dh FIR1C6[7:0] 16h 18h F8h 06h F2h 16h FIR1C7[7:0] 1Bh 1Fh 4Ah 43h 4Dh 1Dh Address: 1Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOEFF1[7:0] Bit Name Reset Function ACOEFF1[7:0] 00100011 Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) Defines the damping factor of the loop. For values, refer to Table 12.

BCOEFF1 Channel 1 Baseband PLL Loop Filter Integral Coefficient & DCO Gain (*) Refer to DEMOD_CTRL (DEMOD_MODE[2:0]) CRF1 Channel 1 Baseband PLL Demodulator Offset CETH1 Channel 1 FM/AM Carrier Level Threshold Address: 1Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF1[7:0] Bit Name Reset Function BCOEFF1[7:0] 00010010 Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain Defines the bandwidth of the loop. For values, refer to Table 12. Table 12: Baseband PLL Loop Filter Adjustment (FM Mode) FM Mode Small Standard Medium Wide* A2 Standard ACOEFF 10h 22h 2Ch 2Ch 10h BCOEFF 1Ah 12h 0Ah 0Ah 11h FM_DEV max (kHz) 62.5 125 250 500 125 DCO Range (kHz) 96 192 384 768 192 Address: 1Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRF1[7:0] Bit Name Reset Function CRF1[7:0] (00000000) Channel 1 Carrier Recovery Frequency Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator. Address: 20h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CETH1[7:0]

SQTH1 Channel 1 FM Squelch Threshold Register CAROFFSET1 Channel 1 DCO Carrier Offset Compensation Bit Name Reset Function CETH1[7:0] 00100000 This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. CETH Threshold (dB) CETH Threshold (dB) FFh -6 10h -32 (Recommended Value) 80h -12 08h -38 40h -18 00h OFF (all carrier levels are accepted) 20h -24 (Default) Address: 21h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SQTH1[7:0] Bit Name Reset Function SQTH1[7:0] 00111100 The squelch detector meas ures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH S/N (dB) FAh 0 77h 10 3Ch 15 (Default) 23h 20 19h 25 Address: 22h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAROFFSET1[7:0] (S) Bit Name Reset Function CAROFFSET1[7:0] 00000000 This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two’s complement format) is added to the pre-programming value by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displays by DC_REMOVAL_L and DC_REMOVAL_R can be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1

12.6 Demodulator Channel 2

IAGCR Channel 2 Internal AGC Reference for QPSK IAGCC Channel 2 Internal AGC Time Constant for QPSK Address: 25h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_REF[7:0] Bit Name Reset Function IAGC_REF[7:0] 10001000 Sets the mean value of the internal AGC, used for QPSK demodulation. The default setting corresponds to half full scale amplitude at the baseband PLL input. Address: 26h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_OFF FAR_FLT_EN MONO_FLT_EN BG_SEL MONO_PROG IAGC_CST[2:0] Bit Name Reset Function IAGC_OFF 0 AGC Disable 0: Internal AGC is active 1: Internal AGC is disabled FAR_FLT_EN 0 1: Enable Farrow filter for NICAM MONO_FLT_EN 0 1: Enable Mono filter for NICAM BG_SEL 0 1: BG NICAM Mono filter selected MONO_PROG 0 1: Enable programmation of Mono filter IAGC_CST[2:0] 011 Internal AGC Programmable Step Constant. These bits control the time per step (values given for QPSK mode). The default value defines the optimum trade-off between fast settling time (for the fastest NICAM identification) and the noise immunity (minimum BER degradation) Step time (us) Time Response (ms) 000 703 128 001 352 64 010 176 32 011 88 16 100 44 8 101 22 4 110 11 2 111 5.5 0.82

IAGCS Channel 2 Internal AGC Status for QPSK CARFQ2H, CARFQ2M, CARFQ2L Channel 2 Carrier DCO Frequency Address: 27h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_CTRL[7:0] Bit Name Reset Function IAGC_CTRL[7:0] 00000000 Indicates the value of the internal AGC gain control Address: 28H to 2Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CARFQ2[23:16], CARFQ2[15.8], CARFQ2[7:0] Bit Name Reset Function CARFQ2[23:16] CARFQ2[15.8] CARFQ2[7:0] 01000100 01000000 00000000 Channel 2 DCO Carrier Frequency (8 MSBs) Channel 2 DCO Carrier Frequency Channel 2 DCO Carrier Frequency (8 LSBs) See Table 13. Table 13: Stereo Carrier Frequencies by System System Stereo Carrier Freq. (MHz) CARFQ2[23:0] (Dec) CARFQ2[23:0] M/N A2+ 4.724212 3225062 3135E6h B/G NICAM 5.85 3993600 3CF000h BG A2 5.7421875 3920000 3BD080h I NICAM 6.552 4472832 444000h L NICAM 5.85 3993600 3CF000h DK NICAM 5.85 3993600 3CF000h DK1 A2* 6.258125 4272000 412F80h DK2 A2* 6.7421875 4602667 463B2Bh DK3 A2* 5.7421875 3920000 3BD080h

FIR2C[0:7] Channel 2 FIR Coefficients ACOEFF2 Channel 2 Baseband PLL Loop Filter Proportional Coefficient BCOEFF2 Channel 2 Baseband PLL Loop Filter Integral Coefficient & DCO Gain Address: 2Bh to 32h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR2C0[7:0] to FIR2C7[7:0] Table 14: Channel 2 FIR Coefficients Bitfield FM 27 kHz FM 50 kHz QPSK 40% (reset state) QPSK100% FIR2C0[7:0] FFh 00h 00h 00h FIR2C1[7:0] FEh FEh 00h 00h FIR2C2[7:0] FEh FCh FFh 00h FIR2C3[7:0] 00h FDh 03h 00h FIR2C4[7:0] 06h 02h 00h FFh FIR2C5[7:0] 0Eh 0Dh F4h 04h FIR2C6[7:0] 16h 18h 0Ah 14h FIR2C7[7:0] 1Bh 1Fh 3Dh 25h Address: 33h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOEFF2[7:0] Bit Name Reset Function ACOEFF2[7:0] 10010000 This value defines the loop clamping factor used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 2). See Table 15 and Table 16. Address: 34h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF2[7:0]

SCOEFF Channel 2 Symbol Tracking Loop Coefficients Bit Name Reset Function BCOEFF2[7:0] 10101100 This value defines the loop bandwidth used to program the Integral Coefficient of the Baseband PLL loop filter and DCO gain. See Table 15 and Table 16. Table 15: Baseband PLL Loop Filter Adjustments (FM Mode) FM mode Small Standard Mid Wide A2 standard ACOEFF 10h 22h 2Ch 2Ch 10h BCOEFF 1Ah 12h 0Ah 0Ah 11h FM_DEV max (kHz) 62.5 125 250 500 125 DCO Range (kHz) 96 192 384 768 192 Table 16: Baseband PLL Loop Filter Adjustments (QPSK Mode) QPSK mode Small Medium Large Extra-large ACOEFF 90h 90h 90h 90h BCOEFF ACh A3h 9Ah 91h DCO_DEV max (kHz) 2.84375 5.6875 11.375 22.75 Address: 35h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCOEFF[7:0] Bit Name Reset Function SCOEFF[7:0] 00011100 This value is used to program the proportional and integral coefficients of the QPSK Symbol tracking loop. See Table 17 and Table 18. Table 17: QPSK System - BG/L/DK Standards (40% Roll-off) Extra-Small Small Medium La rge Extra-Large Open Loop SCOEFF 1Eh 25h 24h 26h 2Ah 80h Table 18: QPSK System - I Standard (100% Roll-off) Extra-Small Small Medium Large Extra-Large SCOEFF 16h 1Dh 1Ch 23h 22h

SRF Channel 2 Symbol Tracking Loop Frequency CRF2 Channel 2 Baseband PLL Demodulator Offset CETH2 Channel 2 FM Carrier Level Threshold Address: 36h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRF[7:0] Bit Name Reset Function SRF[7:0] 00000000 Displays in two’s complement format the frequency deviation between the incoming NICAM bitstream and the quartz clocks. The maximum error is ±250 ppm. Address: 37h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRF2[7:0] Bit Name Reset Function CRF2[7:0] 00000000 Channel 2 Carrier Recovery Frequency. Displays the instantaneous frequency offset of the Channel 2 Baseband PLL Address: 38h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CETH2[7:0] Bit Name Reset Function CETH2[7:0] 00100000 This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. CETH Threshold (dB) CETH Threshold (dB) FFh -6 10h -32 80h -12 08h -38 40h -18 00h OFF (All carrier levels are accepted) 20h -24 (Default

SQTH2 Channel 2 FM Squelch Threshold CAROFFSET2 Channel 2 DCO Carrier Offset Compensation

12.7 NICAM Registers

NICAM_CTRL NICAM Decoder Control Register Address: 39h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SQTH2[7:0] Bit Name Reset Function SQTH2[7:0] 00111100 The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH S/N (dB) FAh 0 77h 10 3Ch 15 (Default) 23h 20 19h 25 Address: 3Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAROFFSET2[7:0] (S) Bit Name Reset Function CAROFFSET2[7:0] 00000000 This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two’s complement format) is added to the pre-programming value by AUTOTSD in the CARFQ2 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displayed by register DC_REMOVAL_R can be directly loaded in register CAROFFSET2 to exactly compensate the carrier offset on Channel 2. Address: 3Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00000 D I F _ P O L E C T M A E

NICAM_BER NICAM Bit Error Rate Register NICAM_STAT NICAM Detection Status Register Bit Name Reset Function Bits[7:3] 00000 Reserved. DIF_POL 0 0: No polarity inversion (Default) 1: Polarity inversion of the differential decoding ECT 0 Error Counter Timer: Defines the NICAM error measurement period 0: 128 ms (Default) 1: 64 ms MAE 0 Max. Allowed Errors. Defines the NICAM error decoding for mute function. 0: 511 Max (Default) 1: 255 Max Address: 3Eh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERROR[7:0] Bit Name Reset Function ERROR[7:0] 00000000 NICAM Error Counter Value Address: 3Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NIC_DET F_MUTE LOA CBI[3:0] NIC_MUTE Bit Name Reset Function NIC_DET 0 NICAM Signal Detect 0: NICAM signal no detected 1: NICAM signal detected F_MUTE 0 Frame Mute 0: No mute 1: Mute due to Superframe Alignment Loss LOA 0 Loss of Frame Alignment Word (FAW) 0: No Alignment Lost 1: Frame Alignment Word Lost CBI[3:0] 0000 Indicates the received NICAM control bits NIC_MUTE 0 Indicates the NICAM decoder mute

12.8 Stereo Mode

ZWT_CTRL Zweiton Detector Control Register ZWT_TIME Zweiton Detector Timing Register Address: 40h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRST_TONE_OFF STD_MODE THRESH[3:0] TSCTRL[1:0] Bit Name Reset Function LRST_TONE_OFF 0 Control of the reset of the tone detector 0: Periodical reset of tone detection enabled 1: Periodical reset of tone detection disabled STD_MODE_C 0 0: German standard (Default) 1: Korean standard THRESH[3:0] 1100 Defines the threshold of the detector for pilot and tone frequencies. Level (% of the mid scale) Level (% of the mid scale) 0000 0 1000 50 0001 6.25 1001 56.25 0010 12.5 1010 62.5 0011 18.75 1011 68.75 0100 25 1100 (Default) 75 0101 31.25 1101 81.25 0110 37.5 1110 87.5 0111 43.75 1111 93.75 TSCTRL[1:0] 00 Defines both the detection time and t he error probability (reliability of the detection). Sample Accumulation Decision Count Time (ms) Error Probability 00 1024 2 256 10 -4 01 (Default) 1024 3 384 10 -6 10 2048 2 512 10 -7 11 2048 3 768 10 -9 Address: 41h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00000 ZWT_TIME[2:0]

Bit [7:3] 00000 Reserved.

ZWT_STAT Zweiton Status Register

12.9 Analog Control

ADC_CTRL Register Description ZWT_TIME[2:0] 100 Defines the period of the re set tone used for tone detection system reset. Duration (ms) 000 256 001 512 010 768 011 1024 100 1280 101 1536 110 1792 111 2040 Address: 42h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRST_TONE_ OFF 000 ZW_STAT_ RDY ZW_DET ZW_ST ZW_DM Bit Name Reset Function LRST_TONE_OFF 0 Indicates the status of the control bit programmed in the reg ZWT-CTRL 0: Periodical reset of tone detection enabled 1: Periodical reset of tone detection disabled Bits[6:4] 000 Reserved. ZW_STAT_RDY 0 Periodic flag indicating when the tone detection flags are updated and ready to be read ZW_DET 0 Pilot Detection Flag ZW_ST 0 Stereo Tone Detection Flag ZW_DM 0 Dual Mono Tone Detection Flag Address: 56h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_DATA0_CTRL[1:0] 0 0 ADC_POWER _UP ADC_INPUT_SEL[2:0] Bit Name Reset Function

SCART1_2_OUTPUT_CTRL Register Description Bit Name Reset Function I2S_DATA0_CTRL[1:0] 00 00 = SCART 01 = L, R 10 = HP or Srnd 11 = C/Sub Bits[7:4] 0000 Reserved. ADC_POWER_UP 1 Control of the power up of the Audio ADC 0: ADC in power down mode 1: Wake up of the ADC ADC_INPUT_SEL [2:0] 000 Selection of the ADC input signal 000: SCART 1 (Default) 011: SCART 4 001: SCART 2 100: Mono input 010: SCART 3 Other: reserved Address: 57h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SC2_MUTE SC2_OUTPUT_SEL[2:0] S C1_MUTE SC1_OUTPUT_SEL[2:0] Bit Name Reset Function SC2_MUTE 1 Mute command for the output SCART 2 0: output not muted 1: output muted SC2_OUTPUT_SEL[2:0]

010 Selection of the output SCART 2 configuration:

000: DSP 100: Input SCART 3 001: Mono input 101: Input SCART 4 010: Input SCART 1 (Default) Other: Reserved 011: Input SCART 2 SC1_MUTE

1 Mute command for the output scart 1

0: output not muted 1: output muted SC1_OUTPUT_SEL[2:0] 000 Selection of the output SCART 1 configuration: 000: DSP (Default) 100: Input SCART 3 001: Mono input 101: Input SCART 4 010: Input SCART 1 Other: Reserved 011: Input SCART 2

SCART3_OUTPUT_CTRL Register Description

12.10 Clocking 2

FS2_DIV FS2 I/O Divider Programming Register FS2_MD FS2 Coarse Selection Register Address: 58h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 SC3_MUTE SC3_OUTPUT_SEL[2:0] Bit Name Reset Function Bits[7:4] 0000 Reserved. SC3_MUTE

1 Mute command for the output SCART 3

0: output not muted 1: output muted SC3_OUTPUT_SEL[2:0] 011 Selection of the output SCART 3 configuration: 000: DSP 100: Input SCART 3 001: Mono input 101: Input SCART 4 010: Input SCART 1 Other: Reserved 011: Input SCART 2 (Default) Address: 5Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 NDIV2[1:0] SDIV2[2:0] Bit Name Reset Function Bit [7:6] 0 Reserved. NDIV2[1:0] 01 FS2 Input clock divider selection Bit 4 0 Reserved. SDIV2[2:0] 001 FS2 Output clock divider selection Address: 5Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000 M D 2 [ 4 : 0 ]

FS2_PE_H FS2 Fine Selection Register (MSBs) FS2_PE_L FS2 Fine Selection Register (LSBs)

12.11 DSP Control

HOST_CMD DSP Hardware Control Register Bit Name Reset Function Bits[7:5] 000 Reserved. MD2[4:0] 10001 FS2 Coarse Selection Address: 5Ch Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PE_H2[7:0] Bit Name Reset Function PE_H2[7:0] 0101 1100 FS2 Fine Selection (MSBs) Address: 5Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PE_L2[7:0] Bit Name Reset Function PE_L2[7:0] 0010 1001 FS2 Fine Selection (LSBs) Address: 80h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IT_IN_DSP 0 0 0 0 HW_RESET Bit Name Reset Function IT_IN_DSP 0 Valid I2C table. Bits[6:3] 0000 Reserved.

IRQ_STATUS IRQ Status Register SOFT_VERSION Embedded Software Version Register ONCHIP_ALGOS Register Description HW_RESET 0 DSP Hardware reset when set. Bits[1:0] 00 Reserved. Address: 81h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Bit Name Reset Function Bits[7:4] 0000 Reserved. IRQ3 0 Unmute HP/Srnd DAC IRQ IRQ2 0 HP connection/deconnectionIRQ IRQ1 0 I2S lock lostIRQ IRQ0 0 Auto-Standard IRQ Address: 82h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOFT_VERSION[7:0] Bit Name Reset Function SOFT_VERSION[7:0] 0000 0002 Version of the Embedded software. Address: 83h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PRO_LOGIC_

SELECT NICAM I2S_INPUT TRUBASS TRU SURROUND PRO_LOGIC MULTICHANNEL Bit Name Reset Function

DSP_STATUS DSP Status Register DSP_RUN Register Description Bit Name Reset Function Bit 7 0 Reserved. PRO_LOGIC_SELECT 0 0: Dolby Pro Logic I 1: Dolby Pro Logic II NICAM 0 NICAM Demodulator is present when set. I2S_INPUT 0 0: 1 I2S input 1: 3 I2S inputs DIALOG_CLARITY 0 SRS Dialog Clarity algorithm is present when set. TRUBASS 0 SRS Trubass algorithm is present when set. TRUSURROUND 0 SRS Trusurround al gorithm is present when set. PRO_LOGIC 0 Dolby Pro Logic algor ithm is present when set. MULTICHANNEL 0 Multichannels out put is present when set. Address: 84h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000000 I N I T _ M E M

Bits[7:1] 0000000 Reserved. INIT_MEM DSP Initialization 0: DSP is not initialized. 1: DSP is initialized. Address: 85h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEST_MODE 0 0 HOST_ NO_INIT HOST_RUN Bit Name Reset Function TEST_MODE_ INPUT[7:6] 00 active in TEST_MODE = 1 (bypass processing) 0: I2S_0 copied to SCART and SPDIF outputs 1: I2S_1 copied to SCART and SPDIF outputs 2: I2S_2 copied to SCART and SPDIF outputs

I2S_IN_CONFIG I²S Configuration Register AV_DELAY Audio/Video Delay Register TEST_MODE[5:4] 00 0: standard configuration 1: bypass processing configuration 2: Clock Loop test Bits[3:2] 00 Reserved HOST_ NO_INIT 0 0: I2C register table is initialized when we soft reset 1: I2C register table is not initialized when we soft reset HOST_RUN 0 0: soft reset DSP 1: start DSP processing Address: 86h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOCK_MODE _EN 0 SYNC LRCLK_START LRCLK_ POLARITY SCLK_ POLARITY DATA_CFG I2S_MODE Bit Name Reset Function LOCK_MODE_EN 1 0: Disable Lock Mode for external I2S input 1: Enable Lock Mode for external I2S input Bit 6 0 Reserved. SYNC 0 I2S synchronisation: 0: Capture directly 1: Wait for synchro LRCLK_START according to LRCLK POLARITY , first data take: 0: Left 1: Right LRCLK_POLARITY 0 Polarit y of the left data SCLK_POLARITY 1 0: Falling edge 1: Rising edge DATA_CFG 1 0: LSB First 1: MSB First I2S_MODE 0 0: Non standard mode 1: Standard mode (Refer to Figure 26) Address: 89h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DELAY_TIME DELAY_ON Bit Name Reset Function

Note: AV_DELAY acts on both LS and HP paths simultaneously (same delay).

12.12 Automatic Standard Recognition

AUTOSTD_CTRL Automatic Standard Recognition Control Register Note: Only standard deviation FM 50K kHz is compatible with other D/K1/K2/K3 standards in Automatic Standard Recognition Search mode. FM deviation superior to 350 kHz will degrade strongly NICAM reception due to overlapping of FM and QPSK IF spectrum in DK-NICAM standard. Bit Name Reset Function DELAY_TIME 0000000 Audio Delay Time 0000000: 0 ms ... 0111100: 60 ms (48kHz) ... 1011010: 90 ms (32kHz) DELAY_ON 0 Audio/video delay is enabled when set. Address: 8Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000 FORCE_SQUE

LCH SINGLE_SHOT DK_DEV[1:0] LDK_SW Bit Name Reset Function Bits[7:5] 000 Reserved. FORCE_SQUELCH Allow to force squelch detection 0: FM squelch is taken into consideration for MONO detection 1: FM squelch is not taken into consideration for MONO detection SINGLE_SHOT Single Shot Mode Selection 0: Single Shot mode is not selected 1: Single Shot mode is selected 1. Single_Shot mode can be used before disabling the Automatic Standard Recognition (Autostandard) to pre-program demodulator registers in a defined standard and reduce I²C programming in Manual mode DK_DEV[1:0] Selects FM deviation configuration to take into account of overmodulation in DK_NICAM standard. 00: FM 50 kHz (Default) 10: FM 350 kHz 01: FM 200 kHz 11: FM 500 kHz LDK_SW Makes exclusive the auto search of DK/K1/K2/K3 and L/L ’ standard 0: DK/K1/K2/K3 standard auto-search / L/L ’ disabled 1: L/L ’ standard auto-search / DK/K1/K2/K3 disabled

L/L ’ and DK/K1/K2/K3 standard cannot be discriminated in Automatic Standard Recognition Search mode because the same frequency is used for the mono IF carrier. AUTOSTD_STANDARD_DETECTAuto Standard Check Standard Register Note: Autostandard is off when all mono standards are disabled (LDK_SCK = 0, I_SCK = 0, BG_SCK = 0 and MN_SCK = 0). AUTOSTD_STEREO_DETECT Auto Standard Check Stereo Register Address: 8Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 NICAM_C4_O

NICAM_GAP_ MODE NICAM_MON O_IN LDK_SCK I_SCK BG_SCK MN_SCK Bit Name Reset Function NICAM_C4_OFF 0 0: Autostandard will consider the C4 bit for MONO backup 1: Autostandard will ignore the C4 bit for MONO backup NICAM_GAP_MODE 1 0: NICAM, fast search 1: NICAM, slow search (no perturbations on LEFT channel in search mode) NICAM_MONO_IN 0 0: the MONO backup for NICAM comes from internal demodulator 1: the MONO backup for NICAM comes from MONO input LDK_SCK L/L ’ or D/K Mono Standard Enable 0: Disabled 1: Enabled I_SCK I Mono Standard Enable 0: Disabled 1: Enabled BG_SCK B/G Mono Standard Enable 0: Disabled 1: Enabled MN_SCK M/N Mono Standard Enable 0: Disabled 1: Enabled Address: 8Ch Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDK_ZWT3 LDK_ZWT2 LDK_ZWT1 LDK_ NIC I_NIC BG_ZWT BG_NIC MN_ZWT

Note: Stereo standard covers all transmission modes (stereo or multi-language) of the NICAM or Zweiton (A2, A2* or A2+) system. AUTOSTD_TIMERS Detection Time Out Register Bit Name Reset Function LDK_ZWT3 D/K3 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_ZWT2 D/K2 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_ZWT1 D/K1 Zweiton (A2*) Stereo Standard Enable 0: Disabled 1: Enabled LDK_NIC D/K NICAM Stereo Standard Enable 0: Disabled 1: Enabled I_NIC I NICAM Stereo Standard Enable 0: Disabled 1: Enabled BG_ZWT B/G Zweiton (A2) Standard Enable 0: Disabled 1: Enabled BG_NIC B/G NICAM Standard Enable 0: Disabled 1: Enabled MN_ZWT M/N Zweiton (A2+) Standard Enable 0: Disabled 1: Enabled Address: 8Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FM_TIME[1:0] NICAM_TIME [2:0] ZWEITON_TIME[2:0] Bit Name Reset Function FM_TIME[1:0] FM/AM Detection Time-out 00 : 16 ms 10: 48 ms (Default) 01: 32 ms 11: 64 ms NICAM_TIME[2:0] 100 NICAM Detection Time-out 000: 96 ms 100: 224 ms (Default) 001: 128 ms 101: 256 ms 010: 160 ms 110: 288 ms 011: 192 ms 111: 320 ms

Note: The time-out default value is optimum and does not normally need to be changed. AUTOSTD_STATUS Detection Standard Status Register ZWEITON_TIME[2:0] 100 Zweiton Detection Time-out 000: forbidens 100: 1280 ms (Default) 001: 512 ms 101: 1536 ms 010: 768 ms 110: 1792 ms 011: 1024 ms 111: 2040 ms Address: 8Eh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STEREO_ID STEREO_OK MONO_OK AUTOSTD_ON STEREO_SID[1:0] MONO_SID[1:0] Bit Name Reset Function STEREO_ID Stereo Mode Detection flag activated when a stereo standard coming from the demodulator selected on Loudspeakers output. Stereo transmission modes are: - Zweiton Stereo Carrier AND Stereo Modulation (indifferently German or Korean standard) - NICAM stereo with backup (CBI = 1000) - NICAM stereo with no backup (CBI = 0000) AUTOSTD_ON Automatic Standard Recognition System Status 0: Automatic Standard Recognition System is OFF 1: Automatic Standard Recognition System is ON STEREO_SID[1:0] 00 Identification of the detected TV sound standard. See Table 19. MONO_SID[1:0] 00 STEREO_OK 0 STEREO STANDARD DETECTED MONO_OK 0 MONO STANDARD DETECTED Table 19: TV Sound Standards System Mono Sound (MHz) MONO_SID [1:0] LDK_SW DK_DEV [1:0] Stereo Sound (MHz) STEREO_SID [1:0] M/N 4.5 (FM 27k) 00 X XX 4.724 (Zweiton A2+) 00 B/G 5.5 (FM 50k) 01 X XX 5.85 (NICAM 40%) 00 X XX 5.742 (Zweiton A2) 01 I 6.0 (FM 50k) 10 X XX 6.552 (NICAM 100%) 00 Bit Name Reset Function

Note: X means don’t care.

12.13 Audio Preprocessing and Selection Registers

DC_REMOVAL_INPUT DC Removal Register L6 . 5 ( A M ) 1 XX 5.85 (NICAM 40%) 00 D/K 6.5 (FM 50k) 5.85 (NICAM 40%) 00 6.5 (FM 200k) 01 6.5 (FM 350k) 10 6.5 (FM 500k) 11 D/K1/K2/ K3 6.5 (FM 50k) 0 XX 5.85 (NICAM 40%) 00 0 XX 6.258 (Zweiton A2*) 01 0 XX 6.742 (Zweiton A2*) 10 0 XX 5.742 (Zweiton A2*) 11 Address: 90h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 DC_SCART DC_NICAM DC_DEMOD Bit Name Reset Function Bits[7:3] 00000 Reserved. DC_SCART 0: SCART input, DC removal inactive 1: SCART input, DC removal active DC_NICAM 0: NICAM input, DC removal inactive 1: NICAM input, DC removal active DC_DEMOD 0: FM input, DC removal inactive 1: FM input, DC removal active Table 19: TV Sound Standards System Mono Sound (MHz) MONO_SID [1:0] LDK_SW DK_DEV [1:0] Stereo Sound (MHz) STEREO_SID [1:0]

DC_REMOVAL_L FM DC Offset Left Registerl DC_REMOVAL_R FM DC Offset Right Register Address: 91h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_REMOVAL_L[7:0] Bit Name Reset Function DC_REMOVAL_L[7:0] 0000 0000 Displays (in two’s complement format) the FM (or AM) DC offset level after demodulation on channel 1 (and removed automatically). In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET1 value in the event of an out-of-standard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF1. See Table 20. Address: 92h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_REMOVAL_R[7:0] Bit Name Reset Function DC_REMOVAL_R[7:0] 0000 0000 Displays (in two’s complement format) the FM (or AM) DC offset level after demodulation on channel 2 (and removed automatically). In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET2 value in the event of an out-of- standard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF2. See Table 20. Table 20: DC_REMOVAL_L/R Range and Resolution FM mode Range (kHz) Resolution (kHz) Small ± 96 0.750 Standard & A2 Standard ± 192 1.5 Medium ± 384 3 Large ± 768 6

PRESCALE_SELECT AM/FM Prescaling Select Register PRESCALE_AM AM Prescaling Register PRESCALE_FM FM Prescaling Register Address: 93h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000000 AM_FM_

Bits[7:1] 0000000 Reserved. AM_FM_SELECT 0 0: FM prescale is applied to demodulator channels 1: AM prescale is applied to demodulator channels Address: 94h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PRESCALE_AM

Bit 7 0 Reserved. PRESCALE_AM[6:0] 0000000 -12 to + 24 dB AM prescaling to normalize the AM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) G (dB) G (dB) 0110000 +24 1101100 -10 0101111 +23.5 1101011 -10.5 0101110 +23 1101010 -11 0101101 +22.5 1101001 -11.5 0101100 +22 1101000 -12 etc. Address: 95h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PRESCALE_FM

PRESCALE_NICAM NICAM Prescaling Register PRESCALE_SCART SCART Prescaling Register Bit Name Reset Function Bit 7 0 Reserved. PRESCALE_FM[6:0] 0001100 -12 to + 24 dB FM prescaling to normalize the FM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = +6 dB) G (dB) G (dB) 0110000 +24 1101100 -10 0101111 +23.5 1101011 -10.5 0101110 +23 1101010 -11 0101101 +22.5 1101001 -11.5 0101100 +22 1101000 -12 etc. Address: 96h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PRESCALE_NICAM

Bit 7 0 Reserved. PRESCALE_NICAM[6:0] 011010 -6 to + 24 dB NICAM prescali ng to normalize the NICAM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = +13 dB) G (dB) G (dB) 0110000 +24 1111000 -4 0101111 +23.5 1110111 -4.5 0101110 +23 1110110 -5 0101101 +22.5 1110101 -5.5 0101100 +22 1110100 -6 etc. Address: 97h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PRESCALE_SCART Bit Name Reset Function Bit [7:6] 00 Reserved.

PRESCALE_I2S_0 I2S_0 Prescaling Register PRESCALE_I2S_1 I2S_1 Prescaling Register PRESCALE_ SCART[5:0] 0000000 -12 to + 12 dB SCART prescaling to normalize the SCART signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) G (dB) G (dB) 011000 +12 101100 -10 010111 +11.5 101011 -10.5 010110 +11 101010 -11 010101 +10.5 101001 -11.5 010100 +10 101000 -12 etc. Address: 98h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PRESCALE_I2S_0[5:0] Bit Name Reset Function Bits [7:6] 00 Reserved. PRESCALE_I2S_0[5:0] 000000 -12 to + 12 dB I2S_0 prescaling to normalize the I2S_0 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) G (dB) G (dB) 011000 +12 101100 -10 010111 +11.5 101011 -10.5 010110 +11 101010 -11 010101 +10.5 101001 -11.5 010100 +10 101000 -12 etc. Address: 99h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PRESCALE_I2S_1[5:0] Bit Name Reset Function Bits [7:6] 00 Reserved. Bit Name Reset Function

PRESCALE_I2S_2 I2S_2 Prescaling Register DEEMPHASIS_DEMATRIX Deemphasis-Dematrix Register PRESCALE_I2S_1[5:0] 000000 -12 to + 12 dB I2S_1 prescaling to normalize the I2S_1 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) G (dB) G (dB) 011000 +12 101100 -10 010111 +11.5 101011 -10.5 010110 +11 101010 -11 010101 +10.5 101001 -11.5 010100 +10 101000 -12 etc. Address: 9Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PRESCALE_I2S_2[5:0] Bit Name Reset Function Bits [7:6] 00 Reserved. PRESCALE_I2S_2[5:0] 000000 -12 to + 12 dB I2S_2 prescaling to normalize the I2S_2 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) G (dB) G (dB) 011000 +12 101100 -10 010111 +11.5 101011 -10.5 010110 +11 101010 -11 010101 +10.5 101001 -11.5 010100 +10 101000 -12 etc. Address: 9Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 NICAM_

NICAM_ DEEMPH_BY PASS FM_DEMATRIX FM_DEEMPH _BYPASS FM_DEEMPH _SW Bit Name Reset Function Bits [7:6] 00 Reserved. Bit Name Reset Function

PEAK_DET_INPUT Peak Detector Input source Register PEAK_DET_L Peak Level Detector Status Register (L channel) NICAM_DEMATRIX 0 Dematrixing fo r NICAM demodulator input: 00: L=ch0, R=ch1 01: L=ch1, R=ch0 NICAM_DEEMPH_ BYPASS 0 0: NICAM deemphasis is not bypassed. 1: NICAM deepmhasis is bypassed. FM_DEMATRIX[3:2] 00 Dematrixi ng for FM demodulator input: 00: L=ch0, R=ch1 01: L=ch0+ch1, R=ch0-ch1 10: L=2ch0-ch1, R=ch1 11: L=(ch0+ch1)/2, R=(ch0-ch1)/2 FM_DEEMPH_ BYPASS 0 0: FM deemphasis is not bypassed. 1: FM deepmhasis is bypassed. FM_DEEMPH_SW 0 0: 50 µs FM deemphasis.| 1: 75 µs FM deepmhasis. Address: 9Dh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEAK_LOCATION 0 PEAK_L_R_RANGE PEAK_DET_INPUT[1:0] Bit Name Reset Function PEAK_LOCATION 0 Peak detector location : 0: Peak detector placed between FM/NICAM Dematrix and Audio Matrix or between I²S Prescale and DownMix 1: Peak detector placed before DC removal (For input saturation detection) Bit 6 0 Reserved. PEAK_L_R_RANGE 0000 Peak L-R range. 0000 : 0 dBFS to -42 dBFS 0001 : -6 dBFS to -48 dBFS 0010 : -12 dBFS to -54 dBFS 0011 : -18 dBFS to -60 dBFS ... PEAK_DET_INPUT[1:0] 00 Peak Level Detector Source Selection 00: AM/FM or I2S 0 10: SCART or I2S 2 01: NICAM or I2S 1 Address: 9Eh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OVERLOAD_L PEAK_L[6:0] Bit Name Reset Function

PEAK_DET_R Peak Level Detector Status Register (R channel) PEAK_DET_L_R Peak Level Detector Status Register (L - R) Bit Name Reset Function OVERLOAD_L[7] 0 Memorise overload on the peak detection. This field can be reset. PEAK_L[6:0] 00000000 Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/ 256 of the full scale (-48 dB). In AM/FM Mono mode, only the PEAK_L[7:0] value must be taken into account. In FM Mono mode, the audio peak level range depends upon the programmed FM bandwidth. The unique difference is that the measurement is done after Sound pre-processing (DC offset removal, Prescaling, De-emphasis and Dematrixing). In FM Stereo mode, the maximum value may be used to check if the incoming signal level is correctly adjusted by the prescaling factor or if there are no FM overmodulation problems (clipping). Programmable values are listed in Table 20. Address: 9Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OVERLOAD_R PEAK_R[6:0] Bit Name Reset Function OVERLOAD_R[7] 0 Memorise overload on the peak detection. This field can be reset. PEAK_R[7:0] 0000000 Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/256 of the full scale (-48 dB). For more information, refer to register PEAK_DET_L. Address: A0h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OVERLOAD_L_R PEAK_L_R[6:0] Bit Name Reset Function OVERLOAD_L_R[7] 0 Memorise overload on the peak detection. This field can be reset. PEAK_L_R[7:0] 0000000 Displays the Difference between L and R (L - R) channels for the audio source selected. For more information, refer to register PEAK_DET_L.

12.14 Matrixing

AUDIO_MATRIX_INPUT Audio Matrix Input Selection Register AUDIO_MATRIX_CONFIG Register Description Address: A2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00000 SCART_ INPUT_ SOURCE HP_INPUT_ SOURCE LS_INPUT_ SOURCE Bit Name Reset Function Bits [7:3] 00000 Reserved. SCART_INPUT_ SOURCE

0 Select input source for SCART output:

0: Demod 1: SCART input HP_INPUT_ SOURCE

0 Select input source for HP output:

0: Demod 1: SCART input LS_INPUT_ SOURCE

0 Select input source for LS output:

0: Demod 1: SCART input Address: A3h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000 SCART_

MATRIX DEMOD_MATRIX[3:0] Bit Name Reset Function Bits [7:5] 000 Reserved. SCART_MATRIX 0 Indicates the SCART input signal matrixing (see Table 22) DEMOD_MATRIX [3:0] 0000 Indicates the demod input signal matrixing (see Table 21)

Note: Switching between Stereo and Forced Mono modes can be done using (FM_L + FM_R)/2 or (NIC_L + NIC_R)/2 configurations. AUDIO_MATRIX_LANGUAGE Register Description Table 21: Demod Matrix Input Mode Language -> Stereo Mono A Mono B Mono C Backup mode demod_mx L R L R L R L R Mono AM/FM with backup 0000 FM FM FM FM Mono AM/FM no backup 0001 - - - FM Zwt St 0100 FM_L FM_R (FM_L + FM_R)/2 (FM_L + FM_R)/2 (FM_L + FM_R)/2 Zwt Dual 0101 FM_M1 FM_M2 FM_M1 FM_M2 (FM_M1 + FM_M2)/2 NICAM Mn, backup 1000 NIC_M1 NIC_M1 NIC_M1 FM Mono AM/FM with backup NICAM Dual backup 1001 NIC_M1 NIC_M2 NIC_M1 NIC_M2 FM Mono AM/FM with backup NICAM St, backup 1010 NIC_L NIC_R (NIC_L + NIC_R)/2 (NIC_L + NIC_R)/2 FM Mono AM/FM with backup NICAM Mn, no backup 1100 NIC_M1 NIC_M1 NIC_M1 FM Mono AM/FM no backup NICAM Dual, no backup 1101 NIC_M1 NIC_M2 NIC_M1 NIC_M2 FM Mono AM/FM no backup NICAM St, no backup 1110 NIC_L NIC_R (NIC_L + NIC_R)/2 (NIC_L + NIC_R)/2 FM Mono AM/FM no backup Table 22: SCART Matrix SCART_MX Stereo Mono A Mono B Mono C Left Right Left Right Left Right Left Right

0 SCART_L SCART_R SCART_L SCART_R (SCART_L +

SCART_R)/2

1 SCART_R SCART_L SCART_R SCART_L (SCART_L +

SCART_R)/2 Address: A4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MUTE_STEREO MUTE_ALL SCART_LANGUAGE[1:0] HP_LANGUAGE[1:0] LS_LANGUAGE[1:0]

DOWNMIX_IN_MODE Register Description Bit Name Reset Function MUTE_STEREO 0 Mute outputs with stereo signal input MUTE_ALL 0 Mute all outputs SCART_ LANGUAGE[1:0]

00 Select language for SCART output

HP_LANGUAGE[1:0] 00 Select language for HPoutput LS_LANGUAGE[1:0]

00 Select language for LS output

00: stereo 01: mono A 10: mono B 11: mono C Address: A6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 LFE_IN MIX_IN_MODE[2:0] Bit Name Reset Function Bits[7:4] 0000 Reserved LFE_IN 0 0: LFE signal is not inputed throught Downmix Block 1: LFE signal is inputed throught Downmix Block MIX_IN_MODE[2:0] 010 see Table 23 Table 23: DownMix IN modes Parameter Coding (Decimal Format) Parameter Field Lebel Function

0 MODE11 Mode not used in STV82x7

1M O D E 1 0 1 / 0 ( C )

2 MODE20 2/0 (L,R)

3 MODE30 3/0 (L,R,C)

4 MODE21 2/1 (L,R,S)

5 MODE31 3/1 (L,R,C,S)

6 MODE22 2/2 (L,R,Ls,Rs)

7 MODE32 3/2 (L,R,C,Ls,Rs)

DOWNMIX_OUT_MODE Register Description Address:A7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 HP_MODE[1:0] SCART_MODE[1:0] LS_OUT_MODE[2:0]

Bit 7 0 Reserved. HP_MODE[1:0] 10 see Table 24 SCART_MODE[1:0] 01 see Table 24 LS_OUT_MODE [2:0] 010 see Table 25 Table 24: DownMix SCART/HP modes Parameter Coding (Decimal Format) Parameter Field Label Function

0 MIX_VCR_OFF Switch off the VCR table setup

1 MIX_VCR_PROLOGIC VCR table setup for Tape outputs (for later

decoding by a Dolby Prologic decoder - Lt,Rt)

2 MIX_VCR_STEREO VCR table setup for Stereo and headphone

listening (Lo,Ro)

3 MIX_COSTOM reserved

Table 25: DownMix LS OUT modes Parameter Coding (Decimal Format) Parameter Field Label Function

0 MODE20t 2/0 Dolby Surround (Lt,Rt)

1M O D E 1 0 1 / 0 ( C )

DOWNMIX_DUAL_MODE Register Description DOWNMIX_CONFIG Register Description Address: A8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 DUAL_ON LS_DUAL_SELECT[1:0] SCART_DU AL_SELECT[1:0] HP_DUAL_SELECT[1:0]

Bit 7 0 Reserved. DUAL_ON 0 0: dual mode disable 1: dual mode enable LS_DUAL_SELECT[1:0] 00 Dual Mono Mode on LS output 00: LS dual stereo 00: LS dual left mono 10: LS dual right mono 11: LS dual mixed SCART_DUAL_SELECT[1:0] 00 Dual Mono Mode on SCART output 00: SCART dual stereo 01: SCART dual left mono 10: SCART dual right mono 11: SCART dual mixed HP_DUAL_SELECT[1:0] 00 Dual Mono Mode on HP output 00: HP dual stereo 01: HP dual left mono 10: HP dual right mono 11: HP dual mixed Address: A9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 SRND_FACTOR[1:0] CENTER_FAC TOR[1:0] LR_UPMIX NORMALIZE Bit Name Reset Function Bits[7:6] 00 SRND_FACTOR [1:0] 00 00: -3dB 01: -4.5dB 10: -6dB 11: -6dB CENTER_FACTOR [1:0] 00 00: -3dB 01: -4.5dB 10: -6dB 11: -4.5dB

12.15 Audio Processing

PRO_LOGIC2_CONTROL Register Description LR_UPMIX 0 0: disable upmixing 1: enable upmixing (DTS specified) NORMALIZE 1 0: disable normalization 1: enable normalization Address: AAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL2_LFE PL2_OUTPUT_DOWNMIX[2: 0] PL2_MODES[2:0] PL2_ACTIVE Bit Name Reset Function PL2_LFE 0 0: Reset the LFE channel 1: Bypass the LFE channel PL2_OUTPUT_ DOWNMIX[2:0] 000 000: not applicable 001: not applicable 010: not applicable 011: 3/0 output mode (L,R,C) 100: 2/1 output mode (L,R,Ls - phantom) 101: 3/1 output mode (L,R,C,Ls) 110: 2/2 output mode (L,R,Ls,Rs - phantom) 111: 3/2 output mode (L,R,C,Ls,Rs) PL2_MODES[2:0] 000 000: Pro Logic 1 Emulation (forced if DPL version) 001: Virtual (DPL2 version only) 010: Music (DPL2 version only) 011: Movie (standard) (DPL2 version only) 100: Matrix (DPL2 version only) 101: Custom (DPL2 version only) 110: not applicable (DPL2 version only) 111: not applicable (DPL2 version only) PL2_ACTIVE 0 0: Dolby Prologic 2 is not active 1: Dolby Prologic 2 is active Table 26: Prologic II Decode Mode Configuration PL2 Mode Decode Mode Dimension Center Width Auto- Balance Panorama Surround Coherence SUR Filtering

0 Pro Logic

1 Virtual 30 1 0 1 0

2 Music xx 0 x 1 1

Note: (x = user defined parameter) PCM_SRND_DELAY Register Description PCM_CENTER_DELAY Register Description

3 Movie/

4 Matrix 30 0 0 1 1

5 Custom xx x x x x

Address: ABh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 SNRD_DELAY[4:0] Bit Name Reset Function Bits[7:5] 000 Reserved. SNRD_DELAY[4:0] 00000 Surround Channel Delay range: 0 to 30 (in ms) Address: ACh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000 C E N T E R _ D E L A Y [ 3 : 0 ]

Bits[7:4] 0000 Reserved. CENTER_DELAY[3:0] 0000 Center Channel Delay range: 0 to 10 (in ms) Table 26: Prologic II Decode Mode Configuration (Continued) PL2 Mode Decode Mode Dimension Center Width Auto- Balance Panorama Surround Coherence SUR Filtering

PRO_LOGIC2_CONFIG Register Description See Table 26: Prologic II Decode Mode Configuration for programmation of these bits depending on the decode mode. PRO_LOGIC2_DIMENSION Register Description Address: ADh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL2_LFE 0 0 PL2_SRND_FILTER[1:0] PL2_RS_ POLARITY PL2_ PANORAMA PL2_ AUTOBALANCE Bit Name Reset Function Bits[7:6] 00 Reserved. PL2_SRND_FILTR[1:0] 00 00: 0: Off 01: 1: Shelf Filter (for music and matrix modes) 10: 2: 7kHz LP 11: 3: not applicable PL2_RS_POLARITY 0 0: Rs polarity normal 1: Rs polarity inverted PL2_PANORAMA 0 0: Panorama Off 1: Panorama On PL2_AUTOBALANCE 0 0: Autobalance Off 1: Autobalance On Address: AEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 PL2_C_WIDTH 0 PL2_DIMENSION

Bit 7 0 Reserved. PL2_C_WIDTH[2:0] 000 000: 0, no spread = OFF 001: 20 010: 28 011: 36 100: 54 101: 62 110:69 111: 90, phantom Bit 3 0 Reserved.

See Table 26: Prologic II Decode Mode Configuration for programmation of these bits depending on the decode mode. PRO_LOGIC2_LEVEL Register Description NOISE_GENERATOR Register Description PL2_DIMENSION[2:0] 000 000: -3, most surround 001: -2 010: -1 011: 0, neutral = OFF 100: 1 101: 2 110:3, most center 111: not applicable Address: AFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL2_LEVEL Bit Name Reset Function PL2_LEVEL[7:0] 00000000 Input Gain attenuation: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB Address: B0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10_DB_ ATTENUATE SRIGHT_ NOISE SLEFT_ NOISE SUB_ NOISE CENTER_ NOISE RIGHT_ NOISE LEFT_ NOISE NOISE_ON Bit Name Reset Function 10_DB_ATTENUATE 0 0: noise is outputed with full range 1: noise is outputed with a 10dB attenuation SRIGHT_NOISE 0 1: Generates noise on LS right surround output SLEFT_NOISE 0 1: Generates noise on LS left surround output SUB_NOISE 0 1: Generates noise on LS subwoofer output CENTER_NOISE 0 1: Generates noise on LS center output RIGHT_NOISE 0 1: Generates noise on LS right output Bit Name Reset Function

TRUSRND_CONTROL Register Description TRUSRND_INPUT_GAIN Register Description LEFT_NOISE 0 1: Generates noise on LS left output NOISE_ON 0 0: Noise Generation not active 1: Noise Generation is active Address: B1h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 TRUSRND_

MONO_SRND TRUSRND_INPUT_ MODE[3:0] TRUSRND_ MODE TRUSRND_ ON Bit Name Reset Function Bit 7 0 Reserved. TRUSRND_MONO _SRND 0 0: Left mono Srnd mode 1: Right mono Srnd mode TRUSRND_ INPUT_ MODE[3:0] 0000 0000: Mono 0001: L/R stereo (SRS mode) 0010: L/R/S (SRS mode, Prologic 1 Process) 0011: L/R/Ls/Rs (SRS mode) 0100: L/R/C (TruSurround mode) 0101: L/R/C/S (TruSurround mode, Prologic 1 Process) 0110: L/R/C/Ls/Rs (TruSurround mode) 0111: Lt/Rt (TruSurround mode) 1000: L/R/C/Ls/Rs (SRS mode, BS Digital Broadcast) 1001: L/R/C/Ls/Rs (TruSurround, Prologic 2 Music mode) TRUSRND_MODE 0 0: TruSurround mode 1: Bypass mode TRUSRND_ON 0 0: TruSurround OFF 1: TruSurround ON Address: B6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUSRND_INPUT_GAIN[7:0] Bit Name Reset Function

TRUSRND_HP_DCL Register Description TRUSRND_DC_ELEVATION Register Description Bit Name Reset Function TRUSRND_INPUT_ GAIN[7:0] 0000 0000 Input Gain attenuation: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB Address: B7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00000 DIALOG_

CLARITY_ON HEADPHONE _ON 0 Bit Name Reset Function Bits[7:2] 00000 Reserved. DIALOG_ CLARITY_ON 0 0: Dialog Clarity OFF 1: Dialog Clarity ON HEADPHONE_ON 0 Activate HP mode in TruSurround XT: 0: HP mode OFF 1: HP mode ON Bit [0] 0 Reserved. Address: B8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUSRND_DC_ELEVATION[7:0] Bit Name Reset Function TRUSRND_DC_ ELEVATION[7:0] 0000 1100 Dialog Calrity Elevation: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB

TRUBASS_LS_CONTROL Register Description TRUBASS_LS_LEVEL Register Description TRUBASS_HP_CONTROL Register Description Address: BAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 TRUBASS_LS_SIZE[2:0] TRUBASS_ LS_ON Bit Name Reset Function Bits[7:3] 00000 Reserved. TRUBASS_LS_SIZE[2:0] 011 000: LF response at 40Hz 001: LF response at 60Hz 010: LF response at 100Hz 011: LF response at 150Hz 100: LF response at 200Hz 101: LF response at 250Hz 110: LF response at 300Hz 111: LF response at 400Hz TRUBASS_LS_ON 0 0: LS TruBass OFF 1: LS TruBass ON Address: BBh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUBASS_LS_LEVEL[7:0] Bit Name Reset Function TRUBASS_LS_ LEVEL[7:0] 0000 1001 Define the amount of SRS TruBass effect for LS outputs: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB Address: BCh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 TRUBASS_HP_SIZE[2:0] TRUBASS_HP _ON

TRUBASS_HP_LEVEL Register Description SVC_LS_CONTROL Register Description Bit Name Reset Function Bits[7:3] 00000 Reserved. TRUBASS_HP_ SIZE[2:0] 011 000: LF response at 40Hz 001: LF response at 60Hz 010: LF response at 100Hz 011: LF response at 150Hz 100: LF response at 200Hz 101: LF response at 250Hz 110: LF response at 300Hz 111: LF response at 400Hz TRUBASS_HP_ON 0 0: HP TruBass OFF 1: HP TruBass ON Address: BDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUBASS_HP_LEVEL[7:0] Bit Name Reset Function TRUBASS_HP_ LEVEL[7:0] 0000 1001 Define the amount of SRS TruBass effect for HP outputs: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB Address: BEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 SVC_LS_INPUT[1:0] SVC_LS_AMP SVC_LS_ON Bit Name Reset Function Bits[7:4] 0000 Reserved. SVC_LS_INPUT[1:0] Select input for peak detection in multichannel mode: 00: Left/Right 01: Center 10: Left/Right/Center SVC_LS_AMP 1 0: 0dB amplification in auto-mode 1: +6dB amplification in auto-mode SVC_LS_ON 0 0: Manual mode(simple prescaler) 1: Automatic mode

SVC_LS_TIME_TH Register Description Address: BFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SVC_LS_TIME[2:0] SVC _LS_THRESHOLD[4:0] Bit Name Reset Function SVC_LS_TIME[2:0] 100 Time constant for the amplification (6dB gain step) in automatic mode: 000: 30ms 001: 200ms 010: 500ms 011: 1s 100: 16s 101: 32s 110: 64s 111: 128s SVC_LS_ THRESHOLD[4:0] 11000 see Table 27 and Table 28. Table 27: Gain (threshold field) values in Manual mode Manual Mode Gain (dB) 00101 +15.5 00100 +12 00011 +9.5 00010 +6 00001 +3.5 00000 0 11111 -2.5 11110 -6 11101 -8.5 11100 -12 11011 -14.5 11010 -18 11001 -20.5 11000 -24 10111 -26.5 10110 -30

SVC_HP_CONTROL Register Description SVC_HP_TIME_TH Register Description Table 28: Threshold values in Automatic mode Automatic Mode Threshold (dB) 11111 -2.5 11110 -6 11101 -8.5 11100 -12 11011 -14.5 11010 -18 11001 -20.5 11000 -24 10111 -26.5 10110 -30 Address: C0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 SVC_

LHP_AMP SVC_HP_ON Bit Name Reset Function Bits[7:2] 000000 Reserved. SVC_LHP_AMP 1 0: 0dB amplification in auto-mode 1: +6dB amplification in auto-mode SVC_HP_ON 0 0: Manual mode (simple prescaler) 1: Automatic mode Address: C1h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SVC_HP_TIME[2:0] SVC _HP_THRESHOLD[4:0]

SVC_LS_GAIN Register Description SVC_HP_GAIN Register Description Bit Name Reset Function SVC_HP_TIME[2:0] 100 Time constant for the amp lification (6dB gain step) in automatic mode: 000: 30ms 001: 200ms 010: 500ms 011: 1s 100: 16s 101: 32s 110: 64s 111: 128s SVC_HP_ THRESHOLD[4:0] 11000 see Table 27 and Table 28 Address: C2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 SVC_LS_GAIN[6:0]

Bit 7 0 Reserved. SVC_LS_GAIN[6:0] 0000000 Set “make-up” gain applied at SVC LS output: 0000000: +0dB 0000001: +0.5dB ... 0101110: +23dB 0101111: +23.5dB 0110000: +24dB Address: C3h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 SVC_HP_GAIN[6:0]

Bit 7 0 Reserved.

STSRND_CONTROL ST WideSurround Control Register STSRND_FREQ ST WideSurround Sound Frequency SVC_HP_GAIN[6:0] 0000000 Set “make-up” gain applied at SVC HP output: 0000000: +0dB 0000001: +0.5dB ... 0101110: +23dB 0101111: +23.5dB 0110000: +24dB Address: C4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00000 STSRND_

STSRND_ MODE STSRND_ON Bit Name Reset Function Bits[7:3] 00000 Reserved. STSRND_STEREO 0 ST WideSurround Mode 0: ST WideSurround Sound in Mono mode (Default) 1: ST WideSurround Sound in Stereo mode STSRND_MODE 0 ST WideSurround Sound Stereo Mode 0: Movie Mode 1: Music Mode STSRND_ON 0 ST WideSurround Sound Enable 0: ST WideSurround Sound is disabled 1: ST WideSurround Sound is enabled Address: C5h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 STSRND_BASS[1:0] ST SRND_MEDIUM[1:0] ST SRND_TREBLE[1:0] Bit Name Reset Function Bits[7:6] 00 Reserved. STSRND_BASS[1:0] 01 Defines the bass fr equency effect for ST WideSurround Sound. Programmable values are listed in Table 29. STSRND_MEDIUM[1:0] 01 Defines the m edium frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 29. Bit Name Reset Function

STSRND_LEVEL ST WideSurround Gain Register OMNISURROUND_CONTROL Register Description STSRND_TREBLE[1:0] 01 Defines the treb le frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 29. Table 29: Phase Shifter Center Frequencies Phase Shifter Center Frequency BASS_FREQ[1:0] MEDIUM_FREQ [1:0] TREBLE_FREQ[1:0] 00 40 Hz 202 Hz 2 kHz 01 (Default) 90 Hz 416 Hz 4 kHz 10 120 Hz 500 Hz 5 kHz 11 160 Hz 588 Hz 6 kHz Address: C6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STSRND_GAIN[7:0] Bit Name Reset Function STSRND_GAIN[7:0] 10000000 Defines the ST WideS urround Sound component gain in linear scale. Level (%) Level (%) 1000 0000 (Default) 100% 0000 0100 3.1% 0111 1111 99.2% 0000 0011 2.3% 0111 1110 98.4% 0000 0010 1.6% 0111 1101 97.6% 0000 0001 0.8% Address: C7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFE ST_VOICE[1:0] FRONT_ BYPASS OMNI_SURND_INPUT_MODE[3:0] OMNISRND_ON Bit Name Reset Function LFE 0 0: Do not use LFE channel 1: Generate LFE channel Bit Name Reset Function

ST_DYNAMIC_BASS Register Description ST_VOICE[1:0] 00 00: OFF 01: Low 10: Mid 11: High FRONT_BYPASS 0 Forced to 0 OMNISRND_ INPUT_ MODE[3:0] 0000 000: Mono 001: L/R stereo 010: L/R/S 011: L/R/Ls/Rs 100: L/R/C 101: L/R/C/S 110: L/R/C/Ls/Rs 111: Lt/Rt (Passive matrix) OMNISURND_ON 0 0: OmniSurround OFF 1: OmniSurround ON Address: C8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASS_LEVEL[4:0] BASS_FREQ[1:0] DYN_BASS_ ON Bit Name Reset Function BASS_LEVEL[4:0] 00000 Set ST Dynamic Bass effect level: 00000: +0d B 00001: +0.5 dB ... 11101: +14.5 dB 11110: +15 dB 11111: +15.5 dB BASS_FREQ[1:0] 00 00: 100 Hz Cut-Off frequency 01: 150 Hz Cut-Off frequency 10: 200 Hz Cut-Off frequency 11: Reserved DYN_BASS_ON 0 0: ST Dynamic Bass OFF 1: ST Dynamic Bass ON Bit Name Reset Function

12.16 5-Band Equalizer / B ass-Treble for Loudspeakers LS_EQ_BT_CTRL Loudspeakers Equalizer Control Register EQ_BANDX_GAIN Loudspeakers Equalizer Gain Register for BandX Address: C9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 LS_EQ_BT_

SW LS_EQ_ON Bit Name Reset Function Bits[7:2] 000000 Reserved. LS_EQ_BT_SW 0 5-Band Equalizer or Bass-Teble selection 0: 5-Band Equalizer is selected for Loudspeakers. 1: Bass-Treble is selected for Loudspeakers. LS_EQ_ON 1 5-Band Equalizer/Bass-Treble for loudspeakers Enable 0: 5-Band Equalizer/Bass-Teble is disabled 1: 5-Band Equalizer/Bass-Teble is enabled (Default) Address: CAh to CEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EQ_BANDX Bit Name Reset Function EQ_BANDX[7:0] 0000 0000 BandX gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Band1: 100 Hz, Band2: 330 Hz, Band3: 1 KHz, Band4: 3.3 KHz, Band5: 10 KHz, see Table 30. Table 30: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values) Value Gain G (dB) 00110000 +12 00101111 +11.75 00101110 +11.50 00000000 (Default) 0 10101110 -11.50

LS_BASS_GAIN Loudspeakers Bass Gain Register LS_TREBLE_GAIN Loudspeakers Treble Gain Register

12.17 Headphone Bass-Treble

HP_BT_CONTROL Headphone Bass-Treble Control Register 10101111 -11.75 10110000 -12 Address: CFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_BASS[7:0] Bit Name Reset Function LS_BASS[7:0] 0000 0000 Bass gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Address: D0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_TREBLE Bit Name Reset Function LS_TREBLE[7:0] 0000 0000 Treble gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Address: D1h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000000 H P _ B T _ O N

Bits [7:1] 0000000 Reserved. Table 30: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values) Value Gain G (dB)

HP_BASS_GAIN Headphone Bass Gain HP_TREBLE_GAIN Headphone Treble Gain OUTPUT_BASS_MNGT Register Description HP_EQ_ON 1 Bass-Treble for headphone Enable 0: Bass-Teble is disabled 1: Bass-Teble is enabled (Default) Address: D2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_BASS_GAIN[7:0] Bit Name Reset Function HP_BASS_ GAIN[7:0]

00000000 Gain Tuning of Headphone Bass Frequency

Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 30. Address: D3h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_TREBLE_GAIN[4:0] Bit Name Reset Function HP_TREBLE_ GAIN[7:0]

00000000 Gain Tuning of Headphone Treble Frequency

Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 30. Address: D4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASS_ MANAGE_ON 0 SUB_ACTIVE GAIN_ SWITCH 0 OCFG_NUM[2:0] Bit Name Reset Function

LS_LOUDNESS Register Description Bit Name Reset Function BASS_MANAGE_ON 1 0: BassManagement disables 1: BassManagement enabled Bit 6 0 Reserved. SUB_ACTIVE 0 0: Subwoofer output is disabled (only in config 2,3,4) 1: Subwoofer output is active GAIN_ SWITCH 0 0: Level adjustment ON 1: Level adjustment OFF OCFG_NUM 000 000: Bass Management Configuration 0 (refer to Figure 13) 001: Bass Management Configuration 1 (refer to Figure 14) 010: Bass Management Configuration 2 (refer to Figure 15) 011: Bass Management Configuration 3 (refer to Figure 16) 100: Bass Management Configuration 4 (refer to Figure 17) Bit 3 0 Reserved. Address: D5h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 LS_LOUD_THRESHOLD[2:0] LS_LOUD_GAIN_HR[2:0] LS_

LOUD_ON Bit Name Reset Function Bit 7 0 Reserved. LS_LOUD_ THRESHOLD[2:0]

000 Define the volume threshold level since which loudness effect is applied :

000: 0dB 001: -6dB 010: -12dB 011: -18dB 100: -24dB 101: -32dB 110: -36dB 111: -42dB LS_LOUD_GAIN_ HR[2:0]

010 Define the amount of Treble added by loudness effect:

000: 0dB 001: 3dB 010: 6dB 011: 9dB 100: 12dB 101: 15dB 110: 18dB LS_LOUD_ON 0 0: Loudness is not active on LS output 1: Loudness is active on LS output

HP_LOUDNESS Register Description

12.18 Volume

VOLUME_MODES Set the Volume Modes Address: D6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 HP_LOUD_THRESHOLD[2: 0] HP_LOUD_GAIN_HR[2:0] HP_

LOUD_ON Bit Name Reset Function Bit 7 0 Reserved. HP_LOUD_ THRESHOLD[2:0] 000: 0dB 001: -6dB 010: -12dB 011: -18dB 100: -24dB 101: -32dB 110: -36dB 111: -42dB HP_LOUD_GAIN_ HR[2:0] 000: 0dB 001: 3dB 010: 6dB 011: 9dB 100: 12dB 101: 15dB 110: 18dB HP_LOUD_ON 0 0: Loudness is not active on HP output 1: Loudness is active on HP output Address: D7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANTICLIP_HP _VOL_CLAMP ANTICLIP_LS _VOL_CLAMP 00 SCART_ VOLUME_ MODE SRND_ VOLUME_ MODE HP_ VOLUME_ MODE LS_ VOLUME_ MODE Bit Name Reset Function ANTICLIP_HP_VOL _CLAMP

1 The output level is clamped depending on the HP Bass-Treble value to avoid any possible signal

clipping on HP output. 0: Volume clamp on HP output is not active 1: Volume clamp on HP output is active

LS_L_VOLUME_MSB Register Description LS_L_VOLUME_LSB Register Description ANTICLIP_LS_VOL _CLAMP

1 The output level is clamped depending on the LS Equalizer or LS Bass-Treble value to avoid any

possible signal clipping on LS output. 0: Volume clamp on LS output is not active 1: Volume clamp on LS output is active Bits[5:4] 00 Reserved. SCART_VOLUME_ MODE

0 Volume mode for SCART output:

0: Independant 1: Differential SRND_VOLUME_ MODE

1 Volume mode for Headphone output:

0: Independant 1: Differential HP_VOLUME_ MODE

1 Volume mode for Surround output:

0: Independant 1: Differential LS_VOLUME_ MODE

1 Volume mode for LS output:

0: Independant 1: Differential Address: D8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_L_VOLUME_MSB[7:0] Bit Name Reset Function LS_L_VOLUME_ MSB[7:0] 1001 1000 LS 10 bits volume Left channel 8 MSB in independent mode or LS 10 bits volume Left and Right channels 8 MSB in differential mode. See Figure 19: Volume Control on page 36 for range values. Address: D9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _L_VOLUME_LSB[1:0]

Bits[7:2] 000000 Reserved. Bit Name Reset Function

The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_L_VOLUME_MSB x 0.5 + Decimal value of LS_L_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_R_VOLUME_MSB Register Description LS_R_VOLUME_LSB Register Description LS_C_VOLUME_MSB Register Description LS_L_VOLUME_ LSB[1:0]

00 LS 10 bits volume Left channel 2 LSB in independent mode or LS 10 bits volume Left and Right

channels 2 LSB in differential mode. See Figure 19: Volume Control on page 36 for range values. Address: DAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_R_VOLUME_MSB[7:0] Bit Name Reset Function LS_R_VOLUME_ MSB[7:0] 0000000 LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits Left and Right balance 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: DBh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _ R _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved. LS_R_VOLUME_ LSB[1:0]

00 LS 10 bits volume Right channel 2 LSB in independent mode or LS 10 bits Left and Right balance

2 LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: DCh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_C_VOLUME_MSB[7:0] Bit Name Reset Function

LS_C_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_C_VOLUME_MSB x 0.5 + Decimal value of LS_C_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SUB_VOLUME_MSB Register Description Bit Name Reset Function LS_C_VOLUME_ MSB[7:0] 1001 1000 LS 10 bits volume Center channel 8 MSB See Figure 19: Volume Control on page 36 for range values. Address: DDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _ C _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved. LS_C_VOLUME_ LSB[1:0]

00 LS 10 bits volume Center channel 2 LSB

See Figure 19: Volume Control on page 36 for range values. Address: DEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SUB_VOLUME_MSB[7:0] Bit Name Reset Function LS_SUB_ VOLUME_MSB[7:0] 1001 1000 LS 10 bits volume Subwoofer channel 8 MSB See Figure 19: Volume Control on page 36 for range values.

LS_SUB_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SUB_VOLUME_MSB x 0.5 + Decimal value of LS_SUB_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SL_VOLUME_MSB Register Description Address: DFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _ S U B _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved. LS_SUB_ VOLUME_LSB[1:0]

00 LS 10 bits volume Subwoofer channel 2 LSB

See Figure 19: Volume Control on page 36 for range values. Address: E0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SL_VOLUME_MSB[7:0] Bit Name Reset Function LS_SL_VOLUME_ MSB[7:0] 1001 1000 LS 10 bits volume Left surround channel 8 MSB in independent mode or LS 10 bits Left and Right surround volume 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37.

LS_SL_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SL_VOLUME_MSB x 0.5 + Decimal value of LS_SL_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SR_VOLUME_MSB Register Description LS_SR_VOLUME_LSB Register Description Address: E1h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _ L S _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved. LS_LS_VOLUME_ LSB[1:0]

00 LS 10 bits volume Left surround channel 2 LSB in independent mode or LS 10 bits Left and Right

surround volume 2 LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: E2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SR_VOLUME_MSB[7:0] Bit Name Reset Function LS_SR_VOLUME_ MSB[7:0]

00000000 LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits surround Left and Right

balance 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: E3h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 L S _ S R _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved.

The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SR_VOLUME_MSB x 0.5 + Decimal value of LS_SR_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_MASTER_VOLUME_MSB Register Description LS_MASTER_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_MASTER_VOLUME_MSB x 0.5 + Decimal value of LS_MASTER_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SR_VOLUME_ LSB[1:0]

00 LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits surround Left and Right

balance 2 LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: E4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_MASTER_VOLUME_MSB[7:0] Bit Name Reset Function LS_MASTER_ VOLUME_MSB[7:0] 1110100 LS 10 bits volume Master channel 8 MSB See Figure 19: Volume Control on page 36 for range values. Address: E5h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 LS_MASTER_VOLUME

_LSB[1:0] Bit Name Reset Function Bits[7:2] 000000 Reserved. LS_MASTER_ VOLUME_LSB[1:0]

00 LS 10 bits volume Master channel 2 LSB

See Figure 19: Volume Control on page 36 for range values. Bit Name Reset Function

HP_L_VOLUME_MSB Register Description HP_L_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of HP_L_VOLUME_MSB x 0.5 + Decimal value of HP_L_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). HP_R_VOLUME_MSB Register Description Address: E6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_L_VOLUME_MSB[7:0] Bit Name Reset Function HP_L_VOLUME_ MSB[7:0] 1001 1000 HP 10 bits volume Left channel 8 MSB in independent mode or HP 10 bits Left and Right volume 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: E7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 H P _L_VOLUME_LSB[1:0]

Bits[7:2] 000000 Reserved. HP_L_VOLUME_ LSB[1:0]

00 HP 10 bits volume Left channel 2 LSB in independent mode or HP 10 bits Left and Right volume 2

LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: E8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_R_VOLUME_MSB[7:0] Bit Name Reset Function HP_R_VOLUME_ MSB[7:0] 0000000 HP 10 bits volume Right channel 8 MSB in independent mode or HP 10 bits Left and Right balance 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37.

HP_R_VOLUME_LSB Register Description SCART_L_VOLUME_MSB Register Description Address: E9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 H P _ R _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved. HP_R_VOLUME_ LSB[1:0]

00 HP 10 bits volume Right channel 2 LSB in i ndependent mode or HP 10 bits Left and Right balance

2LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: EAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCART_L_VOLUME_MSB[7:0] Bit Name Reset Function SCART_L_ VOLUME_MSB[7:0] 1101110 1 SCART 10 bits volume Left channel 8 MSB in independent mode or SCART10 bits Left and Right volume 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37.

SCART_L_VOLUME_LSB Register Description The volume value is defined by the following formula: Vol (dB) = Decimal value of SCART_L_VOLUME_MSB x 0.5 + Decimal value of SCART_L_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). SCART_R_VOLUME_MSB Register Description SCART_R_VOLUME_LSB Register Description Address: EBh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 S C A R T _L_VOLUME_LSB[1:0]

Bits[7:2] 000000 Reserved. SCART_L_ VOLUME_LSB[1:0]

00 SCART 10 bits volume Left channel 2 LSB in independent mode or SCART10 bits Left and Right

volume 2 LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: ECh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCART_R_VOLUME_MSB[7:0] Bit Name Reset Function SCART_R_ VOLUME_MSB[7:0]

11011101 SCART 10 bits volume Right channel 8 MSB in independent mode or SCART10 bits Left and Right

balance 8 MSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: EDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 S C A R T _ R _ V O L U M E _ L S B [ 1 : 0 ]

Bits[7:2] 000000 Reserved.

12.19 Beeper

BEEPER_ON Beeper Activation Register BEEPER_MODE Beeper Control Register SCART_R_ VOLUME_LSB[1:0]

00 SCART 10 bits volume Right channel 2 LSB in independent mode or SCART10 bits Left and Right

balance 2 LSB in differential mode. See Figure 19: Volume Control on page 36 or Figure 20: Differential Balance on page 37. Address: EEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000000 BEEPER_ON

Bits [7:1] 0000000 Reserved. BEEPER_ON 0 Beeper Enable 0: Beeper muted (Default.) 1: Beeper enabled. Address: EFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 BEEPER_DURATION BEEPER_ PULSE BEEPER_PATH Bit Name Reset Function Bits [7:5] 000 Reserved. BEEPER_ DURATION [4:3] 00 Define beeper duration when set to pulse mode. BEEPER_PULSE 0 Set beeper pulse mode 0: Pulse mode selected. 1: Continuous mode selected. BEEPER_PATH [1:0] 11 Set the output channels when beeper is active 00: no channels. 01: Loudspeakers only. 10: Headphone only. 11: Loudspeakers and Headphone selected. Bit Name Reset Function

BEEPER_FREQ_VOL Beeper Frequency and Volume Settings Register

12.20 Mute

MUTE_DIGITAL Register Description Address: F0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BEEP_FREQ[2:0] BEEP_VOL[4:0] Bit Name Reset Function BEEP_FREQ[2:0] 011 Defines the frequency of the beeper tone from 62.5 Hz to 8 kHz in octaves 000: 62.5 Hz 100: 1 kHz 001: 125 Hz 101: 2 kHz 010: 250 Hz 110: 4 kHz 011: 500 Hz (Default) 111: 8 kHz BEEP_VOL[4:0] 10000 Defines the Beeper volume from 0 to -93 dB in steps of 3 dB. 11111: 0 dB (1 V RMS). . . 11110: -3 dB 00011: -84 dB 11101: -6 dB 00010: -87 dB ... 00001: -90 dB 10000: -48 dB (Default) 00000: -93 dB Address: F1h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOSTD_ MUTE_ON 00 SCART_ D_MUTE SRND_HP_D_ MUTE SUB_ D_MUTE D_MUTE LS_ D_MUTE Bit Name Reset Function AUTOSTD_MUTE_ON 1 0: autostandard can not mute outputs 1: autostandard can mute outputs when no signal is detected Bit s[6:5] 00 SCART_D_MUTE

1 SCART left/right digital soft mute

0: signal un-muted 1: signal muted SRND_HP_D_MUTE

1 LS Surround/HP left/right digital soft mute

0: signal un-muted 1: signal muted SUB_D_MUTE

1 LS Subwoofer digital soft mute

0: signal un-muted 1: signal muted

12.21 S/PDIF

S/PDIF_OUT_CONFIG S/PDIF Output Configuration Register

12.22 Headphone Configuration

HEADPHONE_CONFIG Headphone Configuration Register C_D_MUTE

1 LS Center digital soft mute

0: signal un-muted 1: signal muted LS_D_MUTE

1 LS left/right digital soft mute

0: signal un-muted 1: signal muted Address: F2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00000 S/PDIF_OUT_

MUTE S/PDIF_OUT_SELECT Bit Name Reset Function Bits [7:3] 00000 Reserved. S/PDIF_OUT_ MUTE

1 S/PDIF Output Mute:

0: S/PDIF Output unmuted. 1: S/PDIF Output muted. S/PDIF_OUT_ SELECT[1:0]

00 S/PDIF Output channel selection:

00: output SCART signal 01: output LS L-R signal 10: output C/SUB signal 11: ouptut Sur/HP signal Address: F3h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000 H P _ F O R C E HP_LS_

HP_DET_ ACTIVE HP_ DETECTED Bit Name Reset Function Bits [7:4] 0000 Reserved. Bit Name Reset Function

12.23 DAC Control

DAC_CONTROL DAC Control Register HP_FORCE 0 1: force output of t he HP signal (bypass surround) HP_LS_MUTE 0 0: when HP is detected and active, LS are not muted 1: when HP is detected and active, LS are muted HP_DET_ACTIVE 1 0: HP detection is not active 1: HP detection is active, when HP detected, Surround signal is bypassed and HP signal is output on HP HP_DETECTED 0 1: When a signal is detected on HP_DET pin (STATUS) Address: F4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 S/PDIF_MUX DAC_SCART_ MUTE DAC_SHP_ MUTE DAC_CSUB_ MUTE DAC_LSLR_ MUTE POWER_UP Bit Name Reset Function Bits [7:6] 00 Reserved. S/PDIF_MUX 0 redirect external or internal S/ PDIF source to S/PDIF output : 0: internal S/PDIF 1: external S/PDIF DAC_SCART_MUTE

1 SCART left/right analog soft mute

0: signal un-muted 1: signal muted DAC_SHP_MUTE

1 Surround/HP left/right analog soft mute

0: signal un-muted 1: signal muted DAC_CSUB_MUTE

1 Center/Subwoofer analog soft mute

0: signal un-muted 1: signal muted DAC_LSLR_MUTE

1 LS left/right analog soft mute

0: signal un-muted 1: signal muted POWER_UP 10 : D A C s P o w e r O F F 1: Power ON Bit Name Reset Function

SPDIF_CHANNEL_STATUS Register Description

12.24 AutoStandard Co efficients Settings

AUTOSTD_COEFF_CTRL Register Description Address: F9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHANNEL_STATUS EMPHASIS COPYRIGHT NON_AUDIO PRO_CON Bit Name Reset Function CHANNEL_STATUS[7:6] 00 Channel status mode: 00: Mode zero other values: reserved EMPHASIS[5:3] 000 Emphasis: accord ing to IEC60958 specification COPYRIGHT 0 Copyright: 0: Asserted 1: Not asserted NON_AUDIO 0 Non-audio: 0: Linear PCM 1: Non-audio signal PRO_CON 0 Select Professional or Consumer modes: 0: Consumer 1: Professional Address: FBh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000 AUTOSTD_COEFF_

CTRL[1:0] Bit Name Reset Function Bits [7:2] 000000 Reserved. AUTOSTD_COEFF _CTRL[1:0]

01 Control the Demod filter coeff table settings

01: init Coeffs to ROM values 10: Update Coeffs with I2C value

AUTOSTD_COEFF_INDEX_MSB Register Description AUTOSTD_COEFF_INDEX_LSB Register Description AUTOSTD_COEFF_VALUE Register Description Address: FCh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000000 AUTOSTD_ COEFF_ INDEX_MSB Bit Name Reset Function Bits [7:2] 0000000 Reserved. AUTOSTD_COEFF _INDEX_MSB

0 FIR Coefficients table index (MSB)

Address: FDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOSTD_COEFF_INDEX_LSB[7:0] Bit Name Reset Function AUTOSTD_COEFF _INDEX_LSB[7:0] 0000

0000 FIR Coefficients table index (LSB)

Address: FEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOSTD_COEFF_VALUE[7:0] Bit Name Reset Function AUTOSTD_COEFF _VALUE[7:0] 0000

0000 Reserved

Test Conditions: TOPER = 25° C, VCC_H = 8 V, VXX_18 = 1.8V, VXX_33 = 3.3V, Crystal at 27MHz, default register values for synthesizer, otherwise specified.

13.1 Absolute Maximum Ratings

13.2 Thermal Data

13.3 Power Supply Data

Symbol Parameter Value Units VXX_18 Analog and Digital 1.8 V Supply Voltage (VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC) 2.5 V VXX_33 Analog and Digital 3.3 V Supply Voltage (VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO) 4.0 V HVCC Analog Supply High Voltage (VCC_H) 8.8 V VESD Capacitor 100 pF discharged via 1.5 kΩ serial resistor (Human Body Model) 4 kV TOPER Operating Ambient Temperature 0, +70 °C TSTG Storage Temperature -55 to +150 °C Symbol Parameter Value Units RthJA Junction-to-Ambient Thermal Resistance 42 °C/W Symbol Parameter Min. Typ. Max. Units VXX_18 Analog and Digital 1.8 V Supply Voltage (VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC) 1.70 1.80 1.90 V VXX_33 Analog and Digital 3.3 V Supply Voltage (VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO) 3.13 3.30 3.47 V HVCC Analog Supply High Voltage (VCC_H) 7.6 8.0 8.4 V IVDD18 Current Consumption for Digital 1.8 V Supply (VCC18_CLK2, VDD18, VDD18_CONV, VDD18_ADC) 210 mA IVDD33 Current Consumption for Digital 3.3 V Supply ( VDD33_IO1, VDD33_IO2) 10 mA IVCC18 Current Consumption for Analog 1.8 V Supply (VCC18_CLK1, VCC18_IF) 50 mA IVCC33 Current Consumption for Analog 3.3 V Supply (VCC33_SC, VCC33_LS, VDD33_CONV, VCC_NISO) 65 mA IVCC_H Current Consumption for Analog Supply High Voltage (8 V) 4 mA PDTOT Total Power Dissipation 750 mW

STV82x7 Electrical Characteristics

13.4 Crystal Oscillator

13.5 Analog Sound IF Signal

Symbol Parameter Min. Typ. Max. Units fP Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor) 27 MHz DF/FP Frequency Tolerance at 25 °C -30 +30 ppm DF/FT Frequency Stability versus Temperature within a range from 0 to 70 °C -30 +30 ppm C1 Motional Capacitor 15 fF RS Serial Resistance 30 Ω CS Shunt Capacitance 7p F Symbol Parameter Test Condi tions Min. Typ. Max. Units BANDSIF SIF Frequency Flatness AGC_ERR at 0, frequency range from 4 to 7MHz 0.6 3 dB RINSIF SIF Input Resistance 60 72 85 k Ω DCINSIF SIF Input DC Level 0.9 V CINSIF SIF Input Capacitance 3 pF FM Carrier VSIFFM SIF Input Sensitivity SNR 40dB RMS unweighted, 20Hz-15kHz, Standard B/G 27 kHz FM Deviation,1kHz 350 µV PP DEVFM FM Maximum Deviation FM50k (Standard) Signal Lost, DK mode, FM prescale at 0 ±15 ±50 ±115 kHz FM200k ±200 ±320 FM350k ±350 ±560 FM500k ±500 ±700 DFSIF FM SIF Carrier Accuracy for FM Standard (FM50k) ±1 ±5 kHz Shifted Standard (FM50k with DCO compensation) ±120 kHz R FM/QPSK Carrier Ratio FM/QPSK for NICAM System NICAM mute, FAR_MODE is active, standard BG, 100mVPP level for FM carrier 40 dB AM Carrier VSIFAM SIF Input Sensitivity Unmodulated, -3 dB at output amplitude AGC_ERR at 21d Standard L, 54% AM Depth, 1k H z 19 mV PP VMAX_SIFAM SIF Maximum Input Level Unmodulated, THD at 1%, 54% AM Depth, AGC_ERR at 0 1.3 VPP DEVAM Modulation Depth for AM THD at 1% 0 100 %

13.6 SIF to I²S Output Path Characteristics

Test Conditions: SIF amplitude = 100mVpp, otherwise specified, I²S output.

13.7 SCART to SCART Anal og Path Characteristics

Test Conditions: RloadMAX = 10kΩ, CloadMAX = 330pF , MONO_IN voltage = 0.5 VRMS DFSIFAM SIF Carrier Accuracy for AM ±1 ±5 kHz RAM/QPSK AM/QPSK Carrier Ratio for NICAM System NICAM Mute, 100mVPP AM carrier 36 dB AGC AGCstep IF AGC Step 1.4 1.5 1.6 dB AGCdyn Relative maximum gain to step 0 Valid from step 21 to step 31 29 30 31 dB Symbol Parameter Test Conditions Min. Typ. Max. Units FM Demodulation BANDFM Frequency Response 20Hz - 15kHz ±0.7 dB SNRFM Signal to Noise RMS unweighted, 20Hz-15kHz, Standard B/G 27 kHz FM Deviation,1kHz 66 dB THDFM Total Harmonic Distortion 0.05 % SEPFM Stereo Channel Separation Standard B/G stereo A2, 27 kHz FM deviation, 1 kHz 48 dB NICAM Demodulation BANDNIC Frequency Response 20Hz - 15kHz ±0.2 dB SNRNIC Signal to Noise 200Hz - 60dBFS, trap filter 200 Hz RMS unweighted, 20Hz-15kHz, Standard B/G mono NICAM,1 kHz 74 dB THD NIC Total Harmonic Distortion 0.04 % AM Demodulation BANDAM Frequency Response 20 Hz - 15 kHz ±0.5 dB SNRAM Signal to Noise RMS unweighted 2 0Hz-15 kHz, Standard L, 54% AM Depth, 1 kHz AGC: 13d 60 dB THDAM Total Harmonic Distortion 0.4 % Symbol Parameter Test Cond itions Min. Typ. Max. Units Analog-to-Analog STEREO and MONO RINSCART SCART Input Resistance 29 34 39 k Ω ROUTSCART Output Resistance for SCARTs 40 75 Ω VDCINSCART SCART Input DC Level 1.57 V VDCOUTSCART SCART Output DC Level 3.64 V Symbol Parameter Test Condi tions Min. Typ. Max. Units

STV82x7 Electrical Characteristics

13.8 SCART and MONO IN to I²S Path Characteristics

Test Conditions: Sampling Frequency = 32KHz, Maximum MONO_IN voltage = 0.5 VRMS.

13.9 I2S to LS/HP/SUB/C Path Characteristics

Test Conditions: Sampling Frequency = 32KHz, LLOAD = 100 µH, CLOAD = 33nF , RLOAD = 30KΩ. CLIPSCART Clipping SCART Clipping input level from SCART input At 1 kHz 1% THD

2.0 VRMS

MONO_IN input 0.5 VRMS THDSCART THD SCART THD from SCART input 1 VRMS, at 1 KHz 0.02 0.05 % THD from MONO_IN input 0.25 VRMS, at 1 KHz 0.02 0.05 % SNRSCART Signal to Noise Ratio SCART input 1 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 82 dB MONO_IN input 0.25 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 76 dB BANDSCART Frequency Flatness SCART input 20 Hz to 20 kHz -0.5 0.5 dB MONO_IN input 20 Hz to 20 kHz 11.5 12 12.5 dB XTALKL/R Left/Right Crosstalk 1V RMS @ 1 kHz on ref signal, the other one grounded 80 90 dB XTALKIN Audio Crosstalk from Input Channel n to Input Channel m 1V RMS @ 1 kHz on ref signal, all other inputs grounded 80 90 dB XTALKOUT Audio Crosstalk from Output Channel n to Output Channel m 1V RMS @ 1 kHz on reference output, signal on a single input, all other inputs grounded 80 90 dB Symbol Parameter Test Conditions Min. Typ. Max. Units THDADC THD ADC THD from SCART input VIN = 2 VRMS at 1 KHz 0.006 0.05 % THD from MONO_IN input VIN = 0.5 VRMS at 1 KHz 0.006 0.05 % SNRADC Signal to Noise Ratio 20 to 15 kHz Bandwidth, RMS unweighted VIN = 200 mVRMS SCART input 62 dB BANDADC Frequency Flatness 20 Hz to 15 kHz ±0.5 dB XTALKADC Left Right Crosstalk at 1 KHz, VIN = 1 VRMS 95 dB Symbol Parameter Test Conditions Min. Typ. Max. Units ROUTDAC Output Resistance for Main Outputs LS_L, LS_R, LS_SUB, LS_C, HP_LSS_R and HP_LSS_L pins 90 140 Ω VDCOUTDAC MAIN Output DC Level 1.54 V Symbol Parameter Test Cond itions Min. Typ. Max. Units

13.10 I²S to SCART Path Characteristics

Test Conditions: Sampling Frequency = 32KHz, CLOAD = 33nF on DAC SCART pins, DAC SCART prescale at -5.5dB.

13.11 MUTE Characteristics

13.12 Digital I/Os Characteristics

THDDAC Total Harmonic Distortion 90% Full-scale Range at 1 kHz 0.06 % SNRDAC Signal to Noise Ratio 20 to 15 kHz Bandwidth, RMS unweighted, at -20dB full range 75 dB VOUTAMPDAC MAIN Output Amplitude 100% Full-scale Range at 1 kHz 900 mVRMS XTALKDAC Left Right Crosstalk at 1 KHz, -20dBFS 87 dB Symbol Parameter Test Conditions Min. Typ. Max. Units THDDACSCART Total Harmonic Distortion 90% Full-scale Range at 1 kHz 0.08 0.12 % SNRDACSCART Signal to Noise Ratio 20 Hz to 15 kHz Bandwidth unweighted, -20dB Full Range 73 dB VODACSCART MAIN Output Amplitude 100% Full-scale Range at 1 kHz 2 VRMS XTALKDACSCART Left Right Crosstalk at 1 KHz, -20 dBFS 80 dB Symbol Parameter Test Conditions Min. Typ. Max. Units MUTEDAC DAC Mute analog I2S to DAC at 1 kHz 90 dB MUTESCART SCART Mute 2V RMS @ 1 kHz on ref signal, all other inputs grounded 81 dB Symbol Parameter Test Conditions Min. Typ. Max. Units VIL Low Level Input Voltage except SDA, SCL and CLK_SEL, 3.3V power supply 0.5 V VIH High Level Input Voltage except SDA, SCL and CLK_SEL, 3.3V power supply 2.0 V IIN Input Current 1 µA VILCLK_SEL CLK_SEL Low Level Input Voltage 1.8V power supply 0.3 V VIHCLK_SEL CLK_SEL High Level Input Voltage 1.8V power supply 1.2 V VOL Low Level Output Voltage S/PDIF_OUT, IRQ, BUS_EXP 0.3 V VOH High Level Output Voltage S/PDIF_OUT, IRQ, BUS_EXP 3.0 V Symbol Parameter Test Conditions Min. Typ. Max. Units

STV82x7 Electrical Characteristics

13.13 I²C Bus Characteristics

Symbol Parameter Test Conditions Min. Typ Max. Unit SCL VIL Low Level Input Voltage -0.3 1.5 V VIH High Level Input Voltage 2.3 5.5 V IIL Input Leakage Current VIN = 0 to 5.0 V -10 10 µA fSCL Clock Frequency 400 kHz tR Input Rise Time 1 V to 2 V 300 ns tF Input Fall Time 2 V to 1 V 300 ns CI Input Capacitance 10 pF SDA VIL Low Level Input Voltage -0.3 1.5 V VIH High Level Input Voltage 2.3 5.5 V IIL Input Leakage Current VIN = 0 to 5.0 V -10 10 µA tR Input Rise Time 1 V to 2 V 300 ns tF Input Fall Time 2 V to 1 V 300 ns VOL Low Level Output Voltage IOL = 3 mA 0.4 V tF Output Fall Time 2 V to 1 V 250 ns CL Load Capacitance 400 pF CI Input Capacitance 10 pF I²C Timing tLOW Clock Low period 1.3 µs tHIGH Clock High period 0.6 µs tSU,DAT Data Set-up Time 100 ns tHD,DAT Data Hold Time 0 900 ns tSU,STO Set-up Time from Clock High to Stop 0.6 µs tBUF Start Set-up Time following a Stop 1.3 µs tHD,STA Start Hold Time 0.6 µs tSU,STA Start Set-up Time following Clock Low to High Transition 0.6 µs

13.14 I 2S Bus Interface

See timing for I2s on page 41. Figure 28: I²C Bus Timing Symbol Parameter Test Conditions Min. Typ Max. Unit I²S Input VI2S_IL Input I2S Low Level Voltage 0.8 V VI2S_IH Input I2S High Level Voltage 2V ZI2S Input I2S Impedance 5p F II2S_Leak I2S Leakage Current -1 1 µA tI2S_Su I2S Input Setup Time before Rising Edge of Clock See Figure 29 30 ns tI2S_Ho I2S Input Hold Time after Rising Edge of Clock See Figure 29 100 ns fI2S_LR0 I2S Left Right Strobe Input Frequency (I2S_DATA0 only) deviation =+-250ppm 8 48 KHz fI2S_SCL0 I2S Serial Clock Input Frequency (I2S_DATA0 only) 0.512 3.072 MHz fI2S_LR I2S Left Right Strobe Input Frequency (I2S_DATA0,1 ,2) deviation =+-250ppm 32 48 KHz fI2S_SCL I2S Serial Clock Input Frequency (I2S_DATA0 ,1,2) 2.048 3.072 MHz RI2S_SCL I2S Serial Clock Input Ratio 0.9 1.1 I2S Output (I2S_DATA0 only) VI2SOL Output I2S Low Level Voltage IOL = 2 mA 0.4 V VI2SOH Output I2S High Level voltage IOH = 2 mA 2.4 V fI2S_OLR I2S Left Right Strobe Output Frequency deviation =+-250ppm 8 48 KHz tBUF tLOW tHIGHtHD,STA tR tF tSU,STA tHD,DAT tSU,DAT tSU,STO SDA SCL SDA

STV82x7 Electrical Characteristics fI2S_OSCl I2S Serial Clock Output Frequency 0.512 3.072 MHz RI2S_SCL I2S Serial Clock Output Ratio 0.9 1.1 tI2S_Del I2S Output Delay After Falling Edge of Clock See Figure 29, Cl=30pF 30 ns Figure 29: I²S Input Bus Timing Symbol Parameter Test Conditions Min. Typ Max. Unit I2S_SCLK I2S_DATA tI2S_Su tI2S_Ho tI2S_Su I2S_LR_CLK

Input/Output Groups STV82x7

14 Input/Output Groups

Pin numbers apply to SDIP package only. VCC18_IF 50K GND_PSUB SIF_P73 50K 50K VCC18_IF VCC_H GND_PSUB SC1_OUTL 1 SC1_OUTR SC2_OUTL SC2_OUTR SC3_OUTL SC3_OUTR VCC33_LS GND_PSUB LS_C LS_L LS_R SCR_FLT LS_SUB 25LS_L HP_LSS_L HP_LSS_R 150 VCC33_LS GND 33_LS 78MONO_IN 30K VREFA VCC18_IF GNDIF 74SIF_N VCC18_IF REF VCC_H GND_PSUB 9SC1_IN_L 22K5 7K5 VREFA SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R

STV82x7 Input/Output Groups VCC33_LS 5K4 GND33_LS 16K8 11VREFA VB G (1.2V) VCC33_LS GND33_LS 13VB G 10K BAND-GAP=1.2V VSS 35HP_DET ADR_SEL RST_N VDD33_I01 CLK_TST_CTRL 48 VSS 45S/PDIF_OUT VDD33_I01VDD33_I01 VSS BUS_EXD VDD33_I02VDD33_I02 IRQ VSS 44S/PDIF_IN VDD33_I01

Input/Output Groups STV82x7 VSS 60I2S_PCM_CLK I2S_LR_CLK I2S_DATA0 VDD33_I02 I2S_DATA1 63 64I2S_DATA2 VSS 51CLK_SEL VDD18 VSS 35SCL 40SDA 53XTALOUT_CLKXTM 52XTALIN_CLKXTP VCC18_CLK1 500K GND18_CLK1 VCC18_CLK1 GND18_CLK1

STV82x7 Input/Output Groups VDD33_I02 VCC18_CLK1 VDD33_I01 GND_PSUB GND18_CLK2 GND18_CLK1 VSS 57VCC18_CLK2 VDD18 38

Input/Output Groups STV82x7 VDD18_CONV 34 VDD33_CONV 22 VCC_NISO 20 VCC33_LS 16 VCC33_SC 7 VCC_H 3 VDD18_ADC 71 VCC18_IF 76 GND18_IF 77 GNDPW_IF 75 VSS18_ADC 72 GND_PSUB 70 GND33_LS 17 GND_H 4 GND33_SC 8 GND_SA 12 VSS18_CONV 33

STV82x7 Package Mechanical Data Figure 30: 80-Pin Thin Plastic Quad Flat Package Table 31: Package Mechanical Dimensions Dim. mm inches A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 E 16.00 0.630 E1 14.00 0.551 e 0.65 0.026 L1 1.00 0.039 A b e h c L EE1 D

Revision Date Modification 1.96 April 2004 Preliminary Datasheet - First Issue. 1.97 April 2004 Updates to Chapter 13: Electrical Characteristics on page 132.

1.98 April 2004

Added Figure 8: STV82x6/STV82x7 Compatible Application Electrical Diagram on page 18. Added Section 11.2: Start-up and Configuration Change Procedure on page 47. Update of Table 21: Demod Matrix on page 94. Changes to function descriptions in Section 12.18: Volume on page 116. Other minor corrections.

1.99 June 2004

Updates to Table 3: TQFP80 Pin Description on page 14, Section 13.5: Analog Sound IF Signal on page 133, Section 13.9: I2S to LS/HP/SUB/C Path Characteristics on page 135, Section 13.10: I²S to SCART Path Characteristics on page 136 and Section 13.12: Digital I/Os Characteristics on page 136.

2.0 June 2004

Updates to Table 7: RESET Default Values on page 45, Table 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs on page 27, Table 19: Volume Control on page 36, Table 27: Flow chart on page 47 and Section 12.1: I²C Register Map on page 49. Added Register : SPDIF_CHANNEL_STATUS. Other minor corrctions and modifications.

2.01 July 2004

Added logos to page 1. Added notes to Figure 3, Figure 4 and Figure 5. Removed “Pro Logic OFF Switch” from Table 12, Table 13, Table 14 and Table 16. Other minor modifications and cosmetic changes.

2.02 July 2004

Added ST Voice logo to page 1. Modification to ST OmniSurround version in Table 1. Modifications to text in Section 4.1: Back-end Processing on page 24. Other minor modifications and cosmetic changes. 2.03 January 2005 Update of bits I2S_OUT_SEL ECT[1:0] of ADC_CTRL register (56h).

3 February 2005

Modified STSRND-STEREO on page 52 (removed shading), ADC-CTRL register I2S0_DATA0_CTRL field modification on page 74 and OFF added in PL2_C_WIDTH and PL2_DIMENSION on page 102.

A Audio Matrix Automatic Standard Recognition System .... 22, 49 B C D Dolby E Equalizer I L Loudness Control P R Registers

S SIF Signal Signal Processor SRS SRS‚ T V

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