STV8130AD

STV8130AD STMICROELECTRONICS | Alldatasheet

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ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. September 2003 1/12

FEATURES

■ Input Voltage Range: 5 V to 18 V ■ Output Currents up to 750 mA ■ Fixed Precision Output 1 Voltage: 3.3 V ±2% ■ Adjustable Output 2 Voltage: 2.8 to 16 V ■ Output 1 with Reset Function ■ Output 2 with Disable Function by TTL Input ■ Short-circuit Protection at both Outputs ■ Thermal Protection ■ Low Dropout Voltage

DESCRIPTION

The STV8130A # and STV8130D# are monolithic dual positive voltage regulators designed to provide a fixed precision output voltage of 3.3 V and an adjustable voltage between 2.8 and 16 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Output 2 can be disabled via the TTL input. Short-circuit and thermal protections are included. SIP9 (Plastic Package) ORDER CODE: STV8130A# DIP16 (8 + 8) ORDER CODE: STV8130D# OUTPUT1 OUTPUT2 PROGRAM RESET GROUND DISABLE DELAY CAPACITOR INPUT2 INPUT1 T ab is connected to GROUND INPUT1 INPUT2 DELAY CAPACITOR DISABLE RESET PROGRAM OUTPUT2 OUTPUT1 GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND

STV8130AD GENERAL INFORMATION

1 GENERAL INFORMATION

Figure 1: STV8130A# Block Diagram Figure 2: STV8130D# Block Diagram

1 Regulator 1

ELECTRICAL CHARACTERISTICS STV8130AD

2 ELECTRICAL CHARACTERISTICS

2.1 Absolute Maximum Ratings

2.2 Thermal Data

2.3 Electrical Characteristics

TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified. Symbol Parameter Value Unit VIN DC Input Voltage at pins INPUT1 and INPUT2 20 V VDIS Disable Input Voltage at pin DISABLE 20 V VRST Output Voltage at pin RESET 20 V IOUT1,2 Output Currents Internally Limited Pt Power Dissipation Internally Limited TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 0 to +150 °C Symbol Parameter Value Unit R thJC Thermal Resistance (Junction-to-Case) STV8130A # STV8130D # 15 °C/W R thJA Thermal Resistance 1 (Junction-to-Ambient) 1. Mounted on board. For more information, refer to Section 5. STV8130A # STV8130D # 56 °C/W TJ Maximum Recommended Junction Temperature 140 °C TOPER Operating Free Air T emperature Range 0 to +70 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VOUT1 Output Voltage I OUT1 = 10 mA 3.23 3.30 3.37 V VOUT2 Output Voltage IOUT2 = 10 mA 2.8 16.0 V VIO1,2 Dropout Voltage IOUT1,2 = 750 mA 1.4 V VO1,2LI Line Regulation 6V < VIN1 < 12 V

12 V < VIN2 < 18 V

IOUT1,2 = 200 mA 100 mV VO1,2LO Load Regulation 5m A < IOUT1 < 600 mA 5m A < IOUT2 < 600 mA 100 200 mV

STV8130AD ELECTRICAL CHARACTERISTICS IQ Quiescent Current IOUT1 = 10 mA, OUTPUT2 Disabled 2m A VO1RST Reset Threshold Voltage1 K = VOUT1 , IOUT1 ≥ 50 mA K - 0.4 K - 0.25 K - 0.1 V VRTH Reset Threshold Hysteresis See circuit description. 20 50 75 mV tRD Reset Pulse Delay C e = 100 nF See circuit description. 25 ms VRL Saturation Voltage in Reset ConditionIRESET = 5 mA 0.4 V IRH Leakage Current in Normal ConditionVRESET = 10 V 10 µA KOUT1, 2 Output Voltage Thermal Drift TJ = 0 to + 125°C 100 ppm/°C IOUT1,2SC Short Circuit Output Current VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V2 1.6 1.0 A VDISH Disable Voltage when pin DISABLE is High (OUTPUT2 active) 2 V VDISL Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled) 0.8 V IDIS Disable Bias Current 0V < VDIS < 7 V -100 2 µA VREF Reference Voltage at PROGRAM Pin 2.44 V TJSD Junction T emperature for Thermal Shutdown 145 °C 1. This reset signal is activated by a decrease of VOUT1 voltage which can be due to an overload of pin OUT1 or by a lack of Input Voltage (VIN1). 2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V. Symbol Parameter Test Conditions Min. Typ. Max. Unit K 0 Δ V 0 106⋅

CIRCUIT DESCRIPTION STV8130AD

3 CIRCUIT DESCRIPTION

The STV8130A # and STV8130D# are dual-voltage regulators with Reset and Disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (V IN1), the second regulator will not work if pin INPUT1 is not supplied. The adjustable voltage of pin OUTPUT2 (VOUT2 ) is defined by output bridge resistors (R1, R2): the values of these resistors are calculated to obtain, with the targetted value for VOUT2 , the reference voltage (VREF = 2.44 V) on the median point connected to pin PROGRAM. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE . The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1 - 0.25 V (3.05 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. This drop can be caused by a parasitic loading condition on pin OUTPUT1 or by a too low value of VIN (short powering off). When the voltage at pin OUTPUT1 exceeds V OUT1 - 0.2 V (3.1 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.44 V) corresponding to a Reset Pulse Delay (tRD ) as shown in Figure 4. Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.84 V). Figure 3: Reset Diagram Figure 4: Internal Reset Voltages tRD C e 2.44V× OUTPUT1 REG VREF a Ce VREF 0.6V b RESET 10 µA VREF = 2.44 V RESET K VRTH VO1RST tRDtRD VOUT1 Power On Power Off K = Actual Value of VOUT1

STV8130AD APPLICATION DIAGRAMS

4 APPLICATION DIAGRAMS

Figure 5: STV8130A# Typical Application Figure 6: STV8130D# Typical Application RESET V IN2 V OUT1V IN1 V OUT2 Ce 0.1 µF C1 C2 C3 DISABLE C1 to C4 = 10 µF STV8130A # V O2 V REF R 1 R 2+ R 1 DELAY OUTPUT1 OUTPUT2 PROGRAMGROUND INPUT1 INPUT2 CAPACITOR R1 Value (typ.) = 10 kΩ VREF = 2.44 V RESET DISABLE RESET V IN2 V OUT1V IN1 V OUT2 Ce 0.1 µF C1 C2 C3 DISABLE C1 to C4 = 10 µF STV8130D # V O2 V REF R 1 R 2+ R 1 DELAY OUTPUT1 OUTPUT2 PROGRAM INPUT1 INPUT2 CAPACITOR R1 Value (typ.) = 10 kΩ VREF = 2.44 V RESET DISABLE Pins 9 to 16 GROUND

POWER DISSIPATION AND LAYOUT INDICATIONS STV8130AD

5 POWER DISSIPATION AND LAYOUT INDICATIONS

The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VOUT1 ) x IOUT1 + (VIN2-VOUT2 ) x IOUT2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming:

• Maximum Ambient Temperature = 70° C
• Maximum Junction Temperature = 140° C Device Heat Sink R thJA in °C/W P MAX in W STV8130A # No 50 1.4 Yes 20 3.5 STV8130D # No 56 to 40 1.25 to 1.75 Yes 32 2.2 Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink Figure 8: Metal plate mounted near the STV8130D# for heat sinking Copper area (cm²) (35 µm plus solder) Board is face-down To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. RthJA °C/W 10 120 24 8 6 Test Board with “On Board” square heat sink area. Top View Bottom View

STV8130AD PACKAGE MECHANICAL DATA

6 PACKAGE MECHANICAL DATA

Figure 9: 9-Pin Plastic Single In Line Package Dim. mm Inches A 7.1 0.280 a1 2.7 3 0.106 0.118 B 24.8 0.976 b1 0.5 0.020 b3 0.85 1.6 0.033 0.063 C 3.3 0.130 c1 0.43 0.017 c2 1.32 0.052 D 21.2 0.835 d1 14.5 0.571 e2 . 5 4 0 . 1 0 0 e3 20.32 0.800 L 3.1 1.122 L1 3 0.116 L2 17.6 0.693 L3 0.25 0.010 M 3.2 0.126 N 1 0.039

PACKAGE MECHANICAL DATA STV8130AD Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width Dim. mm Inches A 5.33 0.210 A1 0.38 0.015 b 0.36 0.56 0.014 0.022 b2 1.52 1.78 0.060 0.070 e2 . 5 4 0 . 1 0 0

STV8130AD REVISION HISTORY

7 REVISION HISTORY

Revision Main Changes Date 1.8 General Update; DISABLE pin renamed DISABLE (function remains unchanged). August 2001 1.9 Thermal Data updated. September 2001 2.0 Addition of DIP16 package. September 2001 2.1 Thermal Data updated. Figure 1 and Figure 2 updated. October 2001 2.2 Order code changed from STV8130A and STV8130D to STV8130A# and STV8130D#. Update of V O1RST values in Chapter 2.3: Electrical Characteristics on page 4.

31 January 2002

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.