STV160NF02LA

STV160NF02LA STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 20V - 0.0018Ω - 160A PowerSO-10 STripFET™ POWER MOSFET (1) VDD = 35V, ID = 45A, RG = 22Ω , L = 330µH, Starting Tj=25°C (**)Limited only maximum junction temperature allowed by PowerSO-10 ■ TYPICAL R DS (on) = 0.0018 Ω ■ LOW THRESHOLD DRIVE ■ ULTRA LOW ON-RESISTANCE ■ ULTRA FAST SWITCHING ■ 100% AVALANCHE TESTED ■ VERY LOW GATE CHARGE ■ LOW PROFILE, VERY LOW PARASITIC INDUCTANCE PowerSO-10 PACKAGE

DESCRIPTION

The STV160NF02LA represents the second gen- eration of Application Specific STMicroelectronics well established STripFET™ process based on a very unique strip layout design. The resulting MOSFET shows unrivalled high packing density with ultra low on-resistance and superior switching charactestics. Process simplification also trans- lates into improved manufacturing reproducibility. This device is particularly suitable for high current, low voltage switching application where efficiency is crucial

APPLICATIONS

■ BUCK CONVERTERS IN HIGH PERFORMANCE TELECOM AND VRMs DC- DC CONVERTERS ABSOLUTE MAXIMUM RATINGS (● ) Pulse width limited by safe operating area Note: Marking will be STV160NF02AL TYPE V DSS R DS(on) ID STV160NF02LA 20 V < 0.0027 Ω 160 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 20 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 20 V VGS Gate- source Voltage ± 15 V ID (**) Drain Current (continuos) at TC = 25°C 160 A ID Drain Current (continuos) at TC = 100°C 113 A IDM (● ) Drain Current (pulsed) 640 A PTOT Total Dissipation at TC = 25°C 210 W Derating Factor 1.4 W/°C EAS (1) Single Pulse Avalanche Energy 330 mJ Tstg Storage Temperature –65 to 175 °C Tj Max. Operating Junction Temperature 175 °C PowerSO-10 INTERNAL SCHEMATIC DIAGRAM CONNECTION DIAGRAM (TOP VIEW)

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 0.71 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 50 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 20 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 10 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 15 V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 1V R DS(on) Static Drain-source On Resistance VGS = 10 V, ID = 80 A VGS = 10 V, ID = 45 A VGS = 8 V, ID = 80 A VGS = 5 V, ID = 40 A VGS = 10 V, ID =80 A;Tj = 175 °C VGS = 8 V, ID =80 A; Tj = 175 °C VGS = 5 V, ID =40 A; Tj = 125 °C 1.8 1.76 1.9 3.8 2.7 2.7 3.7 6.4 m Ω m Ω m Ω m Ω m Ω m Ω m Ω ID(on) On State Drain Current V DS > ID(on) x RDS(on)max, VGS =1 0 V 160 A Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 80A 210 S R g Gate resistance VDS = 0 V, f = 1 MHz, VGS = 0 1.1 Ω C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 15 V, f = 1 MHz, VGS = 0 5500 3210 750 pF pF pF C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 0 V, f = 1 MHz, VGS = 0 8400 14500 5800 pF pF pF LS Internal Source Inductance From the Lead End (6mm from Package Body) to the Die Center 3n H LD Internal Drain Inductance Not Available on Surface Mounting Package

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 15 V, ID = 80 A R G = 4.7Ω VGS = 10V (see test circuit, Figure 3) 30 ns tr Rise Time 650 ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 16 V, ID = 160 A, VGS = 10 V 130 175 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit t d(off) tf Turn-off-Delay Time Fall Time VDD = 15 V, ID = 80 A, R G =4 . 7Ω, VGS = 10 V (see test circuit, Figure 5) 105 200 ns ns td(off) tr(Voff) tf tc Turn-off Delay Time Off-voltage Rise Time Fall Time Cross-over Time Vclamp = 16 V, I D = 40 A R G =4 . 7Ω, VGS = 10V 125 180 ns ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit I SD Source-drain Current 160 A ISDM (1) Source-drain Current (pulsed) 640 A VSD (2) Forward On Voltage ISD = 160 A, VGS = 0 1.5 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 160A, di/dt = 100A/µs, VDD = 15V, Tj = 25°C (see test circuit, Figure 5) 225 ns nC A Safe Operating Area Thermal Impedance

Gate Charge vs Gate-source Voltage Capacitance Variations Tranfer Characteristics Static Drain-Source On Resistance

Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Basic Schematic For Motherboard VRM Whith Synchronous Rectification Basic Schematic Mosfets Switch Used In Secondary Side Of a Froward Convert Normalized Gate Thereshold Voltage vs Temp.

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 3.35 3.65 0.132 0.144 A1 0.00 0.10 0.000 0.004 B 0.40 0.60 0.016 0.024 C 0.35 0.55 0.013 0.022 D 9.40 9.60 0.370 0.378 D1 7.40 7.60 0.291 0.300 e 1.27 0.050 E 9.30 9.50 0.366 0.374 E1 7.20 7.40 0.283 0.291 E2 7.20 7.60 0.283 0.300 E3 6.10 6.35 0.240 0.250 E4 5.90 6.10 0.232 0.240 F 1.25 1.35 0.049 0.053 h 0.50 0.002 H 13.80 14.40 0.543 0.567 L 1.20 1.80 0.047 0.071 q 1.70 0.067 α 0 o 8o DETAIL "A" PLANE SEATING α L F h A D D1= = = = = = 0.10 A E1E3 C Q A = = B B DETAIL "A" SEATING PLANE = = = = 610 e B HE M0.25 = = = = 0068039-C PowerSO-10 MECHANICAL DATA

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