STV1601A STMICROELECTRONICS | Alldatasheet
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SERIAL INTERFACE TRANSMISSION ENCODER November 1992 27 26 25 24 23 22 21 20 19 123456789
37 V EE
V CC V EE D0Y D0X D1Y D1X D2Y D2X D3Y LST GND SX SY GND D9X D9Y D8X D8Y 1601A-01.EPS PIN CONNECTIONS PGA37 (Ceramic Package) ORDER CODE : STV1601A THIS IC CONTAINS ALL THE CIRCUITS NEEDED FOR CONVERSION FROM PARALLEL DATA, AND PARALLEL CLOCK, INTO SERIAL DATA. APPLICATIONS ARE STRAIGHTFORWARD AS ONLY A FEW EXTERNAL COMPONENTS ARE NEEDED. OTHER RELATED IC’s INCLUDE : .STV1602A, A SERIAL TRANSMISSION DE- CODER (WITH A BUILT-IN CABLE EQUAL- IZER AND PARALLEL-TO-SERIAL CONVERSION) .STV1389AQ COAXIAL CABLE DRIVER STRUCTURE .Hybrid IC
APPLICATIONS
SERIAL DATA TRANSMISSION ENCODER .100 to 270 Mb/s APPLICATIONS EXAMPLES .Serial data transmission of digital television signal 525-625 lines .4:2:2 component 270Mb/s (10-BIT) .4*FSC PAL composite 177Mb/s (10-BIT) .4*FSC NTSC composite 143Mb/s (10-BIT) FUNCTIONS .Parallel-to-serial conversion .Scrambler : Modulo - 2 division by .PLL for serial clock generation .PLL lock detection .Sync word required with the parallel data stream 8 bit 10 bit 1st word FFH 3FFH 2nd word 00H 000H 3rd word 00H 000H Sync word conversion(8-bit timing referencesignal is internally converted to 10-bit). CODE LIMITATION The word composing the Sync word listed above shall not appear during data words. This limitation includes 00 and FF in 8-bit use and 000 through 003 and 3FC through 3FF in 10-bit use.
DESCRIPTION
TheSTV1601Ais aHybrid IC encoderthat converts parallel data into serial data for a serial transmis- sion line.
N Symbol Equivalent circuit Description I/O Standard Min. Typ. Max. Unit
1 LST
PLL lock detection. Is High while PLL locked. If unlocked, becomes irregular. At free running (TN1 H) turns Low H L O -1.0 -4.0 V V
36 PCK
divided to 1/10 VCO output. Used to check VCO free running frequency H L O -0.8 -1.6 V V 3S X Differential Serial Output Input parallel data is converted to serial, then from scrambled NRZ to NRZI data H L O -1.6 -2.4 V V 4S Y 1601A-01.TBL V CCGND 2kΩ 4kΩ 2kΩ EEV 1601A-02.EPS GND EEV 600Ω 600Ω 240Ω 1601A-03.EPS GND VCCVCC EEV VR3 30Ω 100Ω 100Ω 30Ω 2kΩ 2kΩ115Ω 1601A-04.EPS STV1601A
PIN DESCRIPTION (continued) Pin N Symbol Equivalent circuit Description I/O Standard Min. Typ. Max. Unit
29 V CC
Parallel data and clock input buffers power supply. When this pin is connected to +5V, parallel data clock turns to TTL mode. When this pin is connected to GND, parallel data clock turns to ECL mode. D9X D9Y D8X D8Y D7X D7Y D6X D6Y D5X D5Y D4X D4Y D3X D3Y D2X D2Y D1X D1Y D0X D0Y Parallel input ports: LSB : D0X or Y MSB : D9X or Y Signal : DnX Return : DnY For ECL mode, V CC shalll be H L ForTTL mode, VCC shall be +5V H L -1.0 2.0 -1.6 0.8 V V V V
28 RSE
H : high range 140 to 270MHz L : low range 100 to 145MHz H L I -0.4 -4.0 V V 1601A-02.TBL EEV 2kΩ 1kΩ V R3 1601A-05.EPS GND EEV 70kΩ 2kΩ 10kΩ 10kΩ 1601A-06.EPS STV1601A
PIN DESCRIPTION (continued) Pin N Symbol Equivalent circuit Description I/O Standard Min. Typ. Max. Unit
30 PCX
Parallel clock (PCX) and its return (PCY) For ECL mode, V CC =0 H L For TTL mode, VCC = +5V H L I -1.0 2.0 -1.6 0.8 V V V V
31 PCY
2, 5,
32 GND GND
26 V EE
-5V power supply I/O buffer PLL -5.2 -5.0 -4.8 V
27 V EE
-5V power supply Logic part -5.2 -5.0 -4.8 V 33 FV VCO free running frequency adjustment : VEE level gives the lowest frequency. To adjust, set TN1 high. I -3.9 V
34 TRP
comparator output should be connected to a parallel clock frequency trap filter to minimize jitter O -3.2 V
35 TN1
Test mode : High : VCO free running condition (input disabled) Low : Normal mode (input enabled) I -1.0 -4.5 V V 1601A-03.TBL EEV 2kΩ V R3 VCC 2kΩ 2kΩ 1601A-07.EPS GND EEV 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 10kΩ 0.1µF VCC 0.022µF 2µF 220Ω 1601A-08.EPS VCC GND EEV VR3 20kΩ 12kΩ 4kΩ 1601A-09.EPS STV1601A
NRZ ⊗ NRZI 000hex DETECTOR PHASE DETECT OR 353031 33 34 28 36 PARALELL TO SERIAL CONVER TER X + X + 1 SCRAMBLER94 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2529 37 N.C. GND GND GND V EE V EE CCV PCY PCX TN1 FV TRP RSE PCK LST SX SY D9X D9Y D8X D8Y D7X D7Y D6X D6Y D5X D5Y D4X D4Y D3X D3Y D2X D2Y D1X D1Y D0X D0Y Parallel Clock Serial Clock Parallel Load 10-BIT X 3 WORD SHIFT REGISTER 1601A-10.EPS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VEE Supply Voltage -6 V VCC Supply Voltage +6 V VIN Input Voltage V EE to VCC V IOUT Output Current -30 mA Toper Operating Temperature 0 to 65 oC Tstg Storage Temperature -50 to 125 oC PD Allowable Power Dissipation 2.0 W 1601A-04.TBL RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VEE Supply Voltage -4.8 to -5.2 V VCC Supply Voltage * 4.8 to 5.2 V Toper Operating Temperature 0 to 65 oC * For TTL input. Voltages are given with respect to GND 1601A-05.TBL ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA =2 5oC unless otherwise speciied) Symbol Parameter Test Conditions Test Circuit Min. Typ. Max. Unit DC CHARACTERISTICS IEE Supply Current 1 Figure 2 140 mA ICC Supply Current 2 7 mA 1601A-06.TBL STV1601A
ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA =2 5oC unless otherwise speciied) Symbol Parameter Test Conditions Test Circuit Min. Typ. Max. Unit DC CHARACTERISTICS VIH Input Voltage VCC = GND PCX, PCY, DnX, DnY -1.0 V VIL -1.6 V VIH VCC = +5V PCX, PCY, DnX, DnY 2.0 V VIL 0.8 V IIH Input Current PCX, PCY, DnX, DnY Figure 3 5 µA IIL -1 +1 µA VIH Input Voltage RSE Figure 7 -0.4 V VIL -4.0 V VIH TN1 Figure 6 -1 V VIL -4.5 V VOH Output Voltage PCK R P =1 kΩ -0.8 V VOL -1.6 V VOH LST IOH = -10µA, IOL = +10µA Figure 5 -1.0 V VOL -4.0 V VOH SX, SY R P = 220Ω -1.6 V VOL -2.4 V AC CHARACTERISTICS fMAX1 VCO Max. Oscillation Frequency 1RSE = ”H” Figure 4 30.0 MHz fMIN1 VCO Min. Oscillation Frequency 1 14.0 MHz fMAX2 VCO Max. Oscillation Frequency 2RSE = ”L” 15.0 MHz fMIN2 VCO Min. Oscillation Frequency 2 10.0 MHz fHP1 PLL Pull in Range f signal = 270MHz RSE = ”H” Figure 1 27.7 MHz fLP1 25.5 MHz fHP2 f signal = 177MHz RSE = ”H”
18.8 MHz
fLP2 16.5 MHz fHP3 f signal = 143MHz RSE = ”H”
15.0 MHz
fLP3 13.0 MHz fOP1 PLL Generator Frequency RSE = ”H” 14.0 27.0 MHz fOP2 RSE = ”L” 10.0 14.5 MHz tjit Jitter f signal = 270MHz RSE = ”H” Figure 8 ±0.25 nsec Tested through PCK : 1/10 of serial clock. 1601A-07.TBL SWITCHING CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA =2 5oC unless otherwise speciied) Symbol Parameter Test Conditions Test Circuit Min. Typ. Max. Unit tr Rise Time PCK R P =1 kΩ Figure 10 0.8 nsec tf Fall Time 1.4 nsec tr Rise Time SX, SY R P = 220Ω 0.7 nsec tf Fall Time 0.7 nsec 1601A-08.TBL TIMING RELATION OF INPUT CLOCK AND DATA Symbol Parameter Test Conditions Test Circuit Min. Typ. Max. Unit tw Pulse Width PCX, PCY Figure11 -5 + tc/2 t c/2 +5 + tc/2 nsec td Delay Time PCX - Dn -5 +5 nsec 1601A-09.TBL STV1601A
25 D0Y
0.1 10/16V 0.1 10/16V 33 28 N.C. -5V -5V -5V SW1 SW2 AB 10µF/10V 22kΩ A B HIGH RANGE LOW RANGE VCO RANGE SELECT ON : AF FREQUENCY ADJUST 150pF 0.22 µH 34TRP TN1 -5V 36PCK 1kΩ FREQUENCY MONITOR 1LST 220Ω 220 Ω -5V 0.1 220Ω SX SY D.U.T. STV1601A 0.1 VCO FREQUENCY ADJUST 10kΩ V R1 0.1 220Ω -5V 220Ω 0.1 0.1 0.1 -5V 0.1 0.1 220 Ω 150Ω 150Ω 75Ω 75 Ω SERIAL OUT V R VCC EE V -5V INPUT LEVEL TTL ECL +1.4V -1.3V +5V GND STV1389AQ PLL LOCK DETECTOR DIX DIY 220Ω 0.1 -5V 220 Ω 220Ω AIY AIX QFS 73Ω 41pF 41pF MON31 100Ω A B SERIAL IN CX29 ADS32 SW2-5V 10kΩ SY SX4 GND V EE 0.1 0.1 10/16V 24 27 30 23 8 7 -5V A B INPUT SELECT CABLE INPUT DIGITAL INPUT STV1602A -5V VCO FREQUENCY ADJUST 10kΩ FV V R2 ESO ESIRSE 22 1 37 DPR -5V 0.1 20SYN EVR PCK -5V 0.1 1kΩ x4 TRS DETECTOR SIGNAL FREQENCY MONITOR 1kΩ x8 22kΩ TN1 100kΩ QSW
5 SW310µF
-5V 0.1 LED 330Ω ON : AF FREQUENCYADJUST HP8182A SIGNAL ANALYZER FV RSE 10µF 1601A-11.EPS Figure 1 :Test Circuit Diagram Example STV1601A
10kΩ -5V 10/16V 0.1 STV1601A -5V PCX PCY V 1 1LST V TN131 -0.8V -1.6V 1601A-16.EPS Figure 6 2 5 32 29 27 26 3533 PCX SX SY FV TN1 GND V CC EE V VR1 10kΩ 22kΩ 10µF -5V -5V -5V 0.1µF 220Ω 220Ω 1kΩ 10/16V 0.1 STV1601A -5V SW2 FREQUENCY MONITOR 1601A-17.EPS Figure 7 2 5 32 29 27 26 3533 PCX SX SY FV TN1 GND V CC EE V VR1 10kΩ 22kΩ 10µF -5V -5V -5V 0.1µF 1kΩ 10/16V 0.1 STV1601A -5V SW2 FREQUENCY MONITOR RSE -5V 220Ω 220Ω 220Ω 0.1 -5V 0.1µF 150Ω150Ω 0.1 0.1 75 Ω 75Ω STV1389AQ Parallel clock data TRIGGER SIGNAL SERIAL OUT SIGNAL 270Mb/s jitter = 1/2 t 1601A-18.EPS Figure 8 STV1601A
- PLL block PARALLELCLOCK INPUT CONTROL PLL, PLL lock detection and the various blocks of the serial output control are shown in Figure 13. When TN1 is connected to GND (set High), the parallel clock input is disabled. The VCO turns to free running conditions and its frequency can be adjusted through FV. This frequency decreases when the resistor value between FV and V EE is reduced. Oscillation fre- quency monotoring is performed through PCK which delivers a frequency divided by ten. When PLL is locked, PLL and PCX input signal phases are nearly matched. The RC network con- nected to TN1, temporarily, disables the parallel clock in order to avoid mislocking problems. VCO oscillation frequency range selection is avail- able through RSE ; High : from 140 to 270MHz ; Low : from 100 to 145MHz. TRP (Pin 34) is the phase comparator output. To minimize jitter, a trap circuit, consisting in a serial tuned circuit at parallel clock frequency can be used. PLL LOCK DETECTION The LSTsignal is generatedby latching the incom- ing parallel clock by the internal one (which is 1/10 of the VCO frequency).LST is used as a PLL lock detection signal and also controls the serial output. If the parallel clock input is disabled (by means of TN1), LST turns Low and the serial output is dis- abled as described in the previous section (SX (Pin 3) = High, SY (Pin 4) = Low). If the serial output has to be disabled while no parallel clock input is provided, PCX must be set Low and PCY must be set High. 4. Sync word To convert serial data back to parallel, insertion of some timing reference data indicating the parallel data word boundary in the serial data is needed. This, called TRS (Timing Reference Signal) in the digital interface format, consists of the three con- secutive words 3FFH, 000H, 000H. Conversion to 10-bit TRS from 8-bit (TRS) 8-bit parallel data 8-bit paralleldata can be converted into 10-bit data by using the 8th bit as the MSB and by setting the 2 LSBs at logical states as shown in Figure 14. LST SX SY Serial Clock PCY PCX TN1 FV TRP RSE PCK PHASE COMPARATOR VCO 1/10 DIVIDER NRZ To NRZI CONVERSION SCRAMBLER Q DQ D ”0” 1601A-23.EPS Figure 13 :PLL and Serial Output Control Block STV1601A
N.C. PCK TN1 TRP FV GND PCY PCX -5V -5V 22kΩ 1kΩ 10µF/16V C1 L1 Q110kΩ 4.7kΩ 2.2kΩ 51Ω 51Ω 0.1 0.1 -5V 28RSE VCC VEEV EE 26 27 HIGH LOWD0YD0XD1YD1XD2YD2XD3Y 25242322212019 D7X D7Y D6X D6Y D5X D5Y D4X D4Y D3X 123456789 D8Y D8X D9Y D9X GND SY SX GND LST Parallel Data IN (ECL Balanced Pair) PAL Unit 151 210 0.2 300 0.4 0.3 Recommended values -5V 0.1µF 220Ω 220Ω 220Ω 0.1µF 0.1µF -5V -5V 150Ω 150Ω 220Ω 220Ω 0.1µF 0.1µF 1kΩ 68Ω 68Ω Parallel Clock In Test Jumper Parallel Clock Test Ponit (Return) (Rate select) -5V ((115mA typical) NTSC µH For signal Processig For coaxial cable processing nF STV1601A (ENCODERMODULE) STV1389AQ D2 NTSC D1, D2 PAL 10kΩ 1601A-31.EPS Figure 21 :Application Circuit Example STV1601A
25.4 0.5 0.46 0.051.2 0.1 25.4 0.5 3.8 1.15 0.15 4.2 Seating plane 0.22.54 x 9 = 22.86 0.25 Pin 28Pin 19 Pin 36 Pin 10 Pin 1 Pin 37 2.54 2.542.032 max. 2.54 x 9 = 22.86 0.25 Dimensions in mm PM-PGA37.EPS PACKAGE MECHANICAL DATA
37 PINS - CERAMIC PGA
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