STV0299B

STV0299B STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. STV0299B QPSK/BPSK LINK IC I MULTISTANDARD QPSK AND BPSK DEMODULATION I EASY IMPLEMENTATION WITH LOW COST DIRECT CONVERSION TUNERS I EXTREMELY LOW BER WHEN CO-CHANNEL INTERFERENCE I WIDE CARRIER LOOP TRACKING RANGE TO COMPENSATE FOR DISH FREQUENCY DRIFT I COMMON INTERFACE COMPLIANT I VERY LOW POWER CONSUMPTION I INTEGRATED DUAL 6-BIT ANALOG TO DIGIT AL CONVERTERS I DUAL DIGITAL AGC I DIGIT AL NYQUIST ROOT FILTER WITH ROLL-OFF OF 0.35 OR 0.20 I DIGITAL CARRIER LOOP WITH LOCK DETECTOR, ON-CHIP WIDE RANGE DEROTATOR AND TRACKING LOOP (TYP ± 45 MHz) I DIGITAL TIMING RECOVERY WITH LOCK DETECTOR I CHANNEL BIT RATE UP TO 90 Mbps AND SYMBOL FREQUENCY RATE FROM

1 TO 50 MSYMBOLS

I INNER DECODER: - VITERBI SOFT DECODER FOR CONVOLUTIONAL CODES, M=7, RATE 1/2 - PUNCTURED CODES 1/2, 2/3, 3/4, 5/6, 6/7 AND 7/8 I SYNCHROWORD EXTRACTION I CONVOLUTIVE DEINTERLEAVER I OUTER DECODER: - REED-SOLOMON DECODER FOR

16 PARITY BYTES; CORRECTION OF UP

• ENERGY DISPERSAL DESCRAMBLER I ON-CHIP FLEXIBLE CLOCK SYSTEMS TO ALLOW USE OF EXTERNAL CLOCK SIGNALS IN 4 MHz TO 30 MHz RANGE I EASY-TO-USE C/N ESTIMATOR WITH 2 TO 18 dB RANGE I I2C SERIAL BUS AND REPEATER I DVB COMMON INTERFACE COMPLIANT PARALLEL OUTPUT FORMAT I PARALLEL AND SERIAL DATA OUTPUT I LNB SUPPL Y CONTROL WITH STANDARD I/O,

22 KHz TONE AND DISEQC TM MODULATOR

I CMOS TECHNOLOGY: 2.5 V OPERATION; JEDEC (EIA/JESD8-5)

APPLICATIONS

I DIGITAL SATELLITE RECEIVER AND SET -TOP BOXES

DESCRIPTION

The STV0299 Satellite Receiver with FEC is a CMOS single-chip multistandard demodulator for digital satellite broadcasting. It consists of two A/D converters for I-input and Q-input, a multistandard QPSK and BPSK demodulator, and a forward error correction (FEC) unit having both an inner (Viterbi) and outer (Reed-Solomon) decoder. The FEC unit is compliant with the DVB-S and DSS TM specifications. Processing is fully digital. It integrates a derotator before the Nyquist root filter, allowing a wide range of offset tracking. The high sampling rate facilitates the implementation of low-cost, direct conversion tuners. A variety of configurations and behaviours can be selected through a bank of control/configuration registers via an I2C. The chip outputs MPEG Transport Streams and interfaces seamlessly to the Packet Demultiplexers embedded in ST’s ST20-TPx or STi55xx. High sampling frequency (up to 90MHz) considerably reduces the cost of LPF of direct conversion tuners. The multistandard capability associated with a broad range of input frequency operations makes it easy-to-use. Its low power consumption, small package and optional serial output interface makes it perfect for embedding into a tuner. TQFP64 (10 x 10 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV0299B (No Slug)

PageTABLE OF CONTENTS (continued)

1 PIN INFORMATION

1.1 Pin Connections

Figure 1: Pinout for 64-pin TQFP (10x10 mm) VDD QN QP VDDA VTOP VSSA DIRCLK-DIS SCLT VSS SDAT IP IN VSSA VSSA TEST VSS VDD D/P VSS CLK_OUT VDD_3.3 V SERIAL DATA/D7 OP1 LOCK/OP2 ERROR OP0 F22/DiSEqC SCL VDD CLK_IN/XTAL_IN XTAL_OUT VDDA RESET STDBY TEST VDDA TEST TEST VBOT1 64 62 61 60 59 58 57 56 5563 54 53 52 51 50 49 17 19 20 21 22 23 24 25 2618 27 28 29 30 31 32 VSS VSSA VSS VSS SDA VDD_3.3 V TEST TEST VDD DAC VSS IP0 STR_OUT TEST VDD VSS AUX_CLK AGC

1 PIN INFORMATION (continued)

1.2 Pinout Description

Note: 1 The following abbreviations are used: I - Input; O - Output; OD - Open drain output. 2 3.3 V output levels. 3 5 V tolerant Pin Number Name I/O1 Description SIGNAL INPUTS 50, 51 IP , IN I Analog in Phase Component 53, 54 QN, QP I Analog in Quadrature Component FRONT END CONTROLS

1 CLK_IN/XT AL IN I Crystal Input or CLK_IN

2 XT AL OUT O Crystal Output

9A G C OD 3 Control Signal to the Tuner

5 AUX_CLK O 2 Programmable Output Port or Programmable Output Clock

17-18 OP0, OP1 O 2 Programmable Output Ports

19 LOCK/OP2 O 2 Carrier Found or Data Found or Output Port

38 IP0 I Input Port

26-28-29-31, 33 to 36 D[7:0] O 2 Output Data; D7 is DATA_OUT in Serial Mode

24 CLK_OUT O 2 Output Byte Clock; or Bit Clock in Serial Mode

22 STR_OUT O 2 Output 1st byte Signal (synchro byte clock)

21 D/P O 2 Data/Parity Signal

20 ERROR O 2 Output Error Signal. Set in case of uncorrectible packet. I2C INTERFACE

14 SCL I3 Serial Clock (I2C bus)

12 SDA I/OD3 Serial Data (I2C bus)

59 SCLT OD 3 Tuner Serial Clock (repeator) or Output Port

60 SDAT I/OD3 Tuner Serial Data (repeator) or Input/Output Port

37-43-44-45-46-61-62 TEST I Reserved for manufacturing tests; must be tied to VSS

58 DIRCLK_DIS I Sets the DIRCLK function at power on

3, 49, 52, 57 VSSA S Analog Ground 4, 47, 55 VDDA S Analog 2.5 V Supply

56 VTOP S ADC High Voltage Reference

48 VBOT S ADC Low Voltage Reference

6-8-11-23-27-32-39-64 VSS S Ground 13-25 VDD_3.3 V S 3.3 V Supply 7-10-30-41-63 VDD S 2.5 V Supply

15 RESET I Reset, active at low level

42 STDBY I Sets STDBY at power on

16 F22/DiSEqC O 2 DiSEqC modulation, 22 kHz Tone, Programmable

40 DAC O 2 Programmable Digital to Analog Converter Output

2 BLOCK DIAGRAM

3 SYSTEM CHARACTERISTICS

The following given parameters are for indication purposes only. Carrier Loop Tracking Range:  ±fM_CLK /2 Carrier Loop Capture Range (C/N>=4 dB):  up to ± 5% fs in less than 100 Ksymbols  up to ± 2% fs in less than 10 Ksymbols C/N Threshold (lowest C/N at which capture is possible) = 1 dB. Timing Loop Capture Range (C/N>=2 dB):  up to ±250 ppm in less than 100 Ksymbols  conventions used for the above characteristics are: fsampling = fm_clk = fmaster_clock fs = fsymbol C/N = Carrier/Noise = PR = Puncture Rate Carrier Lock Indicator AGC1 Offset Comp. ADCs AGC2 Derotator Error Monitoring Viterbi Decoder Deinterleaver Reed-Solomon Decoder Energy Descrambler General Purpose Functions 22 kHz Tone DiSEqC Interface Clock Generator I2C Interface Nyquist & Interpolation Filter Timing Recovery Timing DCO Timing Lock Indicator C/N Indicator SDAT SCLT DAC IP0 OP0[2:0] D[7:0] V DD_3.3V VDD VSS D/P ERROR STR_OUT CLK_OUT CLK_IN/XTAL_IN AUX_CLK XTAL_OUT F22/DiSEqC SCL SDA AGC VDDA VTOP IN/IP QN/QP VBOT VSSA Eb

4 FUNCTIONAL DESCRIPTION

The STV0299B is a multistandard demodulator and error correction decoder IC for the reception of QPSK and BPSK modulated signals. It is intended for use in digital satellite television applications. The IC can accept two standards of QPSK modulated signals (DVB and DSS) as well as BPSK m odulated signals over a wide symbol frequency range (from 1 to 50 Msymbols/s). The signals are digitized via an integrated dual 6-bit analog to digital converter, and interpolated and digitally filtered by a Nyquist root filter (with a settable roll-off value of either 0.35 or 0.20). There are two built-in digital Automatic Gain Controls (AGCs). The first AGC allows the tuner gain to be controlled by the pulse density modulated output. The second AGC performs power optimization of the digital signal bandwidth (internal to the STV0299B). The digital signal then passes through the digital carrier loop fitted with an on-chip derotator and tracking loop, lock detector, and digital timing recovery. Forward error correction is integrated by way of an inner Viterbi soft decoder, and an outer Reed-Solomon decoder.

4.1 Front End Interfaces

4.1.1 I 2C Interface The standard I2C protocol is used whereby the first byte is Hex D0 for a write operation, or Hex D1 for a read operation. The I 2C interface operates differently depending on whether it is in normal or standby mode.

4.1.2 Write Operation (Normal Mode)

The byte sequence is as follows:

1 The first byte gives the device address plus the

direction bit (R/W = 0).

2 The second byte contains the internal address

of the first register to be accessed. 3 The next byte is written in the internal register. Following bytes (if any) are written in successive internal registers.

4 The transfer lasts until stop conditions are

encountered.

5 The STV0299B acknowledges every byte

transfer.

4.1.3 Read Operation (Normal Mode)

The address of the first register to read is programmed in a write operation without data, and terminated by the stop condition. Then, another start is followed by the device address and R/ W = 1. All following bytes are now data to be read at successive positions starting from the initial address. Figure 2 shows the I 2C Normal Mode Write and Read Registers.

4.1.4 I2C Interface in Standby Mode

Only three registers can be addressed while in standby mode: RCR (address 01 Hex), MCR (address 02 Hex) and ACR (address 03 Hex). These three registers can be either read or written to (refer to Figure 3). Only one register may be read or written to per sequence (no increment). While in standby mode, the Serial Clock (SCL) frequency must be lower than one tenth of the CLK_IN frequency (f CLK_IN / 10). Figure 2: I2C Read and Write Operations in Normal Mode Figure 3: I2C Read and Write Operations in Standby Mode Write registers 0 to 3 with AA, BB, CC, DD Read registers 2 and 3 Start Device Address, Write D0 ACK Register Address ACK Data AA ACK Data BB ACK Data CC ACK Data DD ACK Stop Start Device Address, Write D0 ACK Register Address 02 ACK Stop Start Device Address, Read D1 ACK Data Read CC ACK Data Read DD ACK Stop Write operation Read operation Start Device Address, Write D0 ACK Register Address 01, 02 or 03 ACK Data ACK Stop Start Device Address , Read D0 ACK Register Address ACK Stop Start Device Address, Read D1 ACK Reader Data ACK (or no ACK 1) Stop Note: 1 ACK is not absolutely necessary after Data

4 FUNCTIONAL DESCRIPTION (continued)

4.1.5 Specific Concerns about SCL

For reliable operation in Normal Mode, the SCL frequency must be lower than 1/40 of the Master Clock (M_CLK) frequency. Consequently, care should be taken to observe the following:

1 Before returning to Normal Mode from Standby

Mode, the M_CLK frequency must be selected such that fM_CLK ≥ 40 fSCL

2 After Power-on reset signal, the STV0299B

operates in Normal Mode. There are two possi- ble cases: - DIRCLK-DIS (pin 58) is grounded. M_CLK = CLK_IN, the fSCL frequency of the I2C bus must satisfy: . - DIRCLK-DIS (pin 58) is tied to VDD (where ), and the f SCL frequency of the I2C bus must satisfy: and fSCL ≤ 400 kHz. For example, this second operating mode is required when the application features both a 4 MHz XTAL and a 400 kHz I2C bus.

4.1.6 Identification Register

The Identification Register (at address Hex 00) gives the release number of the circuit. The content of this register at reset is presently A1 (same as STV0299).

4.1.7 Sampling Frequency

The STV0299B converts the analog inputs into digital 6-bit I and Q flows. The sampling frequency is fM_CLK which is derived from an external reference described in Section 4.1.8 ‘Clock Generation’. The maximum value of fM_CLK is 90 MHz. The sampling causes the repetition of the input spectrum at each integer multiple of fM_CLK . One has to ensure that no frequency component is folded in the useful signal bandwidth of fS(1+α )/2 where fS is the symbol frequency, and α is the roll-off value.

4.1.8 Clock Generation

An integrated VCO (optimised to run in the range of 300 to 400 MHz) is locked to a reference frequency provided by a crystal oscillator by the following relation: The VCO ’s loop filter is optimized for a reference frequency between 4 and 8 MHz. The VCO generates the following by division:  The Master Clock (M_CLK)  An auxiliary clock (AUX_CLK) which may either be in the MHz range or in the 25 Hz to 1500 Hz range for some specific LNB control (for example, 60 Hz).  A lower frequency, F22, typically 22 KHz, needed for LNB control or DiSEqC TM control. When DIRCLK_CTRL = 1, the crystal signal is routed directly to M_CLK; the VCO may still be used to generate AUX_CK and/or the F22 (used by the DiSEqCTM interface). If the internal VCO is not used by any of the dividers, it may be stopped in order to decrease the power consumption and/or radiation emissions. The only guaranteed function in standby mode is the I 2C Write/Read function of the three clock control registers. There are restrictions on the high and low level durations, and on the crystal (or external clock) frequency when the direct clock is used. These restrictions are explained in Section 4.1.5 Specific Concerns about SCL Frequency. fSCL CLK_IN fM_CLK 100 fSCL 100 fVCO fref 4M1 +()⋅⋅ fXTAL 4 M1+

Figure 4: Clock Signal Generation Note: 1 Refer to the Register List P[2:0] in table 1 2 At the rising edge of RESET signal (pin 15) the corresponding bit of the I2C bus register is forced to the status of pin STDBY or to DIRCLK-DIS. Table 1: Divider Programming Table 2: Summary of FM_CLK LPF VCO 1/4 1/16 ÷R 1/2 PHASE COMPARATOR÷(M+1) TO SERIAL SHIFTER ÷(K+1) OSC ÷P(Note 1) STDBY DiSEqC/tone burst modulator PROGRAMABLE DIVIDER DIRCLK-CTRL XT AL OUT XTAL IN/CLK-IN DIRCLK-DIS F22/ DiSEqC TM AUX_CLK M_CLK Note 2 VCO ON /OFF Note 2 VCO ON /OFF STDBY (I2C bit) I2C DIRCLK (I2C bit) I2C Re g 01[4:0] Re g 01[7:6] Re g 02[2:0] Re g 08[2:0] Re g 04 Re g 03 PRESCALER K(1:0) in register fREF = fXTAL divided by: 00 1 01 2 10 3 11 4 M(4:0) in register f VCO = fREF multiplied by: 00000 4 00001 8 00010 12 00011 16 11111 128 P(2:0) in register fM_CLK = fVCO divided by P: 000 4 001 6 010 8 011 12 100 16 101 24 110 32 111 48 DIRCLK_CTRL = 0 DIRCLK_CTRL =1 STDBY = 1 fVCO fXTAL 4 M1+ fM_CLK fVCO fM_CLK fCLK_IN= fM_CLK 0=

4.1.9 Clock Registers

The Reference Clock, Master Clock, Auxiliary Clock and F22 Frequency Registers are in Addresses 01, 02, 03 and 04. 4.1.10 I 2C Bus Repeater In low symbol rate applications, signal pollution generated by the SDA/SCL lines of the I2C bus may dramatically worsen tuner phase noise. In order to avoid this problem, the STV0299B offers an I 2C bus repeater so that the SDAT and SCLT are active only when necessary and muted once the tuner frequency has settled. Both SDA T and SCLT pins are set high at reset. When the microprocessor writes a 1 into register bit I 2CT, the next I2C message on SDA and SCL is repeated on the SDAT and SCLT pins respectively, until stop conditions are detected. To write to the tuner, the external microprocessor must, for each tuner message, perform the following:  Program 1 in I 2CT .  Send the message to the tuner. Any size of byte transfers are allowed, regardless of the address, until the stop conditions are detected. Transfers are fully bi-directional. The I 2CT bit is automatically reset at the stop condition. If not used for the I2C repeater, both SDAT and SCLT outputs may be used as general purpose output ports. SDAT status may be read on the DiSEqC register. Configuration is controlled by the I 2C repeater register in Address 0Ah. In the first version of the STV0299, operation of the repeater was very fast, and often too fast versus the rise time of the SDAT and SCLT signals. In the STV0299B, a programmable delay is implemented to accept a wide range of rise times on SDA T and SCLT. The delay is programmed with Reg.05 [5:4]. In practice, operation of the repeater is ensured in the following case:  Reg.05 [5:4]: xx  f M_CLK ≤ 90 MHz  RC ≤ 250ns (R: pull-up resistor, C: total capacitance on either SDAT or SCLT).

4.1.11 General Purpose Σ∆ DAC

A DAC is available in order to control external analog devices. It is built as a sigma-delta first-order loop, and has 12-bit resolution-it only requires an external low-pass filter (simple RC filter). The clock frequency is derived from the main clock by programmable division. The converter is controlled by two registers-one for clock divider control and 4 MSBs, and the other for the 8 LSBs. If the DAC is not needed, the DAC output may be used as an output port. The DAC Registers are in Addresses 06 and 07.

4.1.12 DiSEqC Interface

This interface allows for the simplification of real time processing of the dialog from microprocessor to LNB. It includes a FIFO that is filled by the microprocessor via the I 2C bus, and then transmitted by modulating the F22 clock adjusted beforehand to 22 kHz. Two control signals are available on the I2C bus: FE (FIFO empty) and FF (FIFO full). A typical byte transfer loop, as seen from the microprocessor, may be the following: While (there is data to transfer)

1 Read the control signals

2 If FF=1, go to 1

3 Write byte to transfer in the FIFO

Note, for the above transfer loop, the following:  At the beginning, the FIFO is empty (FE=1, FF=0). This is the idle state.  As soon as a byte is written in the FIFO, the transfer will begin.  After the last transmitted byte, the interface will go into the idle state. Modulation The output is a gated 22 kHz square signal.  In the idle state, modulation is permanently inactive.  In byte transmission, the byte is sent (MSB first) and is followed by an odd parity bit. A byte transmission is therefore a serial 9-bit transmission with an odd number of “1’s”. Each bit lasts 33 periods of F22 and the transmission is PWM-modulated. - Transmission of “0’s”. There are two submodes controlled by PortCtrl(2): a) PortCtrl2 = 1: Modulation is active during 22 pulses, then inactive during 11 pulses (2/3 PWM). b) PortCtrl2 = 0: Modulation is active during 33 pulses (3/3 PWM). - Transmission of “1’s”. During transmission of “1’s”, modulation is active during 11 pulses, then inactive during 22 pulses (1/3 PWM). This is compatible with “Tone Burst” in older LNB protocols. For the “Modulated Tone Burst”, only one byte (with value Hex FF) is written in the FIFO. The parity bit is 1, and as a result, the output signal is 9 bursts of 0.5 ms, separated by 8 intervals of 1 ms.

For the “Unmodulated Tone Burst” Port CTRL 2 is set to 0 and, only one byte, of value 00h is sent. The parity bit is still 1, and as a result, the signal is a continuous train of 12.5 ms. When the modulation is active, the DiSEqC output is driven alternatively to V DD and VSS levels. The DiSEqC and Lock Control, DiSEqC FIFO and DiSEqC Status Registers are in Addresses 08, 09 and 0Ah. Figure 5: Schematic showing Bit Transmission Table 3: Note: 1 Byte to transfer in DiSEqC mode. 2 In mode PortCtrl (1:0)=10, the F22/DiSEqC pin returns to High -2 mode once the transmission is completed.

4.1.13 Standby Mode

A low power consumption mode (standby mode) can be implemented (in this mode, fM_CLK = 0). In standby mode, the I2C decoder still operates, but with some restrictions (see Sections 4.1.4 and 4.1.5). Standby mode can be initiated or stopped by I2C bus commands as described in MCR Register 02. At power-on, the circuit starts to operate in standby mode when the STDBY pin (pin 42) is tied to V DD . This guarantees low power consumption for the stand-alone modules (PCMCIA size front-end modules) before any command is initiated. After the power-on sequence, the standby mode is entirely controlled via MCR Register (02). Idle 11 Periods 11 Periods 11 Periods Next bit Transmission of 1’s Transmission of 0’s: a) PortCtrl2 = 1 b) PortCtrl2 = 0 PortCtrl (1:0) PortCtrl (2) FIFO Output

00 X empty 0

01 X empty 1

10 0 DATA = 00 Unmodulated tone burst

1 DATA = FFor00 Modulated tone burst

1 Note 1 DiSEqC signal

11 X XX Continuous tone

4.2 Signal Processing

4.2.1 I and Q Inputs

The ADC features differential inputs, but in most applications I & Q signals are single-ended. In such applications, I and Q signals from the tuner are fed to the respective IP and QP inputs through a capacitor. The I N and QN pins are DC biased, typically to VBOT .The internal biasing of the ADC is done on the circuit at the mid-voltage between VTOP and VBOT . The Input/Output Configuration Register is described in Address 0Ch.

4.2.2 Main AGC (or AGC1)

The modulus of the I/Q input is compared to a programmable threshold, m1, and the difference is integrated. This signal is then converted into a pulse density modulation signal to drive the AGC output. It should be filtered by a simple analog filter to control the gain command of any amplifier before the A to D converter. The output converter operates at f M_CLK /8 in order to decrease the radiated noise and to simplify the filter design. The output is a 5 V tolerant open drain stage. The reset value of the coefficient allows an initial settling time of less than 100k master clock periods. The 8 integrator MSBs may be read or written at any time by the microprocessor. When written, the LSB ’s are reset and the coefficient may be set to zero by programming (in this case, the AGC is reduced to a programmable 8-bit voltage synthesizer). The time constant of agc1 is estimated as followed: with m1 = AGC1 reference level. The AGC1 Control, AGC1 Reference and AGC1 Integrator Registers are in Addresses 0D and 0F .

4.2.3 Nyquist Root and Interpolation Filters

Two roll off values are available: 0.35 and 0.20. Refer to the Input/Output Configuration Register in Address 0C.

4.2.4 Offset Cancellation

This device suppresses the residual DC component on I and Q. The compensation may be frozen to its last value by resetting the DC offset compensation bit in the AGC Control Register in Address 0D.

4.2.5 Signal AGC (or AGC2)

The rms value of I and Q is measured after the Nyquist filter and compared to a programmable value, m2, such as that of the main AGC. The integrated error signal is applied to a multiplier on each I and Q path. The AGC2 Control Register is in Address 10. Bits [7:5] give the AGC2 coefficient, which sets beta_agc2, the gain of the integrator. Table 4 shows how beta_agc2 is programmed with AGC2 coefficient (which is related to the time constant of the AGC). Table 4: If AGC2 Coefficient = 0, the gain remains unchanged from its last value. The time constant is independent of the symbol frequency, however it does depend on the modulus, m1, of the input signal, programmed in AGC1, with the following approximate relation: The AGC2 Integrator Registers (2 bytes - MSB and LSB) are in Addresses 18 and 19. These values may be read or written by the microprocessor. When written, all the LSB’s integrator bits are reset. This value is an image of the signal power in the useful band. Compared with the total power of the signal, the out-of-band power may be computed (noise, or other channel). Tagc1 26 βagc1– AGC2 Coefficient beta_agc2 31 6 46 4 5 256 6N / A 7N / A Tagc2 60 10 3× TM_CLK⋅

4.3 Timing Recovery

4.3.1 Timing Control

The loop is parametrized by two coefficients: alpha_tmg and beta_tmg. alpha_tmg can take values from 0 to 4, and beta_tmg from 0 to 7 (Register 0E). When the parameter is 0, the actual coefficient value is zero. The 8 MSBs of the frequency accumulator may be read or written at any time by the I 2C bus— when written, all LSBs are reset. The Symbol Frequency Registers (MSB, Middle Bits and LSB) are in Addresses 1F , 20 and 21. These must be programmed with the expected symbol frequency. The units are: Write mode is effective when writing the Middle Bit Register. The MSB Register must be loaded before the Middle Bit Register. The value of the Timing Frequency Register, when the system is locked, is an image of the frequency offset. The unit is f S/219 (approx. 2 ppm). It should be as close as possible to 0 (by adjusting symbol frequency register value) in order to have a symmetrical capture range. Reading it allows for optimal trimming of the timing range (Register 1A). The actual symbol frequency is: where f s_reg is the content of the symbol frequency register and Tmg_reg the content of the timing frequency register.

4.3.2 Loop Equation

The timing loop may be considered as a second order loop. The natural frequency and the damping factor may be calculated using the following formula: where, f S is the symbol frequency, m2 is the AGC2 reference level and β is programmed by the timing register: The damping factor is: where m2 is the reference level of the AGC2 register. Table 5 shows the natural frequency in DVB, with nominal reference level m2 = 20, for different values of beta_tmg and alpha_tmg, without noise.

4.3.3 Timing Lock Indicator

The timing lock indicator reports a value dependent upon the signal-to-noise ratio and on the signal lock state. With an AGC2 Reference level m2 = 20, if the timing lock indicator is above 48, the timing is locked; if it is above 42, this shows that a QPSK signal is present, either locked with low C/N (<3.6 dB) or unlocked with higher C/N; the ambiguity may be solved by changing on purpose the timing frequency of 1%; if it was locked before, the indicator should be now under 42. The indicator needs 30K symbols for stabilization from unlock to lock after a frequency change. The timing lock registers - the Timing Lock Setting Register and the Timing Lock Indicator Register - are in Addresses 11 and 17. Table 5: fM_CLK fSact fM_CLK fs_reg⋅() 2f s Tmg_reg⋅⋅()+ fn 5.2 10 6– fS m2 β⋅⋅= β 2beta_tmg= ξ 0.134 m2 2 alpha_tmg⋅ ⋅ 2beta_tmg a l p h a _ t m g 1234 beta_tmg Natural Frequency for fS =2 0M b a u d Damping Factor

4.4 Carrier Recovery and Derotator Loop

The tracking range of the derotator is ± fM_CLK /2 (± fsampling/2). The initial frequency search may therefore be performed on several MHz ranges without reprogramming the tuner. Three phase detectors are selectable using software:  Phase detector algorithm 0: This algorithm should only be used for BPSK reception.  Phase detector algorithm 1: This algorithm is used with QPSK reception, over a small range of capture phases and with a channel noise value over 4.5 dB.  Phase detector algorithm 2: For QPSK reception, it is used after locking, to minimize the bit error rate in low channel noise conditions. Algorithm 2 is recommended for most applications. The loop is controlled through α and β parameters. The carrier loop control registers (the Alpha Carrier Register, the Beta Carrier Register and the Carrier Frequency Register) are in Addresses 13, 14, 22 and 23.

4.4.1 Loop Parameters

Like the timing loop, the carrier loop is a second-order system where two parameters, α and β, may be programmed with alpha_car and beta_car respectively. The natural frequency (f n) is: The damping factor is: where α =( 2 + a )⋅2b⋅214, with b ≥ 1, and β = (4+2c+d)⋅2e, with e≥ 1. m2 is the reference level in the AGC2 register.

4.4.2 Carrier Lock Detector

The carrier lock detector provides an indicator with a high value when the carrier is locked, dependent on the channel noise. When the carrier is not locked, the indicator value is low. The indicator value is compared to a programmable 8-bit threshold (Register 15h). The result of this comparison (1 if greater than the threshold, else 0 if not) is written as the Carrier Found flag (CF), and may be read in the status register. The CF signal may be permanently routed on the output LOCK (see Register 08h). The Lock Detector Threshold Register and Lock Detector Value Register are in Addresses 15 and 1C.

4.4.3 Derotator Frequency

The derotator frequency can be either measured (read operation) or forced (write operation). Derot_freq is a 16-bit signed value. The Derot_freq Registers are Registers 22 and 23.

4.4.4 Carrier Frequency Offset Detector

The carrier recovery loop features a carrier frequency offset detector and two phase detectors. When the carrier frequency offset detector is enabled, the central loop frequency is modified proportionally to the carrier offset. The gain and time constants of the detector are set by CFD[6:4] and CFD[3:2] respectively. When the carrier loop is about to “phase lock” with the carrier, the frequency detector stops automatically and the phase lock is ensured by the selected phase detector. This switchover point is determined by the threshold CFD [1:0]. For stability reasons, the gain CFD [6:4] should not exceed the coefficient e[3:0] of Register BCLC. The carrier frequency offset detector is in Address 12.

4.5 Noise Indicator

The noise indicator may be used to facilitate the antenna pointing or to give an idea of the RF signal quality and of the front-end installation (dish, LNB, cable, tuner or ADC). A simple C/N estimator can be easily implemented by comparing the current indications with a primarily-recorded look-up table. The time constant ranges from 4 k to 256 k symbols. The 16 MSB of the result may be read by the microprocessor (Registers 24 and 25). fn 71 0 6– fM_CLK m2 β⋅() fS fM_CLK ξ 22 10 6– α m2 fM_CLK freq() kHz Derot_freq

4.6 Forward Error Correction

4.6.1 FEC Modes

Since the STV0299B is a multistandard decoder, several combinations are possible, at different levels:  The demodulator may accept either QPSK or BPSK signals - the only impact is on the carrier algorithm choice (refer to Chapter 4.4). The algorithm choice also affects the carrier lock detector and the noise evaluation.  There two primary options concerning the FEC operation - between DVB, DSS and Reserved Mode.  There are two options concerning the FEC feeding. The first is IQ flow, which is the usual case in QPSK modes DVB or DSS. The second mode is I-only flow, used for BPSK. The FEC Mode Register is in Address 28. In Modes DVB and DSS, data is fed to the Viterbi decoder. Other parts of the decoding (such as the Convolutional Deinterleaver) may be bypassed.

4.6.2 Viterbi Decoder and Synchronization

The convolutive codes are generated by the polynomial G x = 171 octets and Gy = 133 octets in modes DVB or DSS. The Viterbi decoder computes for each symbol the metrics of the four possible paths, proportional to the square of the Euclidian distance between the received I and Q and the theoretical symbol value. The puncture rate and phase are estimated on the error rate basis. Several rates are allowed and may be enabled/disabled through register programming: For each enabled rate, the current error rate is compared to a programmable threshold. If it is greater than this threshold, another phase (or another rate) is tried until the right rate is obtained. A programmable hysteresis is added to avoid losing the phase during short term perturbation. The rate may also be imposed by external software, and the phase is incremented only upon request by the microprocessor. The error rate may be read at any time in order to use an algorithm other than that implemented. The Viterbi decoder produces an absolute decoding. The decoder is controlled via several Viterbi Threshold Registers (Registers 29, 2A, 2B, 2C and 2D). For each Viterbi Threshold Register, bits 6 to 0 represent an error rate threshold - the average number of errors occurring during 256-bit periods. The maximum programmable value is 127/256 (higher error rates are of no practical use). The Puncture Rate and Synchro Register is in Address 31. The automatic rate research is only done through the enabled rates (see the corresponding bit set in the Puncture and synchro register). In DSS, the puncture rate 6/7 replaces the puncture rate 7/8. In DSS, it is recommended that you disable puncture rates 3/4 and 5/6 in order to save time in the synchronization process. The VSEARCH Register is in Address 32. VSEARCH bit 7 (A/M) and bit 6 (F) programs the automatic/manual (or computer aided) search mode as follows:  If A/M =0 and F=0, automatic mode is set. Successive enabled punctured rates are tried with all possible phases, until the system is locked and the block synchro found. This is the default (reset) mode.  If A/M=0 and F=1, the current puncture rate is frozen. If no sync is found, the phase is incremented, but not the rate number. This mode allows shortening of the recovery time in case of noisy conditions. The puncture rate is not supposed to change in a given channel. In a typical computer-aided implementation, the research begins in automatic mode. The microprocessor reads the error rate or the PRF flag in order to detect the capture of a signal, then it switches F to 1, until a new channel is requested by the remote control.  If AM=1 manual mode is set. In this case, only one puncture rate should be validated - the system is forced to this rate, on the current phase, ignoring the time-out register and the error rate. In this mode, each 0 to 1 transition of the bit F leads to a phase incrementation, allowing full control of the operation by an external microprocessor by choosing the lowest error rate. The reset values are A/M=0, and F=0 (automatic search mode). The VERROR Register (a read only register) is in Address 26. The last value of the error rate may be read at any time in the register. Unlike the VTH, the possible range is from 0 to 255/256. The VSTATUS Register (a read only register) is in Address 1B.

4.6.3 Synchronization

In DVB, the packet length after inner decoding is 204. The sync word is the first byte of each packet. Its value is Hex 47, but this value is complemented every 8 packets. In DSS, the packet length is 147 and the sync word is Hex 1D. An Up/Down Sync counter counts whenever a sync word is recognized with the correct timing, and counts down during each missing sync word. This counter is bounded by a programmable maximum - when this value is reached, the LK bit (“locked”) is set in the VSTATUS register. When the event counter counts down to until 0, this flag is reset.

4.6.4 Error Monitoring

A 16-bit counter, ERRCNT, allows the counting of errors at different levels. ERRCNT is fed either by:  the input QPSK bit errors (that are corrected by the Viterbi decoder), or,  the bit, or,  the byte error (that are corrected by the Reed-Solomon decoder), or,  the packet error (not corrigible, leading to a pulse at the ERROR output). The content of ERRCNT may be transferred to the read only registers ERRCNT_LOW (LSB) and ERRCNT_HIGH (MSB). Two functional modes are proposed, depending on a control register bit: 1 Error Mode = 0. This is an error rate measure, that tells the number of errors occurring within a specified number of output bytes, NB. NB has four possible values given in the Error Control Register in Address 34. Every NB bytes, the state of the error counter is transferred to a 16-bit register, then the error counter is reset. The Error Count Registers in Addresses 1D and 1E may be read by the microprocessor via I 2C bus. Two ways of reading may be used: 16-bit reading, starting with MSB, or 8-bit reading (LSB only or MSB only). 2 Error Mode = 1. The error counter just counts the error; the I 2C register permanently copies the content of the error counter. When the MSB byte is read, the error counter is reset. In both modes, the 16-bit counter is saturated to its maximum value.

4.6.5 Convolutional Deinterleaver

In DVB, the convolutional deinterleaver is 17 x 12. The periodicity of 204 bytes per sync byte is retained. In DSS, the convolutional deinterleaver is 146 x 13, and there is also a periodicity of 147 bytes per sync byte. The deinterleaver may be bypassed - for details, see Section 4.6.6 ‘Reed-Solomon Decoder and Descrambler’.

4.6.6 Reed-Solomon Decoder and

The input blocks are 204-byte long with 16 parity bytes in DVB. The synchro byte is the first byte of the block. Up to 8 byte errors may be fixed. The Code Generator polynomial is: over the Galois Field generated by: Energy dispersal descrambler and output energy dispersal descrambler generator: The polynomial is initialized every eight blocks with the sequence 100101010000000. The synchro words are unscrambled and the scrambler is reset every 8 packets. The output interface may be forced into high impedance mode by setting bit 0 of Address 28. Doing this affects the D[7:0], CLK_OUT, STR_OUT, D/P and ERROR pins. This also allows for board testing, and “OR ” wiring several link circuits (for example, cable links). The output stream is either parallel (byte stream) or serial (bit stream) depending on bit 1 of Address 28. The outputs are controlled by the RS Control Register in Address 33.

4.6.7 Parallel Output Interface

A schematic diagram of the parallel output interface is shown in Figure 7. The parallel output format is compliant with the DVB common interface protocol. When the SYNC is not found (LK = 0 in the status register), D/P (corresponding to the MiVAL signal of the DVB common interface standard) remains at a low level. CLK_OUT has a duty cycle between 40 and 60%. x15 x14 1++

4.6.8 Serial Output Interface

The serial output interface is shown in Figure 6. The serial bit stream is available on D7, where MSB is first to reconstruct the original order. If RS0 = 0, then the parity bits are output (Register 33). If RS0 = 1, the data is null during the parity time slots. STR_OUT is only high during the first bit of each packet, instead of during the first byte in parallel mode. ERROR has the same function as in parallel mode. CLK_OUT is the serial bit clock; it is derived from either the master clock, M_CLK, (if SerClk = 0 in Registers 02 and B3), or from the internal VCO frequency divided by 6, (if SerClk = 1), by skipping some pulses to accommodate the frequency difference. All of the outputs are synchronous of the same master clock edge. D0, STR_OUT, D/P and ERROR may be properly sampled externally by the rising edge of CLK_OUT, if RS1 = 0, or by the falling edge of CLK_OUT if RS1 = 1. This clock runs continuously, even during parity data, whatever the value of RS0. The first bit detected in a valid packet may be decoded if it is found on the appropriate edge of CLK_OUT, where STR_OUT = 1, ERROR = 0, D/P = 1. The following bits only require the assertion of D/P (while D/P = 1,...). Outputs D0 to D6 remain at low level in serial mode. Figure 6: Serial Output Interface Figure 7: Parallel Output Interface STR_OUT ERROR RS0 = 0 RS0 = 1 RS0 = 0 RS0 = 1 RS1 = 1 RS1 = 0 D/P Data Parity ParityUseful Data

1 Packet

CLK_OUT or 6/fVCO Data Parity No Error Uncorrectible Packet No Error C LK_OUT D/P STR_OUT ERROR RS1 = 0 RS1 = 1 RS0 = 0 RS0 = 1 RS0 = 0 RS0 = 1 RS0 = 0 RS0 = 1

Table 6: Functional I2C Register Map Name Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ID $00(r/w) Chip identification number Release number RCR * $01(w) K(1:0) dirclk M(4:0) MCR * $02(w) stdby VCO off serclock P(2:0) ACR * $03(w) prescaler divider F22FR $04(w) frequency register f_reg(7:0) 12CRPT $05(w) 12CT T - constant T- constant SCLT value SDAT value DACR1 $06(w) DAC mode DAC(11:8) DACR2 $07(w) DAC(7:0) DiSEqC $08(w) LOCK output LOCK conf DiSEqC DiSEqC mode DiSEqC FIFO $09(w) DiSE1C FIFO1(7:0) DiSEqC Status $0A(r) IP SDAT input status FE FF IOCFG $0C(w) OP1_ opdrain OP1_1 OP0_ opdrain OP01 Nyquist filter I/Q conv AGC1C $0D(w) DCadj beta_agc1(2:0) RTC $0E(w) alpha_tmg(2:0) beta_tmg(2:0) AGC1R $0F(w) Iagc Reference Value ACG2O $10(w) AGC2 coeff(2:0) ACG2_Ref TLSR $11(w) step_minus(3:0) step_plus(3:0) CFD $12(w) FD on/off beta_fd FDTC LDL ACLC $13(w) derot on/off noise_TC alpha_car BCLC $14(w) Ph_detect_algo beta_car CLDT $15(w) Lock detector threshold AGC1I $16(r/w) AGC integrator value TL1R $17(w) Timing lock indicator(7:0) ACG2I1 $18(r/w) ACG2 integrator MSB ACG2I2 $19(r/w) ACG2 integrator LSB RTF $1A(r/w) Timing loop frequency(7:0) VSTATUS $1B(r) CF PRF LK PR(2:0) CLDI $1C(r) Lock detector integrator ECNTH $1D(r) Error count MSBs ECNTL $1E(r) Error count LSBs SFRH $1F(w) Symb_freq(19:12) SFRM $20(w) Symb_freq(11:4) SFRL $21(w) Symb_freq(3:0) CFRM $22(r/w) Carrier frequency register MSB CFRL $23(r/w) Carrier frequency register LSB NIRH $24(r) Noise indicator MSBs NIRL $25(r) Noise indicator LSBs VERROR $26(r) Error value FECM $28(w) FEC mode out type out imp VTH0 $29(w) t0[6:0] VTH1 $2A(w) t1[6:0] VTH2 $2B(w) t2[6:0] VTH3 $2C(w) t3[6:0] VTH4 $2D(w) t4[6:0] PR $31(w) E4 E3 E2 E1 E0 V SEARCH $32(w) A/M F SN(1:0) TO(1:0) H(1:0) RS $33(w) deint sync RS descram err bit MPEG clk pol clk cfg ERRCNT $34(w) Errmode tsters Error source NoE

Note: All register addresses are hexadecimal values. Signed registers are 2’s complement. All registers are read/write registers except those specifically flagged as read-only (RO). All registers not listed in the below table, between 0 and 4E, should be programmed to Name HEX Address Reset Value Bit Position Signal Description IDENTIFICATION REGISTER (Read Only) (refer to Section 4.1.6 on page 8) ID 00 A1 [7:0] Gives the release number of the circuit in order to ensure software compatibility. REFERENCE CLOCK REGISTER (refer to Section 4.1.8 on page 8) RCR 01 18 or 38 [7:6] K[1:0] 5 DIRCLK (Reset value depends on the polarity of DIRCLK-DIS pin). [4:0] M[4:0] MASTER CLOCK REGISTER (refer to Section 4.1.8 on page 8) MCR 02 34 or B4 7 STDBY (Reset value depends on the polarity of STDBY pin).

6 VCO ON/OFF

0: ON 1: OFF [5:4] These bits must be programmed to one.

3 SERCLK

0: Maximum instantaneous SERCL = Master Clock 1: Maximum instantaneous SERCL = [2:0] P[2:0] VC0 to M_CLK divider FVCO

5R E G I S T E R L I S T (continued) AUXILIARY CLOCK REGISTER (refer to Section 4.1.8 on page 8) ACR 03 2A [7:0] ACR Prescaler and Divider This register is made up of the ACR [7:5] Prescaler field and the ACR [4:0] Divider field. The values in these fields configure the auxiliary clock function, the prescalar value, the clock signal frequency. The frequency range is given for fVCO =4 0 0M H z . ACR [7:0] Function Prescaler Signal Frequency Range 000XXXX0 Output Port N/A output port = 0 N/A 000XXXX1 Output Port N/A output port = 1 N/A 001XXXXX HF generator 1 fVCO /8/ACR[4:0] 1.6 to

50 MHz

generator 64 fVCO /8192/(32+ACR[4:0]) 775 to 1525 Hz 011XXXXX LF generator 128 fVCO /16384/(32+ACR[4:0]) 388 to 762 Hz 100XXXXX LF generator 256 fVCO /32768/(32+ACR[4:0]) 194 to 381 Hz 101XXXXX LF generator 512 fVCO /65536/(32+ACR[4:0]) 97 to 190 Hz 110XXXXX LF generator 1024 fVCO /131072/(32+ACR[4:0]) 49 to 95 Hz 111XXXXX LF generator 2048 fVCO /262144/(32+ACR[4:0]) 24 to 47 Hz In the LF generator, the programmable division factor is 32 + ACR[4:0]. In the HF generator, it is simply ACR[4:0]. This allows the building of any frequency from 24 Hz to 1.1 kHz (within ±1.5%) in the full operating range. The output signal is square in all cases. When the auxiliary register is written, the prescaler and the program- mable divider are reset. F22 FREQUENCY REGISTER (refer to Section 4.1.8 on page 8) F22FR 04 8E [7:0] The actual frequency is f VCO /(128 R[7:0]). When this register is accessed, the divider by 16 (also common to AUX_CLK) and the divider by R[7:0] are initialized. I2CRPT REGISTER (refer To Section 4.1.10 on page 10) I2CRPT 05 0F 7 I2CT 1: I2C repeater 0: Output port [6] Must be programmed to zero. [5:4] Repeater response time; value does not matter if the external time constant ≤ 250ns. [3] Must be programmed to zero.

2 SCLT Port value

1 This bit must be programmed to zero.

0 SDAT Port value

Position Signal Description

5R E G I S T E R L I S T (continued) DAC REGISTERS (refer to Section 4.1.11 on page 10) DACR1 (MSB) 06 A2 [7:5] DAC Mode This field controls the DAC: 000: Functions as output port. The DAC output permanently 0. 001: Functions as output port. DAC output permanently 1. 010: High impedance mode. 100: Functions as DAC. Duty cycle modulated at fCLK /16. 101: Functions as DAC. Duty cycle modulated at fCLK /4. 110: Functions as DAC. Duty cycle modulated at fCLK. Other: Reserved functions. 4 This bit must be programmed to zero. [3:0] DAC: 4 MSB DACR2 (LSB) 07 00 [7:0] DAC: 8 LSB DISEQC AND LOCK CONTROL REGISTER (refer to Section 4.1.12 on page 10) DiSEqC 08 60 [7:6] Lock Output 00: 0 01: 1 10: CF 11: LK

5 Lock Configuration

1: Open drain 0: Push-pull [4:3] These bits must be programmed to zero.

2 DiSEqC/Unmodulated Burst

[1:0] DiSEqC Mode DISEQC FIFO (refer to Section 4.1.12 on page 10) DiSEqC FIFO 09 00 [7:0] FIFO byte DISEQC STATUS (refer to Section 4.1.12 on page 10) DiSEqC Status 0A R0 7 Input Port: This bit gives the input level on the pin IP0. It is an input port for general use purposes.

6 SDAT Input State

[5:2] Not relevant.

1 FIFO empty

0 FIFO full

Position Signal Description

5R E G I S T E R L I S T (continued) INPUT/OUTPUT CONFIGURATION REGISTER (refer to Section 4.2.1 on page 12) IOCFG 0C F0 7 OP1 control 1: Open drain 0: Normal

6 OP1 value

5 OP0 control

1: Open drain 0: Normal

4 OP0 value

3 This bit must be programmed to zero. [2:1] Nyquist Filter These bits determine Nyquist filter settings: 00 = raised cosine at 35% 01 = raised cosine at 20% 10 = reserved 11 = reserved

0 Bit 0 when set, multiplies the data on the Q input by -1 in order to

accommodate QPSK modulation with another convention of rotation sense. This is equivalent to a permutation of I and Q inputs, or a spec- tral symmetry. This permutation is performed after derotation. AGC1 CONTROL REGISTER (refer to Section 4.2.2 on page 12) AGC1C 0D 81 7 DC offset compensation: 1: On 0: Off [6:3] These bits must be programmed to zero. [2:0] beta_agc1 TIMING LOOP REGISTER (refer to Section 4.3.1 on page 13) RTC 0E 23 7 This bit must be programmed to zero. [6:4] alpha_tmg 3 This bit must be programmed to zero. [2:0] beta_tmg AGC1 REFERENCE REGISTER (refer to Section 4.2.2 on page 12) AGC1R 0F 54 7 Iagc 1: Invert 0: Normal If Iagc is set, the output signal is complemented (i.e. a high value for the AGC voltage will cause a high gain in the tuner). 6 This bit must be programmed to zero. [5:0] AGC1 Reference Value (m1). Refer to page 12. AGC2 AND OFFSET CONTROL REGISTER (refer to Section 4.2.5 on page 12) AGC2O 10 74 [7:5] AGC2 Coefficient [4:0] AGC2_Ref (m2) Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) TIMING LOCK SETTING REGISTER (refer to ) TLSR 11 88 [7:4] Must be programmed to 8 (to be confirmed) [3:0] Must be programmed to 4 (to be confirmed) CARRIER FREQUENCY DETECTOR REGISTER (refer to Chapter 4.4 on page 14) CFD 12 F7 7 1: Carrier Frequency Offset Detector coupled to Carrier recover loop 0: Carrier Frequency Offset Detector disabled [6:4] Gain for Carrier Frequency Offset Detector [3:2] Time constant for Carrier Frequency Offset Detector [1:0] Lock Detector threshold to disable the Carrier Frequency Offset Detector: 00: -16 01: -32 10: -48 11: -64 ALPHA CARRIER AND NOISE ESTIMATOR REGISTER (refer to Chapter 4.5 on page 14) ACLC 13 88 7 Derotator On/Off 1: On 0: Off 6 This bit must be programmed to zero. [5:4] Noise Estimator Time Constant 00: 4 k symbols 01: 16 k symbols 10: 64 k symbols 11: 256 k symbols [3:0] alpha_car Bits 3, 2 and 1: b[2:0] Bit 0: a BETA CARRIER REGISTER (refer to Chapter 4.4 on page 14) BCLC 14 5C [7:6] phase_detector_algo Phase detector algorithm: 00: Algorithm 0 (BPSK application) 01: Algorithm 1 (QPSK application) 10: Algorithm 2 (QPSK application) 11: Reserved [5:0] beta_car Bits 5 to 2: e[3:0] Bit 1: c Bit 0: d CARRIER LOCK DETECTOR THRESHOLD REGISTER (refer to Section 4.4.2 on page 14) CLDT 15 14 [7:0] Signed Number AGC1 INTEGRATOR REGISTER (refer to Section 4.2.2 on page 12) AGC1I 16 [7:0] AGC Integrator Value (Signed Number) TIMING LOCK INDICATOR REGISTER (refer to Section 4.3.3 on page 13) TLIR 17 R0 [7:0] (Not Signed) Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) AGC2 INTEGRATOR REGISTERS (refer to Section 4.2.5 on page 12) AGC2I1 (MSB) 18 [7:0] AGC2 Integrator MSB Bits (Not Signed) AGC2I2 (LSB) 19 [7:0] AGC2 Integrator LSB Bits (Not Signed) TIMING FREQUENCY REGISTER (refer to Section 4.3.1 on page 13) RTF 1A [7:0] Signed Number VSTATUS REGISTER (Read Only) (refer to Section 4.6.3 on page 16) VST ATUS 1B RO 7 Carrier Found Flag When the Carrier Found (CF) flag (see Chapter 4.4 on page 14) is set, it indicates that a QPSK signal is present at the input of the Viterbi decoder. [6:5] Not relevant.

4 Puncture Rate Found

The Puncture Rate Found (PRF) bit indicates the state of the punc- ture rate research: 0 for searching and 1 when found. This bit is irrele- vant in manual mode.

3 Locked/Searching Sync Word

The LK bit indicates the state of the sync word search: 0 for searching and 1 when found. [2:0] Current Puncture Rate, PR[2:0] The Current Puncture Rate (CPR) bits hold the current puncture rate indices, as follows: 100: Basic 1/2 (modes DVB and DSS) or Punctured 1/2 (reserved mode) 000: Punctured 2/3 001: Punctured 3/4 010: Punctured 5/6 011: Punctured 7/8 (modes DVB and DSS) or 6/7 (reserved mode) CARRIER LOCK DETECTOR VALUE REGISTER (refer to Section 4.4.2 on page 14) CLDI 1C [7:0] Signed Number ERROR COUNT REGISTERS (refer to Section 4.6.4 on page 16) ERRCNT_HIGH 1D [7:0] MSB byte (Not Signed) ERRCNT_LOW 1E [7:0] LSB byte (Not Signed) SYMBOL FREQUENCY REGISTERS (refer to Section 4.3.1 on page 13) SFRH 1F 80 [7:0] Symb_freq (MSBs) The reset value of Hex 800000 corresponds to fM_CLK /2. SFRM 20 00 [7:0] Symb_freq (Middle SBS) SFRL 21 00 [7:4] Symb_freq (LSBS) [3:0] These bits must be programmed to zero. CARRIER FREQUENCY REGISTER (refer to Chapter 4.4 on page 14) CFRM 22 [7:0] Derotator Frequency (MSB) (signed value) CFRL 23 [7:0] Derotator Frequency (LSB) (signed value) NOISE INDICATOR REGISTERS (Read Only) (refer to Chapter 4.5 on page 14) NIRH 24 RO [7:0] Noise Indicator (MSB) (Not Signed) NIRL 25 RO [7:0] Noise Indicator (LSB) (Not Signed) Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) VERROR REGISTER (Read Only) (refer to Section 4.6.2 on page 15) VERROR 26 RO [7:0] Error Rate (Not Signed) FEC MODE REGISTER (refer to Section 4.6.1 on page 15) FECM 28 01 [7:4] FEC Mode This field indicates the FEC Operation mode and the FEC feeding. 0000: DVB (QPSK), FEC feeding IQ/IQ/IQ/IQ 0001: DVB (BPSK extension), FEC feeding IX/IX/IX/IX 001X: Reserved 0100: DSS, FEC feeding IQ/IQ/IQ/IQ 1XXX: Reserved [3:2] These bits must be programmed to zero.

1 Output Type

1: Serial 0: Parallel

0 Output Impedance

1: High Impedance 0: Normal Impedance VITERBI THRESHOLD REGISTERS (refer to Section 4.6.2 on page 15) VTH0 29 1E [7:0] Rate = 1/2 Threshold. VTH1 2A 14 [7:0] Rate = 2/3 Threshold. VTH2 2B 0F [7:0] Rate = 3/4 Threshold. VTH3 2C 09 [7:0] Rate = 5/6 Threshold. VTH4 2D 05 [7:0] Rate = 7/8 or 6/7 Threshold. PUNCTURE RATE AND SYNCHRO REGISTER (refer to Section 4.6.2 on page 15) PR 31 1F [7:6:5] These bits must be programmed to zero. 4 Enable punctured rates 7/8 (in DVB) or 6/7 (in DSS). 3 Enable punctured rate 5/6. 2 Enable punctured rate 3/4. 1 Enable punctured rate 2/3. 0 Enable basic or punctured rate 1/2. Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) VITERBI AND SYNCHRO SEARCH REGISTER (refer to Section 4.6.2 on page 15) VSEARCH 32 19 7 0: Automatic search mode 1: Manual search mode 6F r e e z e [5:4] SN[1:0] This is the averaging period. The field gives the number of bits required to calculate the rate error. 00 = 1024 01 = 4096 10 = 16384 11 = 65536 Reset Value: SN = 01 (4096 bits) [3:2] TO[1:0] This is the time out value (given in 1024-bit periods). This field is used to program the maximum duration of the synchro word research in automatic mode. If no sync is found within this duration, and if bit RS6 (Sync Enable) is set in the Reed-Solomon register, another phase or puncture rate is tried. If RS6 = 0, the time-out has no effect. 00 = 16 01 = 32 10 = 64 11 = 128 Reset Value: TO = 10 (64k bit periods) [1:0] H[1:0] This is the hysteresis value. This field is used to program the maxi- mum value of the Sync counter. The unit is the block duration (204 bytes in DVB, 147 in DSS). 00: 16 01: 32 10: 64 11: 128 Reset Value: H = 01 (32 blocks) Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) RS CONTROL REGISTER (refer to Section 4.6.6 on page 16) RS 33 F8 7 RS7 - Deinterleaver Enable 1: The input flow is deinterleaved. 0: The input flow is not affected.

6 RS6 - Synchro Enable

1: The synchro is processed. 0: The synchro word search is disabled. The bit-to-byte conversion remains in its current phase regardless of whether the synchro word is recognized or not. This allows the use of the STV0299BB with inner convolutional coding only.

5 RS5 - Reed-Solomon Enable

1: The input code is corrected. 0: No correction happens, all the data is fed to the descrambler. The error signal remains inactive.

4 RS4 - Descrambler Enable

1: The output flow from Reed-Solomon decoder is descrambled. 0: The descrambler is disactivated.

3 RS3 - Write Error Bit

1: If an uncorrectible error happens in DVB, the MSB of the first byte following the sync byte is forced to 1 after descrambling. 0: The output flow is unchanged.

2 RS2 - Block Synchro

1: The first byte of each packet is forced to Hex 47 in mode A. 0: The first byte is the one that is received. In DVB, it should be the synchro byte, complemented every 8th packet.

1 RS1 - Output Clock Polarity

1: The data and control signals are clocked during the high-to-low transition of CLK_OUT. 0: The data and control signals are clocked during the low-to-high transition of CLK_OUT.

0 RS0 - Output Clock Signal Configuration during Parity Bytes

1: D[7:0] and ERROR are null during the parity bytes. If the packet contains more than 8 errors, ERROR only remains high during the data transmission. In parallel mode, CLK_OUT remains low during the parity bytes. In serial mode, the output bit clock is always running. 0: CLK_OUT is continuous and the parity bytes are transmitted. If the packet contains more than 8 errors, ERROR remains high during the entire packet. Name HEX Address Reset Value Bit Position Signal Description

5R E G I S T E R L I S T (continued) ERROR CONTROL REGISTER (refer to Section 4.6.4 on page 16) ERRCNT 34 01 7 Error Mode 1: Error count 0: Error rate 6 This bit must be programmed to zero. [5:4] Error Source The error sources are as follows: 00: QPSK bit errors 01: Viterbi bit errors 10: Viterbi byte errors 11: Packet errors. [3:2] These bits must be programmed to zero. [1:0] NOE The NOE bits represent the Count Period in bytes (NB): 00: 2 12 bytes 01: 214 bytes 10: 216 bytes 11: 218 bytes Name HEX Address Reset Value Bit Position Signal Description

6 ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Ratings

Maximum limits indicate where permanent device damages occur. Continuous operation at these limits is not intended, and should be limited to those conditions specified in Section 6.3 ‘DC Electrical Characteristics’. Note: 1 Except for AGC, SDA, SCL, SDAT, SCLT pin, which can be connected to 5 V +10% via a resistor.

6.2 Thermal Data

Note: 2 Single-layer PCB. Note: 3 Multi-layer PCB.

6.3 DC Electrical Characteristics

VDD = 2.5 V, VDD_3.3 V = 3.3 V and Tamb =2 5°C unless otherwise specified. Symbol Parameter Value Unit VDD_3.3 V Pad Power Supply Voltage 4.0 V VDD Core Level Power Supply Voltage 3.0 V VI(1) Voltage on Input Pins -0.5, VDD_3.3 V +0 . 5 V VO (1) Voltage on Output Pins -0.5, VDD_3.3 V +0 . 5 V Tstg Storage Temperature -40, +150 °C Toper Operating Ambient Temperature -10, +70 °C Tj Junction Temperature +125 °C Symbol Parameter Max. Value Unit R th(j-a) Junction-ambient Thermal Resistance 70(4) 45(5) °C/W R th(j-c) Junction-case Thermal Resistance 11 °C/W Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD_3.3 V Operating Voltage 3.0 3.3 3.6 V VDD_core Operating Voltage 2.3 2.5 2.7 V VDDA Operating Voltage Circuit in stand-by 2.2 2.5 2.6 V VDD_STDBY Operating Voltage Circuit in stand-by 2.3 2.5 2.7 V IDD 30M Average VDD_2.5V Current VDD=2.7V = 76MHz 200 mA IDDA 30M Average V DDA Current V DD=2.6V = 76MHz 50 mA IDD 45M Average VDD_2.5V Current VDD=2.7V = 88MHz 240 mA IDDA 45M Average V DDA Current V DD=2.6V = 88MHz 50 mA IDDsb Average Current in Standby Mode VCO stopped 0.5 4 mA VIL VIH Low Level Input Voltage High Level Input Voltage 2.0 0.8 V V ILK Input Leakage Current 3.6 V 1 µA VOL VOH High Level Output Voltage Low Level Output Voltage ISOURCE =1 . 6m A 2.4 0.4 V V

6 ELECTRICAL CHARACTERISTICS (continued)

6.3 DC Electrical Characteristics (continued)

VDD = 2.5 V, VDD_3.3 V = 3.3 V and Tamb =2 5°C unless otherwise specified. Note: 1 Test conditions: Fclock = 52MHz, FIN = 8MHz, VIN = 0.5 Vpp Symbol Parameter Test Conditions Min. Typ. Max. Unit RESET VILT VIHT Low Level Threshold Falling Input High Level Threshold Falling Input 0.8 2.0 V V CLK_IN VIL VIH Low Level Input Voltage High Level Input Voltage 0.8 2.0 V V C IN Input Capacitance 3 pF AGC/SDA/SCL/SDAT/SCLT VOIL Low Level Output Voltage ISINK =2m A 0.4 V ILK Input Leakage Current V AGC =5 . 5V 4.0 µA A/D CONVERTER Vin Differential Input Voltage 0.4 0.5 0.8 Vpp VTOP High Voltage Reference 1.5 V VBOT Low Voltage Reference 1 V R in DC Input Resistance I/Q Inputs 106 ∞Ω C in Input Capacitance I/Q Inputs 5 pF INL Integral Non-Linearity -1.5 +1.5 LSB DNL Differential Non-Linearity -0.8 +0.8 LSB SNR Signal to Noise Ratio 30 33 36 dB N eff Effective Number of bits(1) 5.0 5.5 6.0 bits

6.4 Timing Characteristics

Note: 1 Tm = Master clock period in ns Figure 8: Figure 9: Figure 10: Figure 11: Symbol Parameter Min. Typ. Max. Unit fVCO Internal VCO frequency 300 400 MHz fCLK_IN CLK_IN or XTAL frequency 4 30 MHz PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). Refer to Figure 8 tCLK_duty CLK_OUT duty cycle 40 50 60 % tCKSU D[7:0], D/P , STR_OUT, ERROR stable before CLK_OUT Falling Edge 2*Tm (1) ns tCKH D[7:0], D/P , STR_OUT, ERROR stable after CLK_OUT Falling Edge 2*Tm (1) ns Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). Refer to Figure 9 tCKSU D[7:0], D/P , STR_OUT, ERROR stable before CLK_OUT Falling Edge 2*Tm (1) ns tCKH D[7:0], D/P , STR_OUT, ERROR stable after CLK_OUT Falling Edge 2*Tm (1) ns SERIAL OUTPUT D7, D/P , CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 10 tCKSU D7, D/P , STR_OUT, ERROR stable before CLK_OUT Falling Edge 3.5 ns tCKH D7, D/P , STR_OUT, ERROR stable after CLK_OUT Falling Edge 3n s Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 11 tCKSU D7, D/P , STR_OUT, ERROR stable before CLK_OUT Falling Edge 3.5 ns tCKH D7, D/P , STR_OUT, ERROR stable after CLK_OUT Falling Edge 2n s CLK_OUT D[7:0], D/P. STR_OUT, ERROR tCKHtCKSU CLK_OUT D[7:0], D/P. STR_OUT, ERROR tCKHtCKSU CLK_OUT D7, D/P. STR_OUT, ERROR tCKHtCKSU CLK_OUT D7, D/P. STR_OUT, ERROR tCKHtCKSU

6.5 I2C Bus Characteristics

Figure 12:I2C bus timing diagram Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL VIH Low Level Input Voltage High Level Input Voltage Pull up to 5 V ±10% -0.5 2.0 0.8 5.5 V V VOH VOL High Level Output Voltage Low Level Output Voltage Pull up to 5 V ±10% 5.5 0.4 V V ILK Input Leakage Current VIN = 0 V to 5 V -10 10 µA C IN Input Capacitance 0 3.5 pF IOL Output Sink Current VOL =0 . 5V 10 mA fSCLN fSCLS SCL Clock Frequency Normal Mode Standby Mode fM_CLK /40 fCLK_IN /10 tBUF Bus Free Time between a STOP and START Condition 1.3 µs tHD, STA Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 0.6 µs tLOW tHIGH Low Period of the SCL Clock High Period of the SCL Clock 1.3 0.6 µs µs tSU, ST A Setup Time for a repeated ST ART Condition 0.6 µs tSU, STO Setup Time for STOP Condition 0.6 µs tSU, DAT Data Setup Time 100 ns tR , tF Rise and Fall Time of both SDA and SCL sig- nals 300 ns C B Capacitive Load for each Bus Line 400 pF tBUF tLOW tHIGH tSP tHD,STA tFtR tSU,DAT tSU,STA tSU,STO SDA SCL tHD,STA

7 APPLICATION BLOCK DIAGRAMS

Figure 13:Application Block Diagram I Q AGC Control to PLL Synthesizer

4 MHz

4 serial or 12 parallelI2C Dual ADC

7 APPLICATION BLOCK DIAGRAMS (continued)

Typical Application Diagram 17 18 19 20 21 22 23 24 25 26 3127 28 29 30 32 64 63 62 61 60 59 58 57 56 55 5054 53 52 51 49 OLF OLF ZIF tuner or convential tuner 5V 5V 5V 30V R STV0299 22kΩ 10kΩ 2V5D 2V5D 2V5A 120 Ω 2V5A 120Ω 2V5A 2V5D Parallel DATA O/P Symbols: this symbol represents a Digital ground this symbol represents an Analog ground Requirements: The digital ground and 2.2µF 10nF 10nF 12 Ω 100 nF 10kΩ 10kΩ RESET SDA SCL LNBP 15SP 3V3 2V5D CONTROL Serial DATA O/P D7 D0 22V 22 pF 22 pF 2V5A 2V5D 2V5D 2V5D 3V3 4M H z Error D/P STR_OUT CLK_OUT Serial Clock Serial Data R 120 Ω 470Ω 100 nF 100 nF (option) 4MHz Clock 1 2x4 7Ω 47 pF 2 x 100 nF 10kΩ R ≤10K B the analog ground must be connected by only one track.

8 PACKAGE MECHANICAL DATA

64 Pins Thin Plastic Quad Flat Pack (TQFP No Slug)

A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 7.50 0.295 e 0.50 0.0197 E 12.00 0.472 E1 10.00 0.394 E3 7.50 0.295 - L1 1.00 0.039 K0 °(Min.), 7°(Max.) 64 49 17 32 e c A D EL K 0,25 mm .010 inch GAGE PLANE 0,10 mm .004 inch SEATING PLANE B

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