STD1HN60K3 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 19

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

  • 100% avalanche tested
  • Extremely high dv/dt capability
  • Gate charge minimized
  • Very low intrinsic capacitance
  • Improved diode reverse recovery characteristics
  • Zener-protected

Applications

  • Switching applications

Description

These SuperMESH3™ Power MOSFETs are the result of improvements applied to STMicroelectronics’ SuperMESH™ technology, combined with a new optimized vertical structure. These devices boast an extremely low on- resistance, superior dynamic performance and high avalanche capability, rendering them suitable for the most demanding applications. D(2, TAB) G(1) S(3) AM01476v1 DPAK IPAK TAB TAB Order codes V DS RDS(on) max ID PTOT STD1HN60K3 600 V 8 Ω 1.2 A 27 W STU1HN60K3 Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area

Table 3. Thermal data

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C o(tr) is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS
  2. C o(tr) is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS

voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. Table 6. Switching times Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

Table 8. Gate-source Zener diode

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BVDSS vs temperature Figure 7. Static drain-source on-resistance

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs Figure 11. Normalized on-resistance vs Figure 12. Source-drain diode forward Figure 13. Output capacitance stored energy

0 Qg(nC)

0 VDS(V)

Figure 14. Maximum avalanche energy vs.

3 Test circuits

Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test circuit Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Table 9. DPAK (TO-252) mechanical data

Figure 21. DPAK (TO-252) drawing

Figure 22. DPAK footprint (a)

Table 10. IPAK (TO-251) mechanical data

Figure 23. IPAK (TO-251) drawing

5 Packaging mechanical data

Table 11. DPAK (TO-252) tape and reel mechanical data

6 Revision history

Table 12. Document revision history 09-Apr-2013 1 First release.