STS14N3LLH5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 12

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

Features

■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ Very low switching gate charge ■ High avalanche ruggedness ■ Low gate drive power losses Application ■ Switching applications

Description

This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available R DS(on)*Qg, in SO-8 package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Figure 1. Internal schematic diagram

  1. The value is rated according R thj-pcb

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according R thj-pcb
  2. Pulse width limited by safe operating area

Table 3. Thermal resistance

  1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec

Table 4. Avalanche data

2 Electrical characteristics

Table 5. On/off states Table 6. Dynamic

Table 7. Switching times Table 8. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized B VDSS vs temperature Figure 7. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test Figure 17. Unclamped inductive wavefo rm Figure 18. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M 0.6 0.023 S 8 (max.) SO-8 MECHANICAL DATA

5 Revision history

Table 9. Document revision history – Document status promoted from preliminary data to datasheet.