STPTIC STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 13

Technical content

Features

  • High power capability (+36 dBm)
  • High tuning range (3.5/1)
  • High quality factor (Q)
  • High linearity device
  • Low leakage current
  • Capacitor bias is DC blocked
  • Frequency of operation from DC to 3 GHz
  • 8 values available: 1.2 pF, 2.7 pF, 3.3 pF,
  • Analog control voltage
  • Compatible with high voltage control IC (STHVDAC series)
  • Available in plastic molded package: – µQFN package 1.2 x 1.6 x 0.9 mm – Flip Chip 0.65 x 1.0 x 0.3 mm – Flip Chip 0.65 x 1.2 x 0.3 mm
  • ECOPACK®2 compliant component Benefit
  • RF tunable passive implementation in mobile phones to optimize antenna radiated performances.

Applications

  • Cellular Antenna open loop tunable matching network in multi-band GSM/WCDMA/LTE mobile phone
  • Open loop tunable RF filters

Description

The ST integrated tunable capacitor, offers excellent RF performance, low power consumption and high linearity required in adaptive RF tuning applications. The fundamental building block of PTIC is a tunable material called Parascan, which is a version of barium strontium titanate (BST) developed by Paratek microwave. BST capacitances are tunable capacitances intended for use in mobile phone application, and dedicated to RF tunable applications. These tunable capacitances are controlled through a bias voltage ranging from 2 to 20 V. The use of BST tunable capacitance in mobile phones enables significant improvement in terms of radiated performances making the performance almost insensitive to the external environment. TM: Parascan is a trade mark of Paratek microwave Inc. STPTIC STPTIC µQFN Flip Chip

1 Functional characteristics

Figure 1. PTIC functional block diagram Table 1. Signal descriptions

2 Electrical characteristics

Table 2. Absolute maximum ratings (limiting values)

  1. Currently failing around 400 V, improvement on going to withstand 500 V on 2p7 and 3p3.

Table 3. Recommended operating conditions

Table 4. Representative performances (Tamb = 25 °C)

  1. IP3 and harmonics are measured in the shunt/series configuration in a 50 Ω environment
  2. One or both of RF in and RFout must be connected to DC ground

3 Package information

  • Epoxy meets UL94, V0
  • Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 2. µQFN-6L package dimension Figure 3. Recommended PCB land pattern for µQFN-6L package

Figure 7. Recommended PCB land pattern for Flip Chip package (metal defined pads, Figure 8. Recommended PCB land pattern for Flip Chip PTIC (die size 650 x 1200)

650 X 1200 µm

4 Reflow profile

Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting Note: Minimize air convection currents in the reflow oven to avoid component movement. Table 5. Recommended values for soldering reflow

5 Ordering information

Figure 14. Ordering information scheme Table 6. Ordering information

6 Revision history

Table 7. Document revision history 02-Nov-2012 1 Initial release. 03-Jul-2013 2 Removed 6-pad 650 x 1000 Flip-Chip package. 13-Feb-2014 4 Updated Applications.