STPTIC-27L2 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Features

  • High power capability
  • 5:1 tuning range
  • Higher linearity (48x)
  • High quality factor (Q)
  • Low leakage current
  • Compatible with high voltage control IC (STHVDAC series)
  • Available in WLCSP package 0.75 x 1.00 x 0.3 mm
  • ECOPACK ® 2 compliant component Benefit
  • RF tunable passive implementation in mobile phones to optimize antenna radiated performance

Applications

  • Cellular antenna open loop tunable matching network in multi-band GSM/WCDMA/LTE mobile phone
  • Open loop tunable RF filters

Description

The ST integrated tunable capacitor offers excellent RF performance, low power consumption and high linearity required in adaptive RF tuning applications. The fundamental building block of PTIC is a tunable material called Parascan ™ , which is a version of barium strontium titanate (BST) developed by Paratek Microwave. BST capacitors are tunable capacitors intended for use in mobile phone application and dedicated to RF tunable applications. These tunable capacitors are controlled through an extended bias voltage ranging from 1 to 24 V. The implementation of BST tunable capacitors in mobile phones enables significant improvement in terms of radiated performance making the performance almost insensitive to the external environment. Figure 1. PTIC functional block diagram TM: Parascan is a trademark of Paratek Microwave Inc.

1 Electrical characteristics

Table 1. Absolute maximum ratings (limiting values)

  1. Class 1B defined as passing 500 V, but fails after exposure to 1000V ESD pulse.

Table 2. Recommended operating conditions

Table 3. Representative performance (T amb = 25 °C otherwise specified)

  1. Measured at low frequency
  2. IP3 and harmonics are measured in the shunt configuration in a 50 Ω environment
  3. One or both of RF in and RF out must be connected to DC ground, using the HVDAC turbo mode

2 Package information

  • Epoxy meets UL94, V0
  • Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

2.1 Flip-Chip package information

Figure 7. Flip-Chip package outline The land pattern below is recommended for soldering the STPTIC-G2 on PCB. Table 4. Flip-Chip package dimensions

Figure 8. Recommended PCB land pattern for Flip-Chip package

2.2 Packing information

Figure 9. Flip-Chip tape and reel outline Table 5. Dimensions Table 6. Dimensions

Figure 10. Flip-Chip marking Table 7. Pinout description

  1. When connected in shunt, please connect RF2 (B1 ball) to GND

3 Reflow profile

Figure 11. ST ECOPACK ® recommended soldering reflow profile for PCB mounting Note: Minimize air convection currents in the reflow oven to avoid component movement. Table 8. Recommended values for soldering reflow

4 Ordering information

Figure 12. Ordering information scheme

5 Revision history

Table 9. Ordering information Table 10. Document revision history 04-Dec-2015 1 Initial release.