STPMC1

Programmable poly-phase energy calculator IC

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 77

Technical content

Datasheet sections

• 1 Functional block diagram
• 2 Pin configuration
• 3 Maximum ratings
• 4 Functions
• 5 Application
• 6 Electrical characteristics
• 7 Terminology
• 7.1 Measurement error
• 7.2 Conventions
• 7.3 Notation
• 8 Typical performance characteristics
• 9 Theory of operation
• 9.1 General operation
• 9.2 Power supply
• 9.3 Resetting the STPMC1 (status bit HLT)
• 9.4 Clock generator (bits MDIV , FR1, HSA)
• 9.5 Zero crossing detection (signal ZCR)
• 9.6 Period and line voltage measurement (status bits: LIN, BFR, LOW, BFF)
• 9.7 Single wire operation mode: SWM (status bits: NAH, BFR,
• 9.8 Load monitoring (status bit BIL, configuration bit LTCH)
• 9.9 Error detection (status bits: BCF , PIN)
• 9.10 T amper detection module (status bits: BCS, BSF , BIF ,
• 9.10.1 Sum of currents is above tamper threshold (status bit BCS)
• 9.10.2 Phase sequence is wrong (status bit BSF)
• 9.10.3 Phase active powers do not have the same sign (status bit BIF)

Datasheet sections

• 10.4 Energy integration
• 10.5 Fundamental power calculation
• 11 Package mechanical data
• 12 Revision history

Features

■ Supports 1-, 2- or 3-phase WYE and Delta services, from 2 to 4 wires ■ Computes cumulative active and reactive wide- band and fundamental harmonic energies ■ Computes active and reactive energies, RMS and momentary voltage and current values for each phase ■ Supports Rogowski coil, current transformer, Shunt or Hall current sensors ■ Exclusive ripple-free energy calculation algorithm ■ Programmable pulsed output ■ Stepper motor outputs ■ Neutral current, temperature, and magnetic field monitoring ■ OTP memory for configuration and calibration ■ SPI interface ■ Supports IEC 62052-11 / 62053-21 / 62053-23 standards ■ Less than 0.1 % error over 1:1000 dynamic range

Applications

■ Power metering

Description

The STPMC1 device functions as an energy calculator and is an ASSP designed for effective energy measurement in power line systems utilizing Rogowski, current transformer, Shunt or Hall current sensors. Used in combination with one or more STPMSx ICs, it implements all the functions needed in a 1-, 2- or 3-phase energy meter. It can be coupled with a microprocessor for multi-function energy meters, or it can directly drive a stepper motor for a simple active energy meter. The calculator has five input data pins. The first three receive the voltage and current information of the phases. In fact, each data input processes two ΔΣ signals, multiplexed in time and generated by the STPMSx device. The fourth input receives multiplexed ΔΣ signals also, and can be used to sense the neutral current or another signal - temperature, for example. The fifth input data pin accepts non-multiplexed ΔΣ signals and it can be used for sensing the magnetic field information from a Hall sensor. Four internal hard-wired DSP (digital signal processing) units perform all the computations on the ΔΣ streams in real time by means of ΔΣ arithmetic blocks. This allows the achievement of very high computation precision with fast and efficient digital architecture. All the data recorded by the STPMC1 are accessible through an SPI port, which is also used to configure and calibrate the device. The configuration and calibration data can be saved in a 112-bit OTP block, or dynamically set in microprocessor-based meters. TSSOP20 Table 1. Device summary

9.11 Energy to frequency conversion (configuration bits: APL, KMOT,

9.12 Using STPMC1 in microcontroller based meter - peripheral

9.13 Driving a stepper motor - standalone operating mode

9.14 Negative power accumulation (configuration bit ABS, status bit SIGN) . . 36 9.16 Calibration (configuration bits: PM, TCS, CIX, CVX, CCA, CCB, CPX) . . 39

Table 16. Pin description versus SYS configuration (uX and iX represent the voltage Table 23. f

1 Functional block diagram

Note: DAx stands for DAR, DAS, DAT, and xDSP stands for RDSP , SDSP , TDSP . Figure 1. STPMC1 device block diagram

112 OTP

2 Pin configuration

Figure 2. Pin connections (top view) Table 2. Pin description

1 MON D / P O Programmable output pin, see Ta bl e 5

2 MOP D / P O Programmable output pin, see Ta bl e 5

3 SCS D I Digital input pin, see Table 5

8 DAH D I Input for non-multiplexed ΔΣ signals

9 DAR D I Input for multiplexed ΔΣ R-phase signals

10 DAS D I Input for multiplexed ΔΣ S-phase signals

11 DAT D I Input for multiplexed ΔΣ T -phase signals

12 DAN D I Input for multiplexed ΔΣ PTAT and neutral signal

13 CLK D O 2 mA clock output for STPMSx devices

14 V SSA A GND Ground level of core

15 SYN D I/O Programmable input/output pin, see Table 5

16 XTAL2 A Crystal oscillator pin

17 XTAL1 A Crystal oscillator pin

18 SCLNLC D I/O Programmable input/output pin, see

19 SDATD D I/O Programmable input/output pin, see Table 5

20 LED D O Programmable output pin, see Ta bl e 5

1. A: Analog, D: Digital, P: Power, I: Input, O: Output, GND: Ground

3 Maximum ratings

Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 3. Absolute maximum ratings Table 4. Thermal data

1. This value refers to single-layer PCB, JEDEC standard test board.

4 Functions

Table 5. Programmable pin functions

5 Application

Figure 3. Application schematic in standalone operating mode Figure 4. Application schematic using an MCU

operation is not limited to the choice of these external components. Table 6. Typical external components

6 Electrical characteristics

unless otherwise specified). Table 7. Electrical characteristics

Note: Typical value, not production tested. Table 7. Electrical characteristics (continued)

7 Terminology

7.1 Measurement error

The error associated with the energy measured by the STPMC1 is defined as:

7.2 Conventions

The lowest analog and digital power supply voltage is called VSS which represents the system ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. “Sinking current” is the current flowing into the pin, and so it is positive. “Sourcing current” is the current flowing out of the pin, and so it is negative. Signal timing specifications treated by a digital control part are relative to XTAL1. This signal is provided from the crystal oscillator or from an external source as specified in paragraph 9.4. Signal timing specifications of the SPI interface are relative to the SCLNLC. There is no direct relationship between the clock (SCLNLC) of the SPI interface and the clock of the DSP block (XTAL1). A positive logic convention is used in all equations. EnergyTrue EnergyTrue)reading(1SPMCErrorPercentage −=

7.3 Notation

Table 8. Notation

8 Typical performance characteristics

Figure 5. Supply current vs. supply voltage, T A = 25°C (fXTAL1 = 4.194 MHz, fXTAL1 = 8.192 MHz) Figure 6. Digital voltage regulator: line - load regulation. ( fXTAL1 = 0; 100 nF across VCC and VSS;

Figure 7. Gain response of decimator

9 Theory of operation

9.1 General operation

microprocessor based 1-, 2- or 3-phase energy meter.

• The analog section is composed of a band-gap voltage reference and a low-drop voltage regulator.
• The digital section consists of a system control, clock generator, three PDSP and a NDSP , a SPI interface.
• The 112-bit OTP block and the 16 system signals, used for testing, configuration and calibration purposes, are controlled through SPI by means of a dedicated command set. The calculator has five input data pins, of which four are fed by signals generated by the STPMSx, see Ta bl e 9. Three of them (DAR/DAS/DAT) are used to receive multiplexed signals of voltage and current, implementing energy measurement in 1-, 2- and 3-phase (3 and 4 wires) systems. After being de-multiplexed, each phase input is sent to the correspondent DSP unit that processes voltage and current information and performs energy calculation, according to the settings of the configuration bits (see Table 33). The DAN input, which also receives a multiplexed signal output from STPMSx device, is typically used to monitor neutral current for anti tampering functions in 1-, 2- and 3-phase (4 wires) systems. Normally the STPMSx monitors current and voltage but in case of neutral monitoring the voltage channel can be connected to a different type of sensor, for example a temperature sensor. The fifth input data pin (DAH) accepts non-multiplexed ΔΣ signals. It can be used for EMI sensing through Hall sensors or for temperature sensing. The companion chip (STPMSx) embeds 2 ΔΣ ADC converters and the necessary logic capable of providing the multiplexed ΔΣ streams. See the STPMSx documentation for more details.

Table 9. Input channels from the STPMSx

Theory of operation STPMC1 20/77 Doc ID 15728 Rev 7 These four multiplexed signals are separated, by a digital de-multiplexer, back into eight ΔΣ signals, called streams. The signal coming from the voltage channel of the STPMSx is named with the suffix V, while the stream coming from the current channel is named with the suffix C. For example, the voltage stream of the S-phase is named DAS-V. Then, each pair of phase the voltage and current stream coming from DAR, DAS and DAT is connected to a dual-channel RDSP , SDSP , TDSP unit (i.e. DAR-V and DAR-C are connected to RDSP). Each phase voltage input stream is proportional to phase voltage u. Each phase current input stream is proportional to derivation of phase current di/dt, when it originates from Rogowski coil, or to phase current i, when it originates from Shunt or CT or Hall sensor. In this case a derivative is inserted into the voltage channel to get a stream proportional to du/dt. The sensors differ from each other for sensitivity, phase error and susceptibility to external EM fields. Each of these DSP units performs the following:

• checks the integrity of the streams
• calibrates streams
• filters both streams with a dedicated decimation filter
• computes active and reactive energies, momentary and RMS values for voltage and current, period of power line voltage signal. In each DSP there are calibrators capable of adjusting the readings ±12.5%. The power computer does the final calculations of the value and direction of the power and checks for no-load condition. Another dual DSP unit, called NDSP , processes the streams coming from DAN and DAH. In fact, using the ENH bit (see Table 33), the user can select either the voltage stream of the DAN pin (DAN-V) or the DAH stream as the input of the NDSP unit, while the current stream DAN-C is always processed as neutral current. In its voltage channel, the NDSP unit uses a 2 s time multiplex to process two streams. During the first half of the interval the voltage input stream is processed (which can be DAN- V or DAH, according to the ENH bit), while during the second half a stream constituted by the sum of all four calibrated currents (i.e. DAR-C + DAS-C + DAT-C + DAN-C). In its current channel the NDSP unit process the current stream of the neutral conductor as follows:
• checks the integrity of stream
• calibrates the stream
• filters the stream with a dedicated decimation filter
• computes momentary and RMS values of the stream
• if no errors have been detected in the phase timing, computes phase frequency, integrates the phase powers by means of 3-input integrators of energies and generates all pulse output signals. When the DAH input stream is selected, it is checked to detect an external magnetic influence (EMI) to the meter.

STPMC1 Theory of operation Doc ID 15728 Rev 7 21/77 The calculator, thanks to its flexibility, can work in all worldwide distribution network standards. By programming the SYS OTP bits, it is possible to implement the following systems:

• 3-phase, 4-wire RSTN, 4-system RSTN (tamper);
• 3-phase, 4-wire RSTN, 3-system RST;
• 3-phase, 3-wire RST_, 3-system RST_ (tamper);
• 3-phase, 3-wire RST_, 2-system R_T_ (Aron);
• 2-phase, 3-wire _STN, 2-system _ST_ (America);
• 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:coil);
• 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:shunt);
• 1-phase, 2-wire __TN, 1-system __T_. The results of all DSP units are available as pulse frequency on pin LED, MOP and MON, which can also drive a stepper counter, and as states on the digital outputs of device or as data bits in data records, which can be read from the device by means of SPI interface from pins SDA, SNC, SCL and SYN. This system bus interface is also used during temporary or permanent programming OTP bits and system signals or to execute a remote reset request. A logic block common to all DSP units performs other operations like:
• selecting the valid phase period result from which line frequency is computed in NDSP unit
• checking the equality of phase angles between all three phase voltages
• preparing current values for compensation of external intermediate phase magnetic influences
• checking the sum of currents
• computing intermediate phase voltages
• combining the 3-phase status bits
• performing a watchdog user function After the device is fully tested, configured and calibrated, a dedicated bit of the OTP block, called TSTD, can be written permanently in order to prevent the change of any configuration bit.

9.2 Power supply

The supply pins for the analog part are VCC and VSS. The VCC is the power input of the 1.8 V low drop regulator, band-gap reference and bias generators. From the VCC pin a linear regulator generates the +1.8 V voltage supply level (VDD) which is used to power the OTP module and digital core. The VSS pin represents the reference point for all the internal signals. 100 nF low ESR capacitors should be connected between VCC and VSS, and 1 µF between VDD and VSSA. All these capacitors must be placed very close to the device. The STPMC1 contains a power on reset (POR) detection circuit. If the VCC supply is less than 2.5 V then the STPMC1 goes into an inactive state, all the functions are blocked asserting a reset condition. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which gives a high degree of immunity from false triggering due to noisy supplies. A bandgap voltage reference (VBG) of 1.23 V ±1% is used as a reference voltage level

voltages for all other analog modules and for the OTP module.

9.3 Resetting the STPMC1 (status bit HLT)

board microprocessors when a malfunction of the device is detected. description of the mode signals) are not cleared. performed through SPI, no delayed turn-on is generated. device register are not valid.

9.4 Clock generator (bits MDIV , FR1, HSA)

• Quartz: the oscillator works with an external crystal.
• External clock: the clock is provided by an external source connected to XTAL1. The suggested circuits are depicted in Figure 8.

Figure 8. Connections of oscillator: (a) quartz, (b) external source The clock generator is responsible for two tasks.

ms after a power on reset (see Section 9.3). The second task of the clock generator is to provide all necessary clocks for the digital part. nominal frequency value from XTAL1 (fXTAL1). The internal master clock fMCLK is derived from fXT AL1 as shown in Table 10. the STPMSx devices, can be derived as reported in Table 11. To properly work with STPMS2, the clock configurations in Table 12 must be used. Moreover, with STPMS2 companion chip the PM bit must always be set.

9.5 Zero crossing detection (signal ZCR)

Table 10. Frequency settings through MDIV and FR1 (1)

1. 4 MHz and 8 MHz clock are also supported. MDIV and FR1 have to be set as for 4.194 MHz and 8.192

Table 11. CLK pin frequency settings through HSA Table 12. STPMC1 configuration for STPMS2

as a peripheral with the configuration bit APL=0.

9.6 Period and line voltage measurement (status bits: LIN, BFR,

the sign of dv/dt. With further elaboration, the ZCR signal is also produced. and it is used to reset the period meter. the 8-bit status byte of each phase (see Table 32). Figure 9. ZCR signal Table 13. Good frequency ranges for different clock source values

must be repeated three times, in order to set the error flag BFR, as shown in Figure 10. X in case of non Rogowski current sensor. the presence of the line voltage. they are held low if BFR is set. The 3-ph status bit BFF is the OR of each phase bit BFR.

9.7 Single wire operation mode: SWM (status bits: NAH, BFR,

Figure 10. LIN and BFR behavior when fline > fMCLK/216

Theory of operation STPMC1 26/77 Doc ID 15728 Rev 7 Each ACx register contains a 20-bit accumulator of the relative phase current IX [Ah] and an 8-bit register carrying the information about phase delay between voltage channels. The SWM mode is indicated by status bit NAH =0:

• Bit NAH=0 (SWM on) happens when BFR=1 and RMS value of current signal is IX > IXmax/4096 = 16 (IXmax = 216). In this case frequency is out of limits and RMS current IX is big enough, so it is accumulated in the corresponding ACx phase register.
• Bit NAH=1 (SWM off) happens if BFR=1 and RMS value of current signal is IX < IXmax/8192 = 8, or BFR=0. In this case either voltage frequency is out of limits but RMS current IX is too small to enter SWM mode, or voltage frequency is in the correct range. When bit BFR is set, for a certain phase, its energy registers (active, reactive, fundamental) are blocked. Then, if RMS value of current signal is big enough, bit NAH is cleared (0) and a SWM operation is entered. In this case the RMS value of current signal is accumulated in ACx register and the value of voltage RMS U X is set to zero. Example 1: Single wire operation with SYS = 0 SYS = 0 (3-phase system) is set and in the R-phase the voltage signal is too low (status bits of phase R BFR = 1 and LOW = 1). Because of the too low voltage signal the frequency can't be calculated and energy registers related to the R-phase are blocked. If RMS value of current signal is big enough, the device enters SWM and clears NAH of R phase. The ACR register is incremented by adding IR, the RMS value of current signal. Example 2: Single wire operation with SYS = 0 and TCS = 1 SYS = 0 (3-phase system) and TCS = 1 (CT sensor selection) are set and in all phases (R, S and T) the voltage signal is too low (status bits BFR = 1 and LOW = 1 for all phases). Because of the too low voltage signal the frequency could not be calculated and all energy registers are blocked. Since when TCS = 1, a frequency value is needed to calculate the RMS value of the current signal, the default value of 50 Hz or 60 Hz (if bit FRS=1) is taken. If the RMS value of current signal is big enough, the device enters SWM and clears NAH of all phases and ACR, ACS and ACT registers is fed with the correspondent IX. The accumulators ACx can be read by means of SPI. To retrieve energy information, RMS value of current signal accumulated in registers ACx can be multiplied by a constant representing the value of RMS voltage. This operation must be executed by a microcontroller. Usually the supply voltage for the electronic meter is taken from the line voltage. In SWM, since the line voltage is not present anymore, some other power source must be used in order to provide the necessary supply to STPMC1 and the other electronic components of the meter.

9.8 Load monitoring (status bit BIL, configuration bit LTCH)

The STPMC1 includes in each phase a no-load condition detection circuit with adjustable threshold. This circuit monitors the voltage and the current channels and, when the measured voltage is below the set threshold, an internal signal BIL becomes high. The

The three phase status bit BIL is the AND of each phase status bit BIL. threshold values can be chosen according to the two LTCH bits as reported in Table 14. signal can be accessed through the SPI interface. output frequency, where FS internal AW frequency is 1370 Hz per phase. An energy meter has a power constant of C = 64000 pulses/kWh on LED pin. LED pin if P power is applied to the meter. is half lower than that described above.

9.9 Error detection (status bits: BCF, PIN)

• the ΔΣ signals
• the state of output pins The first error detection circuit checks if any of the ΔΣ signals from the analog part is stuck at 1 or 0 within the period of observation (250 µs). In case of detected error the corresponding ΔΣ signal is replaced with an idle ΔΣ signal, which represents a constant value 0. When this

Table 14. No-load detection thresholds

Theory of operation STPMC1 28/77 Doc ID 15728 Rev 7 error occurs the correspondent phase bit BCF is set. When the ΔΣ signal becomes correct again the BCF flag is cleared immediately. The 3-ph status bit BCF is the OR of each phase bit BFC, but it takes into account also the connection of the neutral wire (DAN-I stream). The other error condition occurs if the MOP , MON and LED pin outputs signals are different from the internal signals that drive them. This can occur if some of this pin is forced to GND or to some other imposed voltage value. In this case the internal status bit PIN is immediately activated providing the information that some hardware problem has been detected, for example the stepper motor has been mechanically blocked. These two error condition don't influence energy accumulation.

9.10 Tamper detection module (status bits: BCS, BSF, BIF,

configuration bit ENH) The tamper detection module is used to prevent theft of energy through improper connection of the meter. The tamper indicator is activated when:

• sum of currents is above tamper threshold (status bit BCS = 1),
• phase sequence is wrong (status bit BSF = 1),
• phase active powers don't have the same sign (status bit BIF = 1),
• electromagnetic interference (EMI) is detected (only with ENH = 1). In standalone application mode (APL [1] = 1) the SDATD pin is used to notify the tamper condition. In 3-phase system (SYS = 0, 1, 2) this output is set if at least one of the internal status bits: BCS, BSF, BIF has been set or if EMI has been detected. In other systems (SYS ≠ 0, 1, 2) it indicates only BCS or EMI. Example 4: Tamper output on SDATD pin SYS = 0, 1 or 2 and APL [1] = 1: BCS = 0, BSF = 0, BIF = 0 → Tamper (SDATD pin) = 0 BCS = 0, BSF = 1, BIF = 1 → Tamper (SDATD pin) = 1 SYS = 0, 1 or 2, APL [1] = 1 and ENH = 1: BCS = 0, BSF = 0, BIF = 0, EMI = 0 → Tamper (SDATD pin) = 0 BCS = 0, BSF = 0, BIF = 0, EMI = 1 → Tamper (SDATD pin) = 1 BCS = 1, BSF = 1, BIF = 1, EMI = 1 → Tamper (SDATD pin) = 1 In peripheral application mode these information can be read out by SPI interface checking the 3-ph status bits, or the status bits corresponding to each phase.

9.10.1 Sum of currents is abov e tamper threshold (status bit BCS)

Tamper detection through bit BCS is meaningful only for SYS = 0, 2, 5, 6 (systems with neutral wire). In other measurement systems it is not useful because there are not enough input current streams. The STPMC1 check tamper detection only if

there is a tamper condition. into register DMN (see paragraph 9.17.2). This value should always be zero (or very close). Table 15. Tamper conditions

IMAX (the threshold corresponds to about 0.4% of IMAX). which means the sIRMS value must not exceed 3.13% of (IR + IS +IT +IN). Figure 11. Currents of the three phase system in example

STPMC1 Theory of operation Doc ID 15728 Rev 7 31/77 Example 6: 3-ph system - BCS = 1 Let us consider a three-phase, four wires system where: IR = 5 A IS = 5 A IT = 3.2 A IN = 0 A The tamper is evaluated because I R + IS +IT +IN = 13.2 A > 0,703125 A = IMAX / 256 In this case sIRMS = 0,449901 A > 0,4125 A = (I R + IS +IT +IN) / 32 Then BCS = 1. Example 7: 1-ph system - BCS = 0 Let us consider a single phase systems with only S and T wires connected where I S= 5 A IT = 4 A IMAX = 180 A In this case the criterion for tamper evaluation is verified since: S + IT) = 9 A > 0,703125 A = IMAX / 256 But BCS = 0 because 7/9 I T = 3.11 A < IS = 5 A < 9/7 IT = 5.14 A and 7/9 I S = 3.88 A < IT = 4 A < 9/7 IS = 6.43 A Example 8: 1-ph system - BCS = 1 Let us consider the case in which: I S = 5 A IT = 3 A IMAX = 180 A Also in this case the criterion for tamper evaluation is verified: S + IT) = 8 A > 0,703125 A = IMAX / 256 Now BCS = 1 because 7/9 I S = 3.88 A > IT = 3 A

9.10.2 Phase sequence is wrong (status bit BSF)

One tamper condition is that phase sequence is not correct. A 3-ph phase status bit BSF checks the sequence of phases, which, in a three phase system is one of the following:

• R → S → T
• S → T → R
• T → R → S In one of the above cases BSF is cleared, otherwise bit BSF is set.

three phase voltage signals (uR, uS, uT) are available and can be checked, as shown in 0.

9.10.3 Phase active powers do not have the same sign (status bit BIF)

equal in all three phases (R, S and T), then bit BIF is set.

9.10.4 EMI is detected

standalone application mode).

• its DC component does not exceed DCMAX/16
• its RMS value does not exceed the maximum value RMSMAX/16 where DCMAX = RMSMAX = 216 with hysteresis. If these condition are not verified the EMI tamper is detected.

Table 16. Pin description versus SYS configuration (uX and iX represent the voltage and the

other tamper conditions) on the SDATD pin of the device. 16-bit DCuN and of the 12-bit RMSuN to the threshold through a microcontroller.

9.11 Energy to frequency conversion (configuration bits: APL ,

harmonic) are connected to the corresponding integrators. be brought out to the LED pin. calibration time of the meter. as shown in paragraphs 9.12 and 9.13. Table 17. Energy registers LSB value

Theory of operation STPMC1 34/77 Doc ID 15728 Rev 7 Example 10: energy registers LSB value for SYS = 0, 1, 2, 4, 5, 6, 7 C = 64000 pulses/kWh = 17.7 Hz*kW KP = KF = 15.258 *10-6 Wh KQ = KR = 15.258 *10-6 VArh This means that the reading of 0x00001 in the active energy register represents 15.258 µWh, while 0xFFFFF represents 16 Wh. Example 11: Energy registers LSB value for SYS = 3 C = 64000 pulses/kWh = 17.7 Hz*kW KP = 15.258 *10-6 Wh KF = 30.517 *10-6 Wh KQ = KR = 30.517 *10-6 VArh From 3-phase active energy wide band signal the stepper driving signals MA and MB (output from MOP and MON pins) are generated. The frequency of these signals can be configured as shown in paragraph 9.13. operating mode (configuration bits: APL, KMOT, LVS, FUND) The higher flexibility of the STPMC1 allows its use in microcontroller based energy meters. In this case the STPMC1 must be programmed to work in peripheral mode setting bit APL [1] = 0. All the SPI pins (SCS, SCLNCL, SDATD, SYN) are used only for communication purposes, allowing the microcontroller to write and read the internal STPMC1 registers. The peripheral mode has two further different configuration modes according to the status of the APL configuration bit, which changes the function of MOP , MON and LED pins as described below. APL = 0: In the MOP pin, the ZCR signal is available (see paragraph 9.5 for details on ZCR signal); The pin MON provides the WatchDOG signal. The DOG signal generates a 16 ms long positive pulse every 1.6 seconds. Generation of these pulses can be suspended if data are read in intervals shorter than 1.6 ms. The DOG signal is actually a watchdog reset signal that can be used to control an operation of an on-board microcontroller. It is set to high whenever the V CC voltage is below 2.5 V, but after VCC goes above 2.5 V this signal starts to run. It is expected that an application microcontroller should access the data in the metering device on regular basis, at least 1/s (recommended is 32/s). Every latching of results in the metering device requested from the microcontroller also resets the watchdog. If latching requests does not follow each other within 1.6 second, an active high pulse on MON is produced, because device assumes that microcontroller does not operate properly. This signal can be either control the RESET pin of the microcontroller or it can be tied to some interrupt pin. The second chance is recommended for a battery backup application which can enter some sleep mode due to power down condition and should not be reset by metering device. The LED pin can be configured through LVS , FUND and KMOT to output different energy signals, as shown in the table below.

Table 18. LED pin configuration for APL = 0

1. C is the number of pulses per kWh set with calibration.

Table 19. LED pin configuration for APL = 1

pulses on LED pin (C, see par. 9.11) following the table below. The mono-flop limits the length of the pulses according to the LVS bit value. them has only a half of selected frequency. integration of power is suspended. Figure 12. Stepper driving signals Table 20. Configuration of MOP and MON driving signals with APL = 1, 2, 3

1 C/128

3 C/256

1 C/1280

2 C/320

3 C/2560

9.14 Negative power accumulation (configuration bit ABS , status

power P and fundamental active power F . status bits SIGNX depends upon phase X power direction.

9.15 Phase delay calculation

line is 50 Hz, a 120° phase delay corresponds to 6.7 ms. Table 21. LED pin configuration for APL = 2, 3 Table 22. Accumulation mode for negative power

1 Absolute accumulation per

2 Ferraris mode per phase if PX < 0 → PX = 0

3 Signed accumulation P Σ = PR + PS + PT PΣ < 0 → SIGN = 0

needed for this calculation. Figure 13. Phase delay

STPMC1 Theory of operation Doc ID 15728 Rev 7 39/77 Example 12: Phase delay calculation fXTAL1 = 4 MHz; MDIV = 0; FR1 = 0 → fMCLK = 8 MHz fLINE = 50 Hz → T = 20 ms; ACR[7:0] = 0101 1010 ACS[7:0] = 0010 0000 ACT[7:0] = 0000 0101 Asr[12] = 0 Asr[10:0] = 000 0101 0010 2 = 82 Art[12] = 0 Art[10:0] = 00001011010 2 = 90 Example 13: Phase delay calculation fXTAL1 = 4 MHz; MDIV = 0; FR1 = 0 → fMCLK = 8 MHz fLINE = 50 Hz → T = 20 ms; ACR[7:0] = 1011 0011 ACS[7:0] = 0011 1111 ACT[7:0] = 0000 0101 Asr[12] = 0 Asr[10:0] = 000 0101 0011 2 = 83 Art[12] = 1 Art[10:0] = 111 1011 0011 2 = 1971 [] () [] () °+=°⋅μ⇒ μ+= ⋅⎟⎠ ⎞⎜⎝ ⎞⎜⎝ ⎛ +−= 5,1360ms20 s82 s82 108 81200000101001MCLK 8120:10Asrtime 6 011 12Asr11 Asr [] () [] () °+=°⋅μ⇒ μ+= ⋅⎟⎠ ⎞⎜⎝ ⎞⎜⎝ ⎛ +−= 6,1360ms20 s90 s90 108 81200000101101MCLK 8120:10Arttime 6 011 12Art11 Art [] () [] () °+=°⋅μ⇒ μ+= ⋅⎟⎠ ⎞⎜⎝ ⎞⎜⎝ ⎛ +−= 5,1360ms20 s83 s83 108 81210000101001MCLK 8120:10Asrtime 6 011 12Asr11 Asr [] () [] () °−=°⋅μ−⇒ μ−= ⋅⎟⎠ ⎞⎜⎝ ⎞⎜⎝ ⎛ +−= 4,1360ms20 s76 s76 108 81211111011001MCLK 8120:10Arttime 6 111 12Art11 Art

Theory of operation STPMC1 40/77 Doc ID 15728 Rev 7

9.16 Calibration (configuration bits: PM , TCS, CIX, CVX, CCA,

CCB, CPX)

9.16.1 Voltage and current channels calibration

The 8-bit calibration values CVX and CIX (where X stands for N, R, S or T) are used as static data for the channel ΔΣ calibrators, multiplying their streams to the following factor: When configuration bit PM is set, a 2-bit CvX or CiX is appended to each CVX or CIX respectively: CvX bits are part of the CCA configuration byte while CiX are part of CCB configuration byte.

9.16.2 Phase compensation

The STPMC1 does not introduce any phase shift between voltage and current channel. However, the voltage and current signals come from transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The STPMC1 provides a means of digitally calibrating these small phase errors introducing some delay. The amount of phase compensation can be set per each phase using the 4 bits of the phase calibration configurators (CPR , CPS, CPT). A vector method of phase shift compensation is implemented. The compensating voltage vector, which is produced from a frequency compensated signal of integrated voltage vector multiplied by a given compensation constant per each phase and is almost perpendicular to the input voltage vector, is subtracted from the input voltage vector at the input of the decimation filter. Those phase compensators are merged from a common coarse part CPC and from each phase 4-bit phase error compensator CPX: CPC[1] = 0: KPHC = - (16 CPC[0] + CPX) CPC[1] = 1: KPHC = (16 - CPX) When either PM or TCS are set, a 2-bit CpC is appended to CPC to produce the following factor: CPC[1] = 0: KPHC = - (32 CpC + 16 CPC[0] + CPX) CPC[1] = 1: KPHC = [64 - (32 CpC + 16 CPC[0] + CPX)] CpC bits are part of the CCA configuration byte. The equation for phase compensation in degree is:

fphc is the clock for phase compensation. Table 23. f phc frequency settings Table 24. f phc frequency values

4.194 MHz

4.195 MHz 614 kHz

1.049 MHz

2.097 MHz

Table 25. f phc frequency settings for PM = 1

Table 26. Phase compensation for PM = 0, TCS = 0, fline = 50 Hz

Table 27. Phase compensation for PM = 0, TCS = 1, fline = 50 Hz

9.16.3 Mutual current compensation

Mutual current compensation is available only when TCS is clear (Rogowski coil). influence compensation according to SYS value. Table 28. Phase compensation for PM = 1, fline = 50 Hz

together and subtracting them from the currents. Table 29. Mutual current compensation matrix for single-phase systems (SYS > 3) Table 30. Mutual current compensation matrix for three-phase systems (SYS < 4)

9.17 Data records map

(see paragraph 9.17.8) and 28-bit data field. sequence of reading, and the name and assembly of data records.

9.17.1 Group 0 data records

0.1 DAP:

• 3- phase active energy wide band: 20-bit accumulator of 3-ph active energy wide band (see paragraph 9.11)
• 3-ph lower status: bits [0:7] of 3-phase status (see Table 31)

0.2 DRP:

• 3- phase reactive energy: 20-bit accumulator of 3-ph reactive energy (see paragraph 9.11)
• 3-ph up status: bits [8:11] of 3-phase status (see Table 31)
• TSG bits: 4 TSG mode signal (see paragraph 9.20)

0.3 DFP:

• 3-phase active energy fundamental: 20-bit accumulator of 3-ph active energy from fundamental harmonic (see paragraph 9.11)
• system signals: commands BANK-PUMP-TST0-TST1-TST2-RD-WE-precharge (see paragraph 9.20)

Figure 14. Group 0 data records

0.4 PRD:

• period: 12-bit line period measurement (see paragraph 9.6). By default it is calculated from R-phase signal, if it is missing from S-phase then from T-phase. The value of the period can be calculated from the decimal value of period as: Equation 10
• DC uN: 16-bit DC component of voltage channel of NDSP . It may be DAN-V or DAH according to the value of ENH bit. For example it is DC offset in sigma delta uN if ENH=0, or DC value of magnetic field if ENH is set and a magnetic sensor is connected via STPMSx on DAH input.

9.17.2 Group 1 data records

1.1 DMR:

• uR MOM: 12-bit momentary value of R phase voltage
• iR MOM: 16-bit momentary value of R phase current

1.2 DMS:

• uS MOM: 12-bit momentary value of S phase voltage
• iS MOM: 16-bit momentary value of S phase current

1.3 DMT:

• uT MOM: 12-bit momentary value of T phase voltage
• iT MOM: 16-bit momentary value of T phase current

1.4 DMN:

• sI RMS: 12-bit RMS value of the sum of all the instantaneous currents (iR + iS + iT + iN) divided by four: MCLK f 2periodT ⋅=

Figure 15. Group 1 data records

• iN MOM: 16-bit momentary value of neutral current Note: In systems 3-phase, no neutral, u ST, uTR, uRS replace uR, uS, uT respectively.

9.17.3 Group 2 data records

2.1 DER:

• uR RMS: 12-bit RMS value of R phase voltage
• iR RMS: 16-bit RMS value of R phase current

2.2 DES:

• uS RMS: 12-bit RMS value of S phase voltage
• iS RMS: 16-bit RMS value of S phase current

2.3 DET:

• uT RMS: 12-bit RMS value of T phase voltage
• iT RMS: 16-bit RMS value of T phase current

2.4 DEN:

• uN RMS: 12-bit RMS value of voltage channel of NDSP . It may be DAN-V or DAH according to the value of ENH bit.
• iN RMS: 16-bit RMS value of neutral current Note: In systems 3-phase, no neutral, U ST, UTR, URS replace UR, US, UT respectively. RMS X isIRMS ⎟ ⎛= ∑

Figure 16. Group 2 data records

9.17.4 Group 3 data records

3.1 DAR:

• R-phase active energy wide band: 20-bit accumulator of R phase active energy wide band
• R-phase status: 8-bit R phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase R active energy wide band.

3.2 DAS:

• S-phase active energy wide band: 20-bit accumulator of S phase active energy wide band
• S-phase status: 8-bit S phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase S active energy wide band.

3.3 DAT:

• phase active energy wide band: 20-bit accumulator of T phase active energy wide band
• T-phase status: 8-bit T phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase T active energy wide band.

3.4 CF0:

• bits [27..0] of configurators (see Table 33).

Figure 17. Group 3 data records

9.17.5 Group 4 data records

4.1 DRR:

• R-phase reactive energy: 20-bit accumulator of R phase reactive energy.
• R-phase status: 8-bit R phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase R reactive energy.

4.2 DRS:

• S-phase reactive energy wide band: 20-bit accumulator of S phase reactive energy
• S-phase status: 8-bit S phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase S reactive energy.

4.3 DRT:

• T-phase reactive energy wide band: 20-bit accumulator of T phase reactive energy
• T-phase status: 8-bit T phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase T reactive energy.

4.4 CF1:

• bits [55..28] of configurators (see Table 33) Note: When the configuration bit FUND is set, fundamental reactive energy replaces full bandwidth reactive energy.

Figure 18. Group 4 data records

9.17.6 Group 5 data records

5.1 DFR:

• R-phase active energy fundamental: 20-bit accumulator of R phase active energy from fundamental harmonic
• R-phase status: 8-bit R phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase R active energy fundamental.

5.2 DFS:

• S-phase active energy fundamental: 20-bit accumulator of S phase active energy from fundamental harmonic
• S-phase status: 8-bit S phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase S active energy fundamental.

5.3 DFT:

• T-phase active energy fundamental: 20-bit accumulator of T phase active energy from fundamental harmonic
• T-phase status: 8-bit T phase status (see Table 32). Bit [0] (BIL) represents no-load condition for phase T active energy fundamental.

5.4 CF2:

• bits [83..56] of configurators (see Table 33)

Figure 19. Group 5 data records

9.17.7 Group 6 data records

6.1 ACR:

• iR RMS SWM accumulator: 20-bit accumulator of R phase current in SWM mode (see paragraph 9.7)
• R-phase elapsed: phase delay (see paragraph 9.15)

6.2 ACS:

• iS RMS SWM accumulator: 20-bit accumulator of S phase current in SWM mode (see paragraph 9.7)
• S-phase elapsed: phase delay (see paragraph 9.15)

6.3 ACT:

• iT RMS SWM accumulator: 20-bit accumulator of T phase current in SWM mode (see paragraph 9.7)
• T-phase elapsed: phase delay (see paragraph 9.15)

6.4 CF3:

• bits [111..84] of configurators (see Table 33)

9.17.8 Parity calculation

Figure 20. Group 6 data records

9.18 Status bits map

each phase. All of them provide information about the current meter status. Table 31. 3-phase status bits description

0 BIL No-load condition not detected in any phase No-load condition detected in all phases

1 BCF ΣΔ signals alive in all phases ΣΔ signal stuck in at least one phase

2 BFF BFR = 0 in all phases BFR = 1 in at least one phase

3 SIGN Three-phase active energy is negative Three-phase active energy is positive

4 PHR Phase 0 ≤ uR < π Phase π ≤ uR < 2π

5 PHS Phase 0 ≤ uS < π Phase π ≤ uS < 2π

6 PHT Phase 0 ≤ uT < π Phase π ≤ uT < 2π

7 HLT Data records reading is valid Data records are not valid. A reset occurred and a restart is in progress.

8 PIN The output pins are consistent with the data The output pins are different from the data,

this means some output pin is forced to 1 or 0.

9 BCS Sum of all phase currents is below threshold Sum of all currents above threshold

10 BSF Phase sequence is R -> S -> T Phase sequence is not R -> S -> T

11 BIF Phase energies have equal sign Phase energies do not have equal sign

bit of status register [0] BIL. This bit indicates no-load condition. In DAx status register bit BIL is represents NLC for phase X active energy. In DRx status register bit BIL is represents NLC for phase X reactive energy. In DFx status register bit BIL is represents NLC for phase X fundamental energy. SDATD pin. All the other signals can be read only through SPI interface.

9.19 Configuration bits map

are cleared whenever a reset condition occurs (both POR and remote reset). STPMC1 is released all antifuses presents low logic state. Table 32. X-phase status bits description

0 BIL No-load Condition not detected No-load condition detected

1 BCF ΣΔ signals alive One or both ΣΔ signal stuck

2 BFR Frequency of phase voltage is in range Frequency of line voltage is out of range or voltage

3 SIGN Active energy is negative Active energy is positive

4 LIN Phase 0 ≤ u < π Phase π ≤ u < 2π

5 ZRC After zero crossing After max value crossing

6 LOW Ux > UXmax / 16 U x < UXmax / 32

7 NAH Single Wire Meter mode

STPMC1 Theory of operation Doc ID 15728 Rev 7 55/77 Each configuration bit can be written sending a byte command to STPMC1 through its SPI interface. See paragraph 9.21 for details on SPI operation. A system signal WE (see paragraph 9.20) is used in order to do the permanent write of some OTP bit. There is also a special high voltage input pad VOTP , which delivers the power level necessary for permanent write to OTP cell. The STPMC1 can work either using the data stored in the OTP cells or the data from the shadow latches. This is done through the RD system signal (see paragraph 9.20). If RD is set, the CFG bits originates from corresponding OTP shadow latches otherwise, if RD is cleared, the CFG bits originates from corresponding OTP antifuses. In this way it is possible to test temporary configurators and calibrators before writing permanently on the device, for example during meter production tests. The very first CFG bit, called TSTD , disables any further OTP writing. After TSTD bit has been set, the only commands accepted are the mode signal precharge (see paragraph 9.20) and the remote reset request (see paragraph 9.21.1), this implies that the test mode is disabled and shadow latches cannot be used as source of configuration data anymore. The following table represents a collection and function of all configuration bits in the device. For multibit configurations the most significant bit address is bold. Table 33. Configuration bits map IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.7-BIT Binary DEC 0000000 0 TSTD 1 Test mode and OTP write disable: - TSTD=0: enable test modes and system signals, - TSTD=1: normal operation and no more writes to OTP or test modes 0000001 1 MDIV 1 Selection of measurement clock option: - MDIV=0: fMCLK = fXTAL1 * 2, - MDIV=1: fMCLK = fXTAL1 0000010 2 HSA 1 High speed analog clock selection: - HSA=0: fCLK = fXTAL1/4, - HSA=1: fCLK = fXTAL1/2 0000011 0000100

4 APL 2

Application type selection: - APL=0: peripheral MOP , MON=ZCR, WatchDOG, LED=pulses (X), - APL=1: peripheral MOP , MON=stepper(P), LED=pulses (X), - APL=2: standalone MOP , MON=stepper(P), LED=pulses(P), SCLNLC=no-load SDATD=tamper detected, SYN=neg act power - APL=3: standalone, MOP ,MON=stepper(P) LED=pulses (P/64) SCLNLC=no-load, SDATD=tamper indicator, SYN=neg act power 0000101 5 TCS 1 Type of current sensor selection: - TCS=0: Rogowski coil, - TCS=1: Current transformer (CT) 0000110 6 FRS 1 Nominal base frequency: - FRS=0: 50Hz - FRS=1: 60Hz 0000111 7 FUND Fundamental active and reactive energy: - FUND=0: full bandwidth active energy controls the stepper; full bandwidth reactive energy computation. - FUND=1: fundamental active energy controls the stepper; fundamental reactive energy computation

Theory of operation STPMC1 56/77 Doc ID 15728 Rev 7 Address Name N. of bits IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.7-BIT Binary DEC 0001000 8 ART 1 Reactive energy computation algorithm: - ART=0: natural computation - ART=1: artificial computation – not allowed if FUND =1 0001001 9 MSBF 1 Bit sequence output during record data reading selection: - MSBF=0: msb first - MSBF=1: lsb first 0001010 0001011

11 ABS 2

Negative power accumulation type: - ABS=0: 3-phase Ferraris, - ABS=1: absolute accumulation per phase - ABS=2: Ferraris per phase, - ABS=3: signed accumulation 0001100 0001101

13 LTCH 2

No-load condition threshold: - LTCH=0: 0,00125 * FS, - LTCH=1: 0,0025 * FS - LTCH=2: 0,005 * FS - LTCH=3: 0,010 * FS 0001110 0001111

15 KMOT 2

If APL=0 output selection for LED pin: KMOT=0 KMOT=1 KMOT=2 KMOT=3 3-phase R phase S phase T phase If APL = 1, 2, 3 pulsed output divider: If LVS=0, KMOT=0 KMOT=1 KMOT=2 KMOT=3 P/64 P/128 P/32 P/256 The constants at LVS=0 is valid also for LED when APL=3 If LVS=1, KMOT=0 KMOT=1 KMOT=2 KMOT=3 P/640 P/1280 P/320 P/2560 0010000 16 LVS 1 if APL = 0, 1 Selection of pulses(X) for LED: - LVS=0: active power, - LVS=1: reactive power. if APL = 1, 2, 3 Type of stepper selection: - LVS=0: 10 poles, 30ms, 5V stepper, - LVS=1: 2 poles, 150ms, 3V stepper 0010001 0010010 0010011 SYS 3 Measurement system selection: - SYS=0: 3-phase, 4-wire RSTN, 4-systxem RSTN (tamper) - SYS=1: 3-phase, 4-wire RSTN, 3-system RST_ - SYS=2: 3-phase, 3-wire RST_, 3-system RST_ (tamper) - SYS=3: 3-phase, 3-wire RST_, 2-system R_T_ (Aron) - SYS=4: 2-phase, 3-wire _STN, 2-system _ST_ (America) - SYS=5: 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:coil) - SYS=6: 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:shunt) - SYS=7: 1-phase, 2-wire __TN, 1-system __T_ 0010100 20 SCLP 1 Polarity of SCLNLC idle state selection: - SCLP=0: idle state SCLNLC=1, - SCLP=1: idle state SCLNLC=0 Table 33. Configuration bits map (continued)

STPMC1 Theory of operation Doc ID 15728 Rev 7 57/77 Address Name N. of bits IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.7-BIT Binary DEC 0010101 21 PM 1 Precision meter: - PM=0: Class 1, - PM=1: Class 0.1 0010110 22 FR1 1 Selection of measurement clock value: - FR1=0: fMCLK =8.192 MHz, - FR1=1: fMCLK =9.8304 MHz 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 CCA 9 - PM =0, TCS=0: Mutual current influence compensation data A SYS = 0, 1, 2, 3 SYS = 4, 5, 6, 7 CCA[8] = sign α CCA[8] = sign α CCA[7] = sign β CCA[7..0] = α CCA[6] = sign γ CCA[5..0] = α - PM=1: Calibration extenders for voltage and phase CCA[8..7] = CvT CCA[6..5] = CvS CCA[4..3] = CvR CCA[1..0] = CpC 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 CIN 8 Calibration data for current channel of neutral conductor 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 CIR 8 Calibration data for current channel of phase R 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 CIS 8 Calibration data for current channel of phase S 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 CIT 8 Calibration data for current channel of phase T

Theory of operation STPMC1 58/77 Doc ID 15728 Rev 7 Address Name N. of bits IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.7-BIT Binary DEC 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 CVR 8 Calibration data for voltage channel of phase R 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 CVS 8 Calibration data for voltage channel of phase S 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 CVT 8 Calibration data for voltage channel of phase T 1011000 1011001 1011010 1011011 CPR 4 Compensation of phase error of phase R 1011100 1011101 1011110 1011111 CPS 4 Compensation of phase error of phase S 1100000 1100001 1100010 1100011 CPT 4 Compensation of phase error of phase T 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 100 101 102 103 104 105 106 107 CCB 8 - PM =0, TCS=0: Mutual current influence compensation data B SYS = 0, 1, 2, 3 SYS = 4, 5, 6, 7 CCB[7..3] = β CCB[7..0] = β CCB[2..0] = γ - PM=1: Calibration extenders for current CCB[7..6] = CiT CCB[5..4] = CiS CCB[3..2] = CiR CCB[1..0] = CiN 1101100 1101101 108

109 CPC 2 Common sign and coarse phase error compensation

STPMC1 Theory of operation Doc ID 15728 Rev 7 59/77

9.20 Mode signals

The STPMC1 includes 12 Mode signals located in the DRP and DFP registers, some are used for internal testing purposes while others are useful to change some of the operation of the STPMC1. The mode signals are not retained when the STPMC1 supply is not available and then they are cleared when a POR occurs, while they are not cleared when a remote reset command (RRR) is sent through SPI. The mode signal bit can be written using the normal writing procedure of the SPI interface (see SPI section). In the table below the commands to change mode signals are given. RD mode signal has been already described in paragraph 9.19 but there is another implied function of the signal RD. When it is set, each sense amplifier is disconnected from corresponding antifuse element and this way, its 3 V NMOS gate is protected from the high voltage of VOTP during permanent write operation. This means that as long as the VOTP voltage reads more than 3 V, the signal RD should be set. PUMP: when set, the PUMP mode signal transform the MOP and MON pins to act as driving signals to implement a charge-pump DC-DC converter. This feature is useful in order Address Name N. of bits IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.7-BIT Binary DEC 1101110 110 ENH 1 Fifth data input enable: - ENH=0: Voltage#0=DAN, - ENH=1: Voltage#0=DAH 1101111 111 CHK 1 Reserved – Must be always set to 1 Table 34. Mode signals description

76543210 REGISTER Functional description of commands for changing system signals

Theory of operation STPMC1 60/77 Doc ID 15728 Rev 7 to boost the VCC supply voltage of the STPMC1 to generate the VOTP voltage (14 V to 20 V) needed to program the OTP antifuse elements. WE (write Enable): This mode signal is used to permanently write to the OTP antifuse element. When this bit is not set, any write to the configuration bit is recorded in the shadow latches. When this bit is set the writing is recorded both in the shadow latch and in the OTP antifuse element. Precharge: this command increments the index register while reading. After reading a 32- bit data record it is possible to access next group data records by sending this command. This way, a faster access to later groups is possible. TSG0: In standalone mode it is possible to produce a data latching request by a pulse on test signal TSG0. In fact in such configuration is not possible to latch internal data into transmission latches because the SYN is an output pin as long as SCS is in idle state and it is under control of an indicator signal of negative power. After TSTD configuration bit is set, only the precharge and TSGx commands can be executed.

9.21 SPI interface (configuration bit SCLP )

The SPI interface supports a simple serial protocol, which is implemented in order to enable a communication between some master system (microcontroller or PC) and the device. Three tasks can be performed with this interface:

• remotely resetting the device,
• reading data records,
• writing the mode bits and the configuration bits (temporarily or permanently); Four pins of the device are dedicated to this purpose: SCS, SYN, SCLNCN, SDATD. SCS, SYN and SCLNLC are all input pins while SDATD can be input or output according if the SPI is in write or read mode. A high level signal for these pins means a voltage level higher than 0.75 x V CC, while a low level signal means a voltage value lower than 0.25 x VCC. The STPMC1 internal registers are not directly accessible, rather a 32-bit of transmission latches are used to pre-load the data before being read or written to the internal registers. The condition in which SCS, SYN and SCLNLC inputs are set to high level determines the idle state of the SPI interface and no data transfer occurs. As previously described in the document, when the STPMC1 is in standalone mode, SYN, SCLNLC and SDATD can provide information on the meter status (see programmable pin functions) and are not used for SPI communication. In this section, the SYN, SCLNLC and SDATD operation as part of the SPI interface is described. SCS: when low, SCS pin enables SPI communication, both in standalone and in peripheral operating mode. This means that the master can abort any task in any phase by deactivation of SCS. In standalone mode SCS high enables SYN, SCLNLC and SDATD to output meter status. SYN: this pin operates different functions according to the status of SCS pin. When SCS is low the SYN pin status select if the SPI is in read (SYN = 1) or write mode (SYN = 0). When SCS is high and SYN is also high the results of the input or output data are transferred to the transmission latches. SCLNLC: it is basically the clock pin of the SPI interface. Configuration bit SCLP controls the polarity of the clock (see configuration bits map). This pin function is also controlled by

the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal. When SCS is high, SCLNLC determines idle state of the SPI. state of any of the input pins above is considered in an idle (not active) state. SDATD and SYN are not high due to the states of the corresponding internal status bits. SCLNLC. The first valid bit of SDATD is always started with activation of signal SCLNLC.

9.21.1 Remote reset

125 ms delayed restart of the digital module. This signal does not clear the mode signals. Note: All the time intervals must be longer than 30 ns. t7 -> t8 is the reset time, this interval must be longer than 30 ns as well. Figure 21. Timing for providing remote reset request

9.21.2 Reading data records

short as 30 ns. There are two phases of reading, called latching and shifting. measurement clock, i.e. more than 500 ns at 4 MHz. can be aborted at any time by deactivation of SCS. t2 −> t3: Data latched, SPI idle. Interval value > 30 ns. t3 −> t4: Enable SPI for read operation. Interval value > 30 ns. t4 −> t5: Serial clock counter is reset. Interval value > 30 ns. Figure 22. Timing for data records reading

can be further divided into a pair of 4-bit nibbles, most and least significant nibble (msn, lsn). with the next group data records sequence. latched into transmission latches, thus losing the previous reading. done, each byte is read out as the least significant bit (lsb) first.

9.21.3 Writing procedure

mode bits the addresses are those indicated in the mode signal paragraph. summarized in the table below. Figure 23. Data records reconstruction

STPMC1 Theory of operation Doc ID 15728 Rev 7 65/77 t3: data value is placed in SDA t4: SDA value is stable and shifted into the device t3 −> t5 (> 10 µs): writing clock period t3 −> t5: 1 bit data value t5 −> t6: 6 bits address of the destination latch t6 −> t7: 1 bit EXE command t8: end of SPI writing t9: SPI enters idle state

9.21.4 Interfacing the standard 3-wire SPI with STPMC1 SPI

Due to the fact that a 2-wire SPI is implemented in the STPMC1, it is clear that sending any command from a standard 3-wire SPI would require 3-wire to 2-wire interface, which should produce a proper signal on SDATD from host signals SDI, SDO and SYN. A single gate 3- state buffer could be omitted by an emulation of SPI just to send some command. On a microcontroller this would be done by the following steps: 1. disable the SPI module 2. set SDI pin which is connected to SDATD to be output 3. activate SYN first and then SCS 4. apply new bit value to SDI and activate SCL 5. deactivate SCL 6. repeat the last two steps seven times to complete one byte transfer 7. repeat the last three steps for any remaining byte transfer 8. set SDI pin to be input 9. deactivate SCS and the SYN 10. enable the SPI module In case of precharge command (0xFF), emulation above is not necessary. Due to the pull up device on the SDATD pin of the STPMC1 the processor needs to perform the following steps: 1. activate SYN first in order to latch the result; 2. after at least 1 s activate SCS 3. write one byte to the transmitter of SPI (this produces 8 pulses on SCL with SDI = 1) 4. deactivate SYN 5. optionally read the data records (the sequence of reading is altered 6. deactivate SCS

9.21.5 Permanent writing of the CFG bits

In order to make a permanent set of some CFG bits, the following procedure should be conducted:

Theory of operation STPMC1 66/77 Doc ID 15728 Rev 7 1. collect all addresses of CFG bits to be permanently set into some list 2. clear all OTP shadow latches 3. set the system signal RD 4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP 5. wait for VOTP voltage is stable 6. set one OTP shadow latch from the list 7. set the system signal WE 8. wait for 300 µs 9. clear the system signal WE 10. clear the OTP shadow latch which was set in step 6 11. until all wanted CFG bits are permanently set, repeat steps 5 to 11 12. disconnect the current source 13. wait for VOTP voltage is less than 3V 14. clear the system signal RD 15. read all data records, in the last two of them there is read back of CFG bits 16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1 to 16 For set or clear steps, apply the timing shown in timing for data records reading with proper signal on the SDATD. For step 15, apply the timing shown in timing for writing configuration and mode bits. For permanent set of the TSTD bit, which causes no more writing to the configuration bits, the procedure above must be conducted in such way that steps 6 to 13 are performed in series during single period of active SCS because the idle state of SCS would make the signal TSTD immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal RD and so, connecting all gates of 3 V NMOS sense amplifiers of already permanently set CFG bits to the VOTP source.

STPMC1 Energy calculation algorithm Doc ID 15728 Rev 7 67/77

10 Energy calculation algorithm

For the purpose of simplicity the energy computation shown below is relative to only one phase. Given line voltage and current as: Equation 12 u = U sin (ω t) i = I sin(ω t + ϕ) The voltage divider, AD converter and calibrator produce the value: Equation 13 vu = u (R2/(R1+R2) (AU/VREF) kU = u kD = A sin (ω t) The Rogowski coil preamplifier, AD converter and calibrator produce the value: Equation 14 vi = - L (di/dt) (AI/VREF) kI = - I kL ω cos (ω t + ϕ) = - B ω cos (ω t + ϕ) The 2nd stage internal integrations produce the values: Equation 15 vui = ∫ vudt = - (A / ω) cos (ω t) kINT Equation 16 vii = ∫ vidt = - B sin (ω t + ϕ) kINT From signs of vu and vui the base frequency of line can be produced: Equation 17 ω / kINT = k / T The frequency compensated values are: Equation 18 v uic = ω / kINT vui = - A cos (ω t) Equation 19 viic = ω / kINT vii = - B ω sin (ω t + ϕ) The 3rd stage internal integrations and DC cancellations produce the values: Equation 20 vuiic = ∫ vuicdt = - (A / ω) sin (ω t) kINT Equation 21 viiic = ∫ viicdt = B cos (ω t + ϕ) kINT

Energy calculation algorithm STPMC1 68/77 Doc ID 15728 Rev 7 In case of shunt sensor (TCS = 1), an additional stage of internal digital differentiated produces the value: Equation 22 vd = dvu/dt = A ω cos (ω t) kDIF The shunt preamplifier, AD converter and calibrator produce the value: Equation 23 vs = i RS (AI/VREF) kI = i kS = C sin (ω t + ϕ) The 2nd stage internal integrations produce the values: Equation 24 vdi = ∫ vddt = A sin (ω t) kDIF kINT = A sin (ω t) Equation 25 vsi = ∫ vsdt = - (C / ω) cos (ω t + ϕ) kINT The frequency compensated values are: Equation 26 Vdic = ω / kINT vdi = A ω sin (ω t) / kINT Equation 27 vsic = ω / kINT vsi = - C cos (ω t + ϕ) The 3rd stage internal integrations and DC cancellations produce the values: Equation 28 vdiic = ∫ vdicdt = A cos (ω t) kDIF kINT = A cos (ω t) Equation 29 vsiic = ∫ vsicdt = - (C / ω) sin (ω t + ϕ) kINT

10.1 Active energy calculation

The active power is computed as follows. First, the voltage stream from the 1st stage (Equation 13 or Equation 22) is multiplied to the 16-bit current from the 2nd stage (Equation 16 or Equation 25) and current stream from the 1st stage (Equation 14 or Equation 23) is multiplied to 16-bit voltage from the 2nd stage of filter (Equation 15 or Equation 24), yielding: Equation 30 P1 = vu vii = - ABkINT sin (ω t) sin (ω t + ϕ) = - ABkINT[cos ϕ - cos (2 ω t + ϕ)] / 2 Equation 31 P2 = vui vi = ABkINT cos (ω t) cos (ω t + ϕ) = ABkINT [cos ϕ + cos (2 ω t + ϕ)] / 2

STPMC1 Energy calculation algorithm Doc ID 15728 Rev 7 69/77 In case of a non Rogowski sensor, the corresponding products are: Equation 32 P1 = vd vsi = - AC kDIFkINT cos (ω t) cos (ω t + ϕ) = - AC [cos ϕ + cos (2 ω t + ϕ)] / 2 Equation 33 P2 = vdi vs = AC kDIFkINT sin (ω t) sin (ω t + ϕ) = AC [cos ϕ - cos (2 ω t + ϕ)] / 2 Then a subtraction of P1 from P2 is performed: Equation 34 P = (P2 - P1) / 2 = (AB cos ϕ) kINT / 2 = (UkDIkL cos ϕ) kINT / 2 = URMS IRMS cos ϕ kP where: Equation 35 kP = kD kL kINT This gives the same result for P in case of non Rogowski sensor, substituting B and kL kINT with C and kS: Equation 36 P = (P2 - P1) / 2 = (AC cos ϕ) / 2 = (UkDIkS cos ϕ) / 2 = URMS IRMS cos ϕ kP where: Equation 37 kP = kD kS The result in Equation 35 and Equation 36 is proportional to the DC part of active power of line. The division by 2 is a feature of ΔΣ subtractor. The absence of harmonic components eliminates the spread of results due to asynchronism with the line. This fact enables fast a calibration procedure which is used to set the target constant of meter k A sensitivity analysis of kP yields: Equation 38 ΔkP/kP = ΔL/L + R1 / (R1+R2)(ΔR2/R2 - ΔR1/R1) + ΔAU/AU + ΔAI/AI - 2 ΔVREF/VREF Equation 39 ΔkP/kP = ΔRS / RS + R1 / (R1+R2)(ΔR2/R2 - ΔR1/R1) + ΔAU/AU + ΔAI/AI - 2 ΔVREF/VREF It is clear that the device is responsible for AU, AI and VREF parts. The parts kU, kI and kINT are omitted, because they are not subject to aging or temperature variations due to digital implementation.

10.2 Reactive energy calculation

The natural reactive power (ART = 0) of the line is computed as follows. First, 16-bit voltage from the 3rd stage (Equation 20 or Equation 28) is multiplied by the current stream from the 1st stage (Equation 14 or Equation 23) and the frequency

Energy calculation algorithm STPMC1 70/77 Doc ID 15728 Rev 7 compensated stream of 16-bit voltage from the 2nd stage of filter (Equation 18 or Equation 26) is multiplied by the 16-bit current stream from the 2nd stage (Equation 16 or Equation 25) yielding: Equation 40 Q1 = vuiic vi = ABkINT sin (ω t) cos (ω t + ϕ) = - ABkINT [sin ϕ - sin (2 ω t + ϕ)] / 2 Equation 41 Q2 = ω / kINT vui vii = ABkINT cos (ω t) sin (ω t + ϕ) = ABkINT [sin ϕ + sin (2 ω t + ϕ)] / 2 In case of non Rogowski sensor, the corresponding products are: Equation 42 Q1 = vdiic vs = ACkDIFkINT cos (ω t) sin (ω t + ϕ) = AC [sin ϕ + sin (2 ω t + ϕ)] / 2 Equation 43 Q2 = ω / kINT vdi vsi = - ACkDIFkINT sin (ω t) cos (ω t + ϕ) = - AC [sin ϕ - sin (2 ω t + ϕ)] / 2 Then a subtraction of Q1 from Q2 is performed: Equation 44 Q = (Q2 - Q1) / 2 = (AB sin ϕ) kINT / 2 = (UkDIkL sin ϕ) kINT / 2 = URMS IRMS sin ϕ kP This gives the same result for Q in case of non Rogowski sensor, substituting B and kLkINT with C and kS: Equation 45 Q = (Q2 - Q1) / 2 = (AC sin ϕ) = (UkDIkS sin ϕ) / 2 = URMS IRMS sin ϕ kP The artificial reactive power (ART = 1) of line is computed as follows. The inter-phase voltage sigma-delta stream is computed from voltage stream from the 1st stage as follows: Equation 46 ΔvuR = (vuS - vuT) / 2 ΔvuS = (vuT - vuR) / 2 ΔvuT = (vuR - vuS) / 2 The inter-phase voltage sigma-delta stream (Equation 46), the 16-bit current from the 2nd stage (Equation 16 or Equation 25) and the value of 1 / √3 are multiplied yielding: Equation 47 Q = Δvu vii 1 / √3 = AB kINT [sin ϕ + sin (2 ω t + ϕ)] / 2 or in case of non Rogowski sensor, the corresponding products are: Equation 48 Q = Δvd vsi 1 / √30 = AC [sin ϕ + sin (2 ω t + ϕ)] / 2

STPMC1 Energy calculation algorithm Doc ID 15728 Rev 7 71/77

10.3 Voltage and current RMS values calculation

The IRMS value is produced from 16-bit value of Equation 16: Equation 49 The UiRMS is produced from stream and 16-bit value of Equation 15: Equation 50 In case of non Rogowski sensor, the same dedicated RMS blocks produce some other values, because input values for the blocks are changed. Therefore, another RMS value, named IiRMS is produced from 16-bit value of Equation 25: Equation 51 The URMS is produced from stream and 16-bit value of Equation 24: Equation 52

10.4 Energy integration

The internal hard-wired DSP unit performs all the computations above in real time for a power line in parallel by means of arithmetic blocks. Due to implementation of an integrator, up/down counter or deviator, part of which is also an integrator in a feedback, additional factors are introduced into computations. If we declare f MCLK as the measurement clock frequency and M as number of possible values of some integrator, the following constant factors can be defined: Equation 53 k INT = 2 fMCLK / MINT = 28 kUD = 2 fMCLK / MUD = 211 kDIF = MDIF / 2 fMCLK = 2-8 IRMSkLkINT = ∫ T ii dtT v = B 2 UiRMSkD = ∫ T ui dtT v = AkINT/ω 2 IiRMSkSkINT = ∫ T si dtT v = C/ω 2 URMSkD = ∫ T di dtT v = A 2

Energy calculation algorithm STPMC1 72/77 Doc ID 15728 Rev 7 The DSP performs also an integration of powers (P , Q) into energies: Equation 54 AW = URMS IRMS cos ϕ kP kUD Equation 55 AW = URMS IRMS sin ϕ kP kUD These integrators are implemented as up/down counters and they can roll over. 20-bit output buses of the counters are assigned as the most significant part of the energy data records. It is a responsibility of the application to read the counters at least every second so as not to miss any rollover. The integration of power can be suspended due to detected error on the source signals or due to no load condition. From AW, stepper output signals are generated.

10.5 Fundamental power calculation

The fact that integration suppresses all but fundamental components of signals is used to compute the fundamental active power, which is in case of Rogowski coil: Equation 56 F 1 = vuic viiic = - ABkINT cos (ω t) cos (ω t + ϕ) = - ABkINT [cos ϕ + cos (2 ω t + ϕ)] / 2 Equation 57 F2 = viic vuiic = - ABkINT sin (ω t) sin (ω t + ϕ) = ABkINT [cos ϕ - cos (2 ω t + ϕ)] / 2 Equation 58 F = (F2 - F1) / 2 = (AB cos ϕ) kINT / 2 = (UkDIkLcos ϕ) kINT / 2 = URMS IRMS cos ϕ kP Similar result are found in case of non Rogowski sensor: Equation 59 F1 = vdic vsiic = - AC sin (ω t) sin (ω t + ϕ) = - AC [cos ϕ - cos (2 ω t + ϕ)] / 2 Equation 60 F2 = vsic vdiic = - ACkDIFkINT cos (ω t) cos (ω t + ϕ) = - AC [cos ϕ + cos (2 ω t + ϕ)] / 2 Equation 61 F = (F2 - F1) / 2 = - AC cos (2 ω t + ϕ) = UkDIks cos (2 ω t + ϕ) / 2 = URMS IRMS cos (2 ω t + ϕ) kP The fundamental reactive power in case of a Rogowski coil is: Equation 62 Q = vuiic viiic ω / kINT = - ABkINT cos (ω t) sin (ω t + ϕ) = ABkINT [sin ϕ - sin (2 ω t + ϕ)] / 2 Similar results are found in cases of non Rogowski sensors: Equation 63 Q = vdiic vsiic ω / kINT = - AC cos (ω t) sin (ω t + ϕ) = AC [sin ϕ - sin (2 ω t + ϕ)] / 2.

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Dim. mm. inch. A 1.2 0.047 b 0.19 0.30 0.007 0.012 c0 . 0 9 0.20 0.004 0.007 9 e 0.65 B SC 0.0256 B SC K0 ° 8°0 ° 8° TSSOP20 mechanical data c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 0087225C

Dim. mm. inch. A 330 12. 992 C 12. 8 13.2 0.504 0.51 9 D 20.2 0.7 95 N6 0 2 . 362 T 22.4 0. 882 Ao 6. 8 7 0.26 8 0.276 Bo 6. 9 7.1 0.272 0.2 80 Ko 1.7 1. 9 0.067 0.075 Po 3.9 4.1 0.15 3 0.161 P 11. 9 12.1 0.46 8 0.476 Tape & reel TSSOP20 mechanical data

Table 36. Document revision history 22-May-2009 1 Initial release. 28-Jul-2009 3 Updated: paragraph 9.16.2. Example 8: 1-ph system - BCS = 1 on page 31 and Equation 11: on page 48. Modified: paragraph 9.17.2 on page 47. 11-Oct-2011 5 Updated: V IH and VIL values Table 7 on page 13. on page 1, T able 11 on page 23 and Table 23 on page 41. 14-Nov-2012 7 Modified Figure 8 on page 22.