STPM11_V01 STM | Alldatasheet
Document overview
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- PDF pages: 46
Technical content
Datasheet sections
- 1 Schematic diagram
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Terminology
- 5.1 Measurement error
- 5.2 ADC offset error
- 5.3 Gain error
- 5.4 Power supply DC and AC rejection
- 5.5 Conventions
- 6 Typical performance characteristi cs
- 7 Theory of operation
- 7.1 General operation
- 7.2 Analog inputs
- 7.4 Period and line voltage measurement
- 7.5 Single wire meter mode (STPM13/14 with Rogowsky coil sensor)
- 7.6 Power supply
- 7.7 Load monitoring
- 7.8 Error detection
- 7.9 Tamper detection module (STPM13/14 only)
- 7.10 Phase compensation
- 7.11 Clock generator
- 7.12 Resetting the STPM1x
- 7.13 Energy to frequency conversion
- 7.14 Driving a stepper motor
- 7.15 Configuring the STPM1x
Features
■ Ripple free active energy pulsed output ■ Direct stepper counter drivers ■ Shunt, current transformer, Rogowsky coil sensors ■ Live and neutral monitoring (STPM13/14) ■ Easy and fast digital calibration at only one load point ■ No-load, negative power and tamper indicators ■ Integrated linear VREGs ■ RC (STPM11/13) or crystal oscillator (STPM12/14) ■ Support 50 ÷ 60 Hz - IEC62052-11, IEC62053- 2X specification ■ Less than 0.1% error
Description
The STPM1x family is designed for effective measurement of active energy in a power line system using a Rogowski Coil, current transformer and shunt sensors. This device is specifically designed to provide all the necessary features to implement a single phase energy meter without any other active component. The STPM1x device family consists, essentially, of two parts: the analog part and the digital part. The former, is composed of a preamplifier and first order ∑ Δ A/D converter blocks, band gap voltage reference, low drop voltage regulator. The digital part is composed of a system control, oscillator, hard wired DSP and interface for calibration and configuration. The calibration and configuration are done by OTP cells, that can be programmed through a serial interface. The configured bits are used for testing, configuration and calibration purposes. From two ∑ Δ output signals coming from the analog section, a DSP unit computes the amount of consumed active energy. The active energy is available as a pulse frequency output and directly driven by a stepper counter. In the STPM1x an output signal with pulse frequency proportional to energy is generated. This signal is used in the calibration phase of the energy meter application allowing a very easy approach. When the device is fully configured and calibrated, a dedicated bit of OTP block can be written permanently in order to prevent accidental entry into test mode or changing any configuration bit. TSSOP20 Table 1. Device summary
STPM11, STPM12, STPM13, STPM14 Contents Doc ID 13167 Rev 8 3/46 Obsolete Product(s) - Obsolete Product(s)
1 Schematic diagram
Figure 1. Block diagram
2 Pin configuration
Figure 2. Pin connections (top view) Table 2. Pin description
1 MON P O Output for Stepper’s node
2 MOP P O Output for Stepper’s node
3 SCS D IN Enable or disable configuration interface for device configuration. 4V DDD A OUT 1.5 V Output of internal low drop regulator which supplies the digital core. 7V OTP P INr Supply voltage for OTP cells. 8V DDA A OUT 3 V output of internal low drop regulator which supplies the analog part.
10 I IN1 A IN Negative input of primary current channel
11 I IP2 A IN Positive input of secondary current channel (STPM13/14 only)
12 I IN2 A IN Negative input of secondary current channel (STPM13/14 only)
13 V IP A IN Positive input of voltage channel
14 V IN A IN Negative input of voltage channel
16 CLKIN A IN Crystal oscillator input or resi stor connection if RC oscillator is selected
17 CLKOUT A OUT Oscillator output (RC or crystal)
20 LED D O Pulsed output proportional to active energy
- A: Analog, D: Digital, P: Power
3 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 3. Absolute maximum ratings (see Note:) Table 4. Thermal data
- This value is referred to single-layer PCB, JEDEC standard test board.
4 Electrical characteristics
between VCC and VSS unless otherwise specified. Table 5. Electrical characteristics
5 V±10%
4 MHz, VCC = 5 V 120
4 MHz, VCC = 5 V 2
Table 5. Electrical characteristics (continued)
Table 6. Typical external components
Terminology STPM11, STPM 12, STPM13, STPM14 12/46 Doc ID 13167 Rev 8
5 Terminology
5.1 Measurement error
The error associated with the energy measured by STPM1X is defined as: Percentage Error = [STPM1X (reading) - True Energy] / True Energy
5.2 ADC offset error
This is the error due to the DC component associated with the analog inputs of the A/D converters. Due to the internal automatic DC offset cancellation, the STPM1X measurement is not affected by DC components in voltage and current channel. The DC offset cancellation is implemented in the DSP .
5.3 Gain error
The gain error is gain due to the signal channel gain amplifiers. This is the difference between the measured ADC code and the ideal output code. The difference is expressed as a percentage of the ideal code.
5.4 Power supply DC and AC rejection
This parameter quantifies the STPM1X measurement error as a percentage of the reading when the power supplies are varied. For the PSRR AC measurement, a reading at two nominal supply voltages (3.3 and 5 V) is taken. A second reading is obtained with the same input signal levels when an ac (200 mV RMS/100 Hz) signal is introduced onto the supply voltages. Any error introduced by this ac signal is expressed as a percentage of reading. For the PSRRDC measurement, a reading at two nominal supply voltages (3.3 and 5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±10%. Any error introduced is again expressed as a percentage of the reading.
5.5 Conventions
The lowest analog and digital power supply voltage is named VSS which represents the system Ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. Sinking current means that the current is flowing into the pin and is positive. Sourcing current means that the current is flowing out of the pin and is negative. The timing specifications of the signal treated by digital control are relative to CLKOUT. This signal is provided by from the crystal oscillator of 4.194 MHz nominal frequency or by the internal RC oscillator. An external source of 4.194 MHz or 8.192 MHz can be used. The timing specifications of signals of the CFGI interface are relative to the SCL-NLC, there is no direct relationship between the clock (SCL-NLC) of the CFGI interface and the clock of the DSP block. A positive logic convention is used in all equations. Obsolete Product(s) - Obsolete Product(s)
6 Typical performance characteristics
Figure 3. Supply current vs. supply voltage, Figure 4. RC oscillator frequency vs. V CC, Figure 5. RC oscillator: frequency jitter vs. Figure 6. Analog voltage regulator: line - load Figure 7. Digital voltage regulator: line - load Figure 8. Voltage channel linearity at
7 Theory of operation
7.1 General operation
single-phase energy meter systems. OTP (one time programmable) cells, preventing calibration tampering. called PST that allow the selection of the sensor and the gain of the input amplifiers. provides information on tamper, no-load and negative power. harmonic only. This last energy value is obtained by filtering the wide band active energy.
7.2 Analog inputs
(STPM13/14) fully differential current input channels. differential input voltage for the voltage channel is ± 0.3 V. Table 7. Voltage channel
which has the benefit of avoiding any offset compensation. Table 8. Configuration of current sensors
32 Shunt 3 x
Table 9. Configuration of current sensors
of the DAC output (and therefore the bit stream) can approach that of the input signal level. resulting signal has a resolution of 11bits for voltage channel and 16 bits for current channel.
7.4 Period and line voltage measurement
lower than fCLK/217 Hz and an internal error flag BFR (base frequency range) is set. three times in a row, in order to set the error flag BFR. Figure 15. First order ∑ Δ A/D converter
Where KV is the voltage calibrator value ranging from 0.875 to 1.000.
7.5 Single wire meter mode (STPM13/14 with Rogowsky coil
predefined value for computing the energy without sensing it.
- In this way, if the BFR error is detected, STPM1X enters in SWM. If BFR is cleared, the
Table 10. RMS voltage check
provide the necessary supply to STPM1x and the other electronic components of the meter.
7.6 Power supply
the necessary voltage for the analog part VDDA (3 V) and for the digital part VDDD (1.5 V). capacitors must be located very close to the device. Table 11. Nominal voltage values
7.7 Load monitoring
signal is also available in the status bit BIL. dependent on the selected current gain (Ai) and the calibration registers constant Kp=Kv*Ki. forces the SCLNLC pin to be low. Figure 16. Bandgap temperature variation Table 12. No load detection thresholds
STPM11, STPM12, STPM13, STPM14 Theory of operation Doc ID 13167 Rev 8 21/46
7.8 Error detection
In addition to the no-load condition and the line frequency band, the integration of power can be suspended also due to detected error on the source signals. There are two kinds of error detection circuits involved. The first checks all the ∑ Δ signals from the analog part if any are stacked at 1 or 0 within the 1/128 of fCLK period of observation. In case of detected error the corresponding ∑ Δ signal is replaced with an idle ∑ Δ signal, which represents a constant value 0. Another error, condition occurs if the MOP , MON and LED pin outputs signals are different from the internal signals that drive them. This can occur if some of this pin is forced to GND or to some other imposed voltage value.
7.9 Tamper detection module (STPM13/14 only)
The STPM13/14 is able to measure the current in both live and neutral wires to implement an anti-tamper function. When a difference between the two measurements is detected, the STPM13/14 enters the tamper state. When there is a very small difference between the two channels, the STPM13/14 is in normal state. In particular, both channels are not constantly observed. A time multiplex mechanism is used. During the observation time of the selected channel, its active energy is calculated. The detection of a tamper condition occurs when the absolute value of the difference between the two active energy values is greater than a certain percentage of the averaged energy during the activated tamper module. This percentage value can be selected between two different values (12.5% and 6.25%) according to the value of the configuration bit CRIT. The tamper condition will be detected when the following formula is satisfied: Equation 6 EnergyCH1 - EnergyCH2 > K CRIT (EnergyCH1 + EnergyCH2)/2; where KCRIT can be 12.5% or 6.25%. The detection threshold is much higher than the accuracy difference of the current channels, which should be less than 0.1%. Some margin should be left for a possible transition effect, due to accidental synchronism between the actual load current change and the rhythm of taking the energy samples. The tamper circuit works if the energies associated with the two current channels will be both positive or both negative. If the two energies have different signs, the tamper remains on constantly. However, the channel with the associated higher power is selected for the final computation of energy. In single wire mode, the apparent energy rather than active is used for tamper detection. Detailed operational description Normal state The meter is initially set to normal state, i.e. tamper not detected. In such state, we expect that the values of both load currents should not differ more than the accuracy difference of the channels. For this reason, we can use an average value of currents of both channels for the active energy calculation. The average is implemented with the multiplex ratio of 32:32 periods of line per channel. This means that for 32 periods of line voltage, i.e. 640 ms at 50 Hz, the current of the primary channel is used for the calculation followed by another 32 Obsolete Product(s) - Obsolete Product(s)
tamper detected state is changed to either normal or another tamper detected state. SDA-TD pin. When this pin is low, a tamper condition has been detected. Figure 17. Tamper conditions
STPM11, STPM12, STPM13, STPM14 Theory of operation Doc ID 13167 Rev 8 23/46 When internal signals are not good enough to perform the computation, i.e. line period is out or range or ∑Δ signals from the analog part are stacked at high or low logic level, or no load condition is activated, the tamper module is disabled and its state is preset to normal.
7.10 Phase compensation
The STPM1X is does not introduce any phase shift between voltage and current channels. However, the voltage and current signals come from transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The STPM1x provide a means of digitally calibrating these small phase errors through a introducing delays on the voltage or current signal. The amount of phase compensation can be set using the 4 bits of the phase calibration register (CPH). The default value of this register is at a value of 0 which gives 0° phase compensation. A CPH value of 15 (1111) introduces a phase compensation of +0.576°. This compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. The resolution step of the phase compensation is 0.038°.
7.11 Clock generator
All the internal timing of the STPM1X is based on the CLKOUT signal. This signal is generated by different circuits according to the STPM1x version.
- STPM11/13: Internal RC Oscillator. A resistor connected between CLKIN and Ground will set the RC current. For 4 MHz operation the suggested settling resistor is 12 kΩ; The oscillator frequency can be compensated using the CRC configuration bit (see Table 15 and Figure 14)
- STPM12/14: Quartz Oscillator. The oscillator circuit is designed to support an external crystal. The suggested circuit is depicted in Figure 18. These versions support also an external oscillator signal source that must be connected to the CLKOUT pin. The clock generator is powered from analog supply and is responsible for two tasks. The first one is to retard the turn-on of some function blocks after POR in order to help smooth start of external power supply circuitry by keeping all major loads off. The second task of the clock generator is to provide all necessary clocks for analog and digital parts. Within this task, the MDIV configuration bit is used to inform the device about the nominal frequency value of CLKOUT. The suggested operation frequency range is from 4.000 MHz to 4.194 MHz. Obsolete Product(s) - Obsolete Product(s)
7.12 Resetting the STPM1x
reset state for about 125 ms after a reset condition.
7.13 Energy to frequency conversion
calibration phase and low frequency for readout purposes; STPM1x supports both cases. corresponds to 1 kWh. We will name this value as P . KMOT configuration bits. In this case the pulses will have a fixed width of 31.25 ms. Figure 18. Different oscillator circuits (a); (b); (c)
calibration time of the meter.
7.14 Driving a stepper motor
signals are brought to the MOP and MON pins that are able to drive the stepper motor. The mono-flop limits the length of the pulses according to the LVS bit value. them has only one half of selected frequency. Table 13. Different settings for led signal
1 P/128
2 P/32
3 P/256
Table 14. Configuration of MOP and MON pins
When a no-load condition is detected MOP and MON are held low.
7.15 Configuring the STPM1x
infinite number of times in order to test the device operation. The shadow registers are cleared whenever a reset condition occurs. certain configuration and calibration values of the device. Figure 19. Positive energy stepper driving signals Figure 20. Negative energy stepper driving signals
Configuration Interface section (7.17). implies that the shadow latches can no longer be used as source of configuration data. Table 15. Configuration bits map
This bit swaps the energy type between fundamental or wide band. BGTC 2 Bandgap temperature compensation bits. See Figure 16 for details. the compensation is 0°, when CPH=15 the compensation is 0.576°. 8-bit unsigned data for voltage channel calibration. Table 15. Configuration bits map (continued)
8-bit unsigned data for primary current channel calibration. 8-bit unsigned data for secondary current channel calibration. 2-bit modifier of nominal voltage for Single Wire Meter.
- IMPORTANT: This Bit represents the MSB of the decimal value indicated in the description column.
7.16 Mode signals
and then they are cleared when a POR occurs. as driving signals to implement a charge-pump DC-DC converter (see Figure 23). latch and in the OTP anti-fuse element.
7.17 CFGI: configuration interface
Four pins of the device are dedicated to this purpose: SCS, SYN-NP , SCLNCN, SDATD. Table 16. Mode signals description
0 MOP and MON operate normally 0111001x 72 or 73
1 MOP and MON provide the driving signals to implement a
0 The 56 Configuration bits originated by OTP anti-fuses 0111101x 7A or 7B
1 The 56 Configuration bits originated by shadow latches 1111101x FA or FB
0 Any writing in the configuration bits is recorded in the shadow
1 Any writing in the configuration bits is recorded both in the
STPM11, STPM12, STPM13, STPM14 Theory of operation Doc ID 13167 Rev 8 31/46 The condition in which SCS, SYN-NP and SCL-NLC inputs are set to high level determines the idle state of the CFGI interface and no data transfer occurs. – SCS: in the STPM1X, the SYN-NP , SCL-NLC and SDA-TD have the dual task to provide information on the meter status (see Pin Description table) and to allow CFGI communication. The SCS pin allows using the above pins for CFGI communication when it is low and allows the normal operation of SYN-NP , SCL-NLC and SDA-TD when it is high. In this section, the SYN-NP , SCL-NLC and SDA-TD operation as part of the CFGI interface is described. – SYN-NP: this pin allows synchronization of the communication between STPM1x and the host. See Figure 21 - for detailed timing of the pin. – SCL-NLC: it is basically the clock pin of the CFGI interface. This pin function is also controlled by the SCS status. If SCS is low, SCL-NLC is the input of the serial bit synchronization clock signal. When SCS is high, SCL-NLC is also high which determines the idle state of the CFGI. – SDA-TD is the Data pin. SDA-TD is the input of the serial bit data signal. Any pin above has internal weak pull up device of nominal 15 A. This means that when a pin is not forced by external signals, the state of the pin is logic high. A high state of any input pin above is considered as an idle (not active) state. For the CFGI to operate correctly, the STPM1x must be correctly supplied as described in the power supply section. When SCS is active (low), signal SDA-TD should change its state at trailing edge of signal SCL-NLC and the signal SDA-TD should be stable at the next leading edge of signal SCL-NLC. The first valid bit of SDA-TD always starts with the activation of signal SCL-NLC. Writing procedure Each writable bit (configuration and mode bits) has its own 6-bit absolute address. For the configuration bits, the 6-bit address value corresponds to its decimal value, while for the mode bits, the addresses are the ones indicated in the Mode Signal paragraph (7.16). In order to change the latch state, a byte of data must be sent to STPM1x via CFGI. This byte consists of 1-bit data to be latched (msb), followed by 6-bit address of destination latch, followed by 1-bit don't care data (lsb) which totals 8 bits of command byte. For example, if we would like to set the configuration bit 52 (additional gain of 8) to 1, we must convert the decimal 52 to its 6-bit binary value: 110100. The byte command will be then composed like this: 1 bit DATA value+6-bits address+1 bit (0 or 1) as depicted in Figure 21. In this case the binary command will be 11101000 (0xE8) or 11101001 (0xE9). Obsolete Product(s) - Obsolete Product(s)
address must be taken from the Table 15. the device logic except from the signal POR. active signals SCS and SYN-NP . Figure 21. Timing for writing configuration and mode bits
STPM11, STPM12, STPM13, STPM14 Theory of operation Doc ID 13167 Rev 8 33/46 Permanent writing of the CFG bits In order to make a permanent set of some CFG bits, use the following procedure: 1. collect all addresses of CFG bits to be permanently set into a list; 2. clear all OTP shadow latches; 3. set the system signal RD; 4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP; 5. wait for VOTP voltage to be stable; 6. set one OTP shadow latch from the list; 7. set the system signal WE; 8. wait for 300 s; 9. clear the system signal WE; 10. clear the OTP shadow latch which was set in step 6; 11. until all CFG bits are permanently set as desired, repeat steps 5 to 11; 12. disconnect the current source; 13. wait for VOTP voltage to be less than 3 V; 14. clear the system signal RD; 15. verify the correct writing, testing STPM1x operation; 16. if the verification of CFG bits fails, repeat steps 1 to 16. For steps of set or clear, apply the timing shown in Figure 21 - with proper signal on the SDA-TD. In order to create a permanent set of the TSTD bit, which does not result in any more writing to the Configuration bits, the procedure above must be conducted in such a way that steps 6 to 13 are performed in series during a single period of active SCS. The idle state of SCS would make the signal TSTD immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal RD. This would result in the connecting of all gates of 3 V NMOS sense amplifiers of already permanently set CFG bits to the V OTP source. Obsolete Product(s) - Obsolete Product(s)
8 Energy calculation algorithm
performances in terms of accuracy. Figure 22. Active energy computation diagram
STPM11, STPM12, STPM13, STPM14 Energy calculation algorithm Doc ID 13167 Rev 8 35/46 In the STPM1x, after the pre-conditioning and the A/D conversion, the digital voltage signal (which is dynamically more stable with respect to the current signal) is processed by a differentiate stage which transforms: Equation 9 v(t) → v’(t) = dv/dt = V ⋅ ω ⋅ cos tω; (see [5] in Figure 22); The result, together with the pre-processed and digitalized current signal: Equation 10 i(t) = I ⋅ sin (tω + ϕ); (see [6] in Figure 22) can then be used to calculate. These digital signals are also used in two additional steps for integration, obtaining: Equation 11 dv/dt → v(t) = V ⋅ sin tω; (see [7] in Figure 22) Equation 12 (see [8] in Figure 22) Now four signals are available. Combining (pairing) them by two multiplication steps two results are obtained: Equation 13 (see [9] in Figure 22) Equation 14 (see [10] in Figure 22) After these two operations, another stage another step involves the subtraction of p1 from p2 and dividing the result by 2, to obtain the active power: Equation 15 (see [12] in Figure 22) In this way, the AC part )tcos(Idt)t(i)t(I ϕ+ω⋅ω−=⋅= ∫i(t) ⋅ )t2cos(IV cosIVdt)t(idt dv)t(p1 )t2cos(IV cosIV)t(i)t(v)t(p2 cosIV ))t(p)t(p()t(p 12 ϕ⋅⋅=/−/= Obsolete Product(s) - Obsolete Product(s)
Energy calculation algorithm ST PM11, STPM12, STPM13, STPM14 36/46 Doc ID 13167 Rev 8 Equation 16 has been then removed from the instantaneous power. In the case of current sensors like "Rogowski coils", which provide the rate of the instantaneous current signal, the initial voltage signal differentiation stage is switched off. In this case the signals coming from the A/D conversion and their consequent integrations are: Equation 17 v(t) = V ⋅ sin (tω); Equation 18 Equation 19 Equation 20 The signals process flow is the same as shown in the previous case, and even with the formulas above, the result is the same. The absence of any AC component allows a very fast calibration procedure. Averaging the readings of several line periods is not needed. The active energy measurement is already stable after one line cycle. Moreover the digital calibration allows saving time and space compared to the hardware calibration made with resistor strings. ⎛ ϕ+ω⋅⋅ )t2cos(IV )tcos(Idt )t(di)t(i ϕ+ω⋅ω⋅−==′ tcosVdt)t(v)t(V ω⋅ω−=⋅= ∫ )tsin(I)t(idt)t(i)t(i ϕ+ω⋅−==⋅′=′′ ∫ Obsolete Product(s) - Obsolete Product(s)
9 STPM1x calibration
is included to remove any signal DC component. Table 17. Calibration entries Table 18. Device calculation constants
err = 100(fx/f -1) [%], where fx is the real frequency read at LED output. R-768=127.755; while in this other one set CV=127; set CC=128. Table 19. Calibration results
STPM11, STPM12, STPM13, STPM14 STPM1x calibration Doc ID 13167 Rev 8 39/46 Note: STPM13/14: each current channel must be calibrated separately. In order to do this, follow these steps: Apply the nominal test voltage to the voltage sensor, and the nominal test current to the primary current channel sensor. Do not apply such current on the secondary current channel sensor. Adjust the voltage and primary current calibrators (see above). Disconnect the nominal test current from the primary current channel sensor, and apply it to the secondary current channel sensor. Adjust only the secondary current calibrators, so that the same power is computed. Obsolete Product(s) - Obsolete Product(s)
10 Schematic
Figure 23. Charge pump schematic
Figure 24. Application schematic
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Obsolete Product(s) - Obsolete Product(s)
Dim. mm. inch. A 1.2 0.047 b 0.19 0.30 0.007 0.012 c0 . 0 9 0.20 0.004 0.007 9 e 0.65 B SC 0.0256 B SC K0 ° 8°0 ° 8° TSSOP20 mechanical data c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 0087225C Obsolete Product(s) - Obsolete Product(s)
Dim. mm. inch. A 330 12. 992 C 12. 8 13.2 0.504 0.51 9 D 20.2 0.7 95 N6 0 2 . 362 T 22.4 0. 882 Ao 6. 8 7 0.26 8 0.276 Bo 6. 9 7.1 0.272 0.2 80 Ko 1.7 1. 9 0.067 0.075 Po 3.9 4.1 0.15 3 0.161 P 11. 9 12.1 0.46 8 0.476 Tape & reel TSSOP20 mechanical data Obsolete Product(s) - Obsolete Product(s)
Table 20. Document revision history 30-Jan-2007 1 Initial release. 06-Feb-2007 2 The Figure 11 has been changed. 20-Mar-2007 3 General description has been updated. 13-Sep-2007 4 Add Table 1 in cover page. 21-Jan-2008 5 Added Note: on page 39. 07-Apr-2009 6 Modified paragraph 7.14 on page 25. 16-Mar-2011 7 Modified Table 16 on page 30. 09-Jun-2011 8 Modified Section 7.1 on page 15.