STPM01 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Schematic diagram
- 2 Pin configuration
- 3 Maximum ratings
- 4 Functions
- 5 Electrical characteristics
- 6 Terminology
- 6.1 Measurement error
- 6.2 ADC Offset error
- 6.3 Gain error
- 6.4 Power supply DC and AC Rejection
- 6.5 Conventions
- 7 Typical performance characteristics
- 8 Theory of operation
- 8.1 General operation description
- 8.2 Analog inputs
- 8.4 Zero crossing detection
- 8.5 Period and line voltage measurement
- 8.6 Single wire meter mode (only Rogowsky coil sensor)
- 8.7 Power supply
- 8.8 Load monitoring
- 8.9 Error detection
- 8.10 Tamper detection module
- 8.10.1 Detailed operational description
- 8.10.2 Tamper state
- 8.11 Phase compensation
- 8.12 Clock generator
February 2007 Rev. 4 1/56 STPM01 Programmable single phase energy metering IC with tamper detection Feature summary ■ Active, reactive, apparent energies and RMS values ■ Ripple free active energy pulsed output ■ Live and neutral monitoring for tamper detection ■ Easy and fast digital calibration in only one point over the whole current range ■ OTP for calibration and configuration ■ Integrated linear VREGS for digital and analog supply ■ Selectable RC or crystal oscillator ■ Support 50÷60 HZ – IEC62052-11, IEC62053- 2x specification ■ Less than 0.1% error ■ Precision voltage reference: 1.23V and 30 ppm/°C Max
Description
The STPM01 is designed for effective measurement of active, reactive and apparent energy in a power line system using Rogowski Coil, Current Transformer and Shunt sensors. This device can be implemented as a single chip 1-phase energy meter or as a peripheral measurement in a microcontroller based 1-phase or 3-phase energy meter. The STPM01 consists, essentially, of two parts: the analog part and the digital part. The former, is composed by preamplifier and 1st order ∆ ∑ A/D converter blocks, Band gap voltage reference, Low drop voltage regulator, the latter, is composed by system control, oscillator, hard wired DSP and SPI interface. There is also an OTP block, which is controlled through the SPI by means of a dedicated command set. The configured bits are used for testing, configuration and calibration purpose. From a pair of ∆ ∑ output signals coming from analog section, a DSP unit computes the amount of consummated active, reactive and apparent energy, RMS and instantaneous values of voltage and current. The results of computation are available as pulse frequency and states on the digital outputs of the device or as data bits in a data stream, which can be read from the device by means of SPI interface. This system bus interface is used also during production testing of the device and/or for temporary or permanent programming of bits of internal OTP . In the STPM01 an output signal with pulse frequency proportional to energy is generated, this signal is used in the calibration phase of the energy meter application allowing a very easy approach. When the device is fully configured and calibrated, a dedicated bit of OTP block can be written permanently in order to prevent accidental entering into some test mode or changing any configuration bit. TSSOP20 Order code Part number Temperature range Package Packaging STPM01FTR -40 to 85 °C TSSOP20 (Tape & reel) 2500 parts per reel
1 Schematic diagram
Figure 1. Block diagram
2 Pin configuration
Figure 2. Pin connections (top view) Table 1. Pin description
1 MON P O Programmable output pin, see table 1
2 MOP P O Programmable output pin, see table 1
3 SCS D IN Digital input/output pin, see table 1
10 I IN1 A IN Negative input of primary current channel
11 I IP2 A IN Positive input of secondary current channel
12 I IN2 A IN Negative input of secondary current channel
13 V IP A IN Positive input of voltage channel
14 V IN A IN Negative input of voltage channel
15 SYN D I/O Programmable input/output pin, see table 1
16 CLKIN A IN Crystal oscillator input or resistor connection if RC oscillator is selected
17 CLKOUT A OUT Oscillator Output (RC or crystal)
18 SCL/NLC D I/O Programmable input/output pin, see table 1
19 SDA/TD D I/O Programmable input/output pin, see table 1
20 LED D O Programmable output pin, see table 1
- A: Analog, D: Digital, P: Power
3 Maximum ratings
Table 2. Absolute maximum ratings (See note) Table 3. Thermal Data
- This value is referred to single-layer PCB, JEDEC standard test board.
4 Functions
Table 4. Programmable pin functions MON Output for Stepper’s node (MB) If APL=0 then Watchdog signal. according to the value of KMOT configuration bit. value of KMOT configuration bit. secondary current channel is selected.
Table 5. Internal signal description the voltage channel is falling. Basically this signal is the sign of dv/dt. band. It is low when the voltage line frequency is inside the nominal band. register but is also available on the SCLNLC pin when in standalone mode. BIL=1 no load condition, BIL=0 normal operation.
5 Electrical characteristics
Table 6. Electrical characteristics
4 MHz, VCC = 5V 3 4
8 MHz, VCC = 5V 5 6
4 MHz, VCC = 5V 120
4 MHz, VCC = 5V 2
Table 7. Typical external components
6 Terminology
6.1 Measurement error
The error associated with the energy measurement made by the STPM01 is defined as: Percentage Error = [STPM01 (reading) - True Energy] / True Energy
6.2 ADC Offset error
This is the error due to the DC component associated with the analog inputs of the A/D converters. Due to the internal automatic DC offset cancellation the STPM01 measurement is not affected by DC components in voltage and current channel. The DC offset cancellation is implemented in the DSP .
6.3 Gain error
The gain error is gain due to the signal channel gain amplifiers. This is the difference between the measured ADC code and the ideal output code. The difference is expressed as percentage of the ideal code.
6.4 Power supply DC and AC Rejection
This parameter quantifies the STPM01 measurement error as a percentage of reading when the power supplies are varied. For the PSRRAC measurement, a reading at two nominal supplies voltages (3.3 and 5 V) is taken. A second reading is obtained with the same input signal levels when an ac (200 mVrms/100 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading. For the PSRRDC measurement, a reading at two nominal supplies voltages (3.3 and 5V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±10%. Any error introduced is again expressed as a percentage of the reading.
6.5 Conventions
The lowest analog and digital power supply voltage is named VSS which represent the system Ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. Sinking current means that the current is flowing into the pin and then it is positive. Sourcing current means that the current is flowing out of the pin and then it is negative. Timing specifications of signal treated by a digital control part are relative to CLKOUT. This signal is provided from the crystal oscillator of 4.194MHz nominal frequency or from the internal RC oscillator, eventually an external source of 4.194MHz or 8.192MHz can be used. Timing specifications of signals of the SPI interface are relative to the SCLNLC, there is no direct relationship between the clock (SCLNLC) of the SPI interface and the clock of the DSP block. A positive logic convention is used in all equations.
7 Typical performance characteristics
Figure 3. Supply current vs supply voltage, Figure 4. RC Oscillator frequency vs V CC, Figure 5. RC Oscillator: Frequency jitter vs Figure 6. Analog voltage regulator: Line - Figure 7. Digital voltage regulator: Line - load Figure 8. Voltage channel linearity at
STPM01 Theory of operation
8 Theory of operation
8.1 General operation description
The STPM01 is able to perform active, reactive and apparent energy measurements, RMS and instantaneous values for voltage and current, line frequency information. Most of the functions are fully programmable using internal configuration bits accessible through SPI interface. The most important configuration bits are the two Application bits (APL - see table 1 for configuration register). Using these bits the STPM01 can be programmed as peripheral (APL=0 or APL=1) in microcontroller based meter systems or as standalone meter device (APL=2 or APL=3). In standalone mode, the STPM01 is able to drive a stepper motor with the MOP and MON pins, while some of the SPI pins (see table 1) are used to provide information on tamper, no load and negative power. In peripheral mode, due to the fact that the stepper motor is not used, the MOP and MON pins are used to provide different information (see table 1), while the SPI pins are used to communicate with the microcontroller. The STPM01 includes internal registers that hold the useful information for the meter system. Two kinds of active energy are available: the total active energy that includes all harmonic content called type0 and the active energy limited to the 1st harmonic called type1. This last energy value is obtained filtering the type0 active energy. The resolution of both the two active energies is 20-bit. Reactive and Apparent energies are also available with a 20-bit resolution. STPM01 provides also the RMS values of voltage and current. Due to the modest dynamic variation of the voltage, the RMS value is stored with a resolution of 11bit. While the RMS current value has a resolution of 16bit. The momentary sampled value of voltage and current are available also with a resolution of 11 and 16 bit respectively. The line frequency value is stored with a resolution of 14 bits. Due to the proprietary energy computation algorithm, STPM01 calibration is very easy and fast allowing calibration in only one point over the whole current range. The calibration parameters are stored permanently in the OTP (one time programmable) cells, preventing calibration tampering.
8.2 Analog inputs
The STPM01 has one fully differential voltage input channel and two fully differential current input channels. The voltage channel consists of a differential amplifier with a gain of 4. The maximum differential input voltage for the voltage channel is ±0.3V. The two current channels are multiplexed (see tamper section for details) to provide a single input to a preamplifier with a gain of 4. The output of this preamplifier is connected to the input of a programmable gain amplifier (PGA) with possible gain selections of 2,4,6,8. The total gain of the current channels will be then 8, 16, 24, 32. The gain selections are made by writing to the gain register and it can be different for the two current channels. In case the tamper function is not used, the secondary current can be disabled.
which gives the benefit to avoid any offset compensation. that make possible avoiding any manual offset calibration on the analog inputs. Table 8. Gain of voltage and current channels Table 9. Configuration of current sensors
32 Shunt 3 X
has a resolution of 11bits for voltage channel and 16 bits for current channel.
8.4 Zero crossing detection
Figure 14. First order ∑ ∆ A/D Converter
8.5 Period and line voltage measurement
the status bit register (see table 12). repeated three times in a row, in order to set the error flag BFR. about the presence of the line voltage inside the meter. Figure 15. ZCR Signal
also set, all the energy computation is carried on as BFR was cleared. BFR error flag is also assembled as part of 8-bit status register.
8.6 Single wire meter mode (only Rogowsky coil sensor)
predefined value for computing the energy without sensing it. Figure 16. LIN and BFR signal
nominal voltage value according to the NOM configuration bits.
8.7 Power supply
capacitors must be located very close to the device. which give a high degree of immunity to false triggering due to noisy supplies. Table 10. Nominal voltage values
8.8 Load monitoring
signal is also available in the status bit BIL. below a given value. This value can be set with the LTCH configuration bits. In peripheral mode, the BIL signal can be accessed only through the SPI interface. Figure 17. Bandgap temperature variation Table 11. No load detection thresholds
Theory of operation STPM01
8.9 Error detection
In addition to the no load condition and the line frequency band, the integration of power can be suspended also due to detected error on the source signals. There are two kinds of error detection circuits involved. The first checks all the ∑ ∆ signals from the analog part if any is stacked at 1 or 0 within the 1/128 of fCLK period of observation. In case of detected error the corresponding ∑ ∆ signal is replaced with an idle ∑ ∆ signal, which represents a constant value 0. All error and other resolved flags are treated as bits of a device status and can be read out by means of SPI interface. Another error condition occurs if the MOP, MON and LED pin outputs signals are different from the internal signals that drive them. This can occur if some of this pin is forced to GND or to some other imposed voltage value. In this case the internal status bit PIN is activated providing the information that some hardware problem has been detected, for example the stepper motor has been mechanically blocked.
8.10 Tamper detection module
The STPM01 is able to measure the current in both live and neutral wire. This mechanism is adopted to implement anti-tamper function. If this function is selected (see Table 10), the live and neutral wire currents are monitored; when a difference between the two measurements is detected, the STPM01 enters the Tamper State, while when there is a very small difference between the two channels the STPM01 is in Normal state. In particular, both channels are not observed all the time, rather a time multiplex mechanism is used. During the observation time of the selected channel, its active energy is calculated. The detection of a tamper condition occurs when the absolute value of the difference between the two active energy values is greater than a certain percentage of the averaged energy during the activated tamper module. This percentage value can be selected between two different values (12.5% and 6.25%) according to the value of the configuration bit CRIT. The tamper condition will be detected when the following formula will be satisfied: EnergyCH1 - EnergyCH2 > K CRIT (EnergyCH1 + EnergyCH2)/2; where KCRIT can be 12.5% or 6.25%. The detection threshold is much higher than the accuracy difference of the current channels, which should be less than 0.2%, but, some headroom should be left for possible transition effect, due to accidental synchronism of actual load current change with the rhythm of taking the energy samples. The tamper circuit works if the energies associated with the two current channels will be both positive or negative, if the two energies will have different sign, the tamper will be on all the time however, the channel with the associated higher power will be selected for the final computation of energy. In single wire mode, the Apparent energy rather then the active is used for Tamper detection.
8.10.1 Detailed ope rational description
The meter is initially set to normal state, i.e. tamper not detected. In such state, we expect that the values of both load currents should not differ more than the accuracy difference of the channels does. For this reason, we can use an average value of currents of both
of 32:32 periods of line per channel. This means that for 32 periods of line voltage, i.e. another 32 periods of line voltage when the current of secondary channel is used instead.
8.10.2 Tamper state
Several cases of transition of the state are shown on the Figure below. Figure 18. Tamper conditions
Theory of operation STPM01 The detected tamper condition is stored in the BIT status bit. If BIT=0 tamper is not detected, if BIT=1 a tamper condition has been detected. In standalone mode the BIT flag is also available in the SDATD pin. When internal signals are not good enough to perform the computation, i.e. line period is out or range or ∑ ∆ signals from analog part are stacked at high or low logic level, or no load condition is activated, the tamper module is disabled and its state is preset to normal.
8.11 Phase compensation
The STPM01 is does not introduce any phase shift between voltage and current channel. However, the voltage and current signals come from transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The STPM01 provides a means of digitally calibrating these small phase errors through a introducing delays on the voltage or current signal. The amount of phase compensation can be set using the 4 bits of the phase calibration register (CPH). The default value of this register is at value of 0 which gives 0° phase compensation. When the 4 bits give a CPH of 15 (1111) the introduced compensation is +0.576°. This compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. The resolution step of the phase compensation is 0.038°.
8.12 Clock generator
All the internal timing of the STPM01 is based on the CLKOUT signal. This signal can be generated in three different ways: 1. RC: this oscillator mode can be selected using the RC configuration bit. If RC=1 the STPM01 will run using the RC oscillator. A resistor connected between CLKIN and Ground will set the RC current. For 4Mhz operation the suggested settling resistor is 12kΩ; The oscillator frequency can be compensated using the CRC configuration bit (see table 13) 2. Quartz: If RC=0 the oscillator will work with an external crystal. The suggested circuit is depicted in fig. 18; 3. External Clock: keeping RC=0, it is also possible to feed the CLKOUT pin with an external oscillator signal The clock generator is powered from analog supply and is responsible for two tasks. The first one is to retard the turn on of some function blocks after POR in order to help smooth start of external power supply circuitry by keeping off all major loads. The second task of the clock generator is to provide all necessary clocks for analog and digital parts. Within this task, the MDIV configuration bit is used to inform the device about the nominal frequency value of CLKOUT. Two nominal frequency ranges are expected, from
8.13 Resetting the STPM01
dedicated command (see SPI section for remote reset command details). a reset state for about 125ms after a reset condition. When the reset is performed through SPI no delayed turn on is generated. malfunction of metering device will be detected.
8.14 Energy to frequency conversion (standalone)
register and the number of pulses provided per each kWh (P) can be defined as. Figure 19. Different oscillator circuits (a): STPM12/14 with quartz; (b) STPM11/13; (c) STPM12/14
will have a fixed width of 31.25 ms. calibration time of the meter. while 0xFFFFF represents 8Wh.
8.15 Driving a stepper motor (standalone)
are possible for the driving signals according to the configuration bits LVS and KMOT. number of pulses of the LED P (see previous paragraph) pin with the following relationship:. Table 12. Different settings for led signal
1 P/128
2 P/32
3 P/256
Table 13. Configuration of Mop and Mon Pins
The mono-flop limits the length of the pulses according to the LVS bit value. them has only a half of selected frequency. in order to make the backward rotation direction of the motor. See the diagram below.. When a no-load condition is detected MOP and MON are held low.
8.16 Using STPM01 in microcontroller based meter (peripheral)
Figure 20. Positive energy or absolute computation energy (ABS=1) stepper driving signals Figure 21. Negative energy stepper driving signals
according to the description below. DDA voltage is below 2.5 V, but after VDDA goes above 2.5V this signal starts to run. be reset by metering device because it would exit from the sleep mode. channel is actually selected. Table 14. Led pin configuration in peripheral mode
0 AW Type 0 (1) P [kWh]
1 AW Type 1 (1) P [kWh]
2 RW P [kVARh]
3 SW P [kVAh]
- * Type0 is the Wide band Active Energy and Type1 is the f undamental Active Energy if FUND=0, if FUND=1 they are
8.17 Status bits
SDATD pin. All the other signals can be read only through SPI interface.
8.18 Programming the STPM01
makes total of 32 bits or 4 bytes. Table 15. Status bit description
0 BIL No load condition
2 BFR Line frequency range
3 BIT T amper condition
4 MUX Current channel selection
5 LIN T rend of the line voltage
LIN=0: line voltage is going from the minimum to the maximum value. LIN=1: line voltage is going from the maximum to the minimum value.
6 PIN Output pins check
output pin is forced to 1 or 0.
7 HLT Data Validity
HLT=0: the data records reading are valid.
configuring and programming the STPM01.
8.19 Configuration bits
paired elements, one is latch, the OTP shadow, and another is the OTP antifuse element. Figure 22. STPM01 Data records map
the CFG signals are used to keep certain configuration and calibration values of device. example, this is extensively exercised during production tests. interface. The procedure to write the configuration bits is described in the SPI section. Table 16. Configuration bits map
this bit set the way to compute the power. and type1 (first 20 bits of DFP register) active energy.
2 RESERVED
BGTC 2 Bandgap Temperature compensation bits. See figure 4 for details. 4-bit unsigned data for compensation of phase error, 0°+0.576°. compensation is 0°, when CPH=15 the compensation is 0.576°. 8-bit unsigned data for voltage channel calibration. 8-bit unsigned data for primary current channel calibration. 8-bit unsigned data for secondary current channel calibration.
8.20 Mode signals
command (RRR) is sent through SPI. 2-bit modifier of nominal voltage for Single Wire Meter.
- IMPORTANT: This Bit represents the MSB of the decimal value indicated in the description column.
long as the VOTP voltage reads more than 3V, the signal RD should be set. and in the OTP antifuse element. sent to STPM01 when the TSTD bit has been set. Table 17. Mode signals description
0 Reserved
0 MOP and MON operates normally 0111001x 72 or 73
1 MOP and MON provides the driving signals to implement a
3 Reserved
4 CSEL
0 The 56 Configuration bits originated by OTP antifuses 0111101x 7A or 7B
0 Any writing in the configuration bits is recorded in the
1 Any writing in the configuration bits is recorded both in the
Theory of operation STPM01
8.21 SPI Interface
The SPI interface supports a simple serial protocol, which is implemented in order to enable a communication between some master system (microcontroller or PC) and the device. Three tasks can be performed with this interface: - remote resetting the device, - reading data records, - writing the Mode bits and the configuration bits (temporarily or permanently); Four pins of the device are dedicated to this purpose: SCS, SYN, SCLNCN, SDATD. SCS, SYN and SCLNLC are all input pins while SDATD can be input or output according if the SPI is in write or read mode. A high level signal for these pins means a voltage level higher than 0.75xV CC, while a low level signal means a voltage value lower than 0.25xVCC. The internal register are not directly accessible, rather a 32bit of transmission latches are used to pre-load the data before being read or written to the internal registers. The condition in which SCS, SYN and SCLNLC inputs are set to high level determines the idle state of the SPI interface and no data transfer occurs. – SCS: as already described in the document, when STPM01 is in standalone mode, the SYN, SCLNLC and SDATD are used also for providing information on the meter status (see table 1) and are not used for SPI communication. The SCS pin allows using the above pins for SPI communication even when the STPM01 is working in standalone mode, in fact SCS pin enables SPI operation when low. In this section, the SYN, SCLNLC and SDATD operation as part of the SPI interface is described. – SYN: this pin operates different functions according to the status of SCS pin. When SCS is low the SYN pin status select if the SPI is in read (SYN=1) or write mode (SYN=0). When SCS is high and SYN is also high the results of the input or output data are transferred to the transmission latches. – SCLNLC: it is basically the clock pin of the SPI interface. This pin function is also controlled by the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal. When SCS is high, SCLNLC is also high determining the idle state of the SPI. – SDATD is the Data pin. If SCS is low, the operation of SDATD is dependent on the status of SYN pin. if SYN is high SDATD is the output of serial bit data (read mode) if SYN is low SDATD is the input of serial bit data signal (write mode). If SCS is high SDATD is input of idle signal. Any pin above has internal weak pull up device of nominal 15µA. This means that when some pin is not forced by external signals, the state of pin is logic high. A high state of any input pin above is considered as an idle (not active) state. For the SPI to operate correctly the STPM01 must be correctly supplied as described in the Power Supply section. Idle state of SPI module is recognized when the signals of pins SYN, SCS, SCLNLC and SDATD are in a logic high state. Any SPI operations should start from such idle state. The exception to this rule is when STPM01 has been put into mode of standalone application. In such mode it can happen that states of pins SCLNLC, SDATD and SYN are not high due to states of corresponding internal status bits. When SCS is active (low), signal SDATD should change its state at trailing edge of signal SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC. The first valid bit of SDATD is always started with activation of signal SCLNLC.
8.21.1 Remote Reset
the 30ms retard restart of analog module and the 120ms retard restart of digital module. This signal doesn’t clear the mode signals.
8.22 Reading data records
can be as short as 30ns. There are two phases of reading, called latching and shifting. measurement clock, i.e. more than 500ns at 4MHz. can be aborted at any time by deactivation of SCS (see figure 23). Figure 23. Timing for providing remote reset request
code rather than useful data. Figure 24. Data records reconstruction
incorrectly read one would be lost. is read out as least significant bit (lsb) first.
8.23 Writing procedure
mode bits the addresses are the ones indicated in the Mode Signal paragraph. makes total 8 bits of command byte. channel calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111. Figure 25. Timing for data records reading
address must be taken from the table 18. device logic except from the signal POR. Interfacing the standard 3-wire SPI with STPM01 SPI. Figure 26. Timing for writing configuration and mode bits
STPM01 Theory of operation state buffer could be omitted by an emulation of SPI just to send some command. On a microcontroller this would be done by the following steps: 1. disable the SPI module; 2. set SDI pin which is connected to SDATD to be output; 3. activate SYN first and then SCS; 4. apply new bit value to SDI and activate SCL; 5. deactivate SCL; 6. repeat the last two steps seven times to complete one byte transfer; 7. repeat the last three steps for any remaining byte transfer; 8. set SDI pin to be input; 9. deactivate SCS and the SYN; 10. enable the SPI module; In case of Precharge command (0xFF), emulation above is not necessary. Due to the pull up device on the SDATD pin of the STPM01 the processor needs to perform the following steps: 1. activate SYN first in order to latch the results; 2. after at least 1µs activate SCS; 3. write one byte to the transmitter of SPI (this will produce 8 pulses on SCL with SDI=1); 4. deactivate SYN; 5. optionally read the data records (the sequence of reading will be altered; 6. deactivate SCS; Permanent writing of the CFG bits In order to make a permanent set of some CFG bits, the following procedure should be conducted: 1. collect all addresses of CFG bits to be permanently set into some list; 2. clear all OTP shadow latches; 3. set the system signal RD; 4. connect a current source of at least +14V, 1mA to 3mA to VOTP; 5. wait for VOTP voltage is stable; 6. set one OTP shadow latch from the list; 7. set the system signal WE; 8. wait for 300µs; 9. clear the system signal WE; 10. clear the OTP shadow latch which was set in step 6; 11. until all wanted CFG bits are permanently set, repeat steps 5 to 11; 12. disconnect the current source; 13. wait for VOTP voltage is less than 3V; 14. clear the system signal RD; 15. read all data records, in the last two of them there is read back of CFG bits; 16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1 to 16. For steps of set or clear apply the timing shown in Figure 24 with proper signal on the SDATD. For step 15 apply the timing shown in Figure 23.
Theory of operation STPM01 For permanent set of the TSTD bit, which will cause no more writing to the Configuration bits, the procedure above must be conducted in such way that steps 6 to 13 are performed in series during single period of active SCS because the idle state of SCS would make the signal TSTD immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal RD and so, connecting all gates of 3V NMOS sense amplifiers of already permanently set CFG bits to the V OTP source.
8.24 Energy calculation algorithm
Inside the STPM01 the computing section of the measured active power uses a completely new signal patented process approach. This approach allows the device to reach high performances in terms of accuracy. The signals, coming from the sensors, for the instantaneous voltage: v(t) = Vsin ωt; where V is the peak voltage and ω is related to the line frequency (see[1]) and the instantaneous current: i(t) = I sin ( ωt + ϕ); where I is the peak current, ω is related to the line frequency and ϕ is the phase difference between voltage and current (see[2]).
8.24.1 Active power
Figure 27. Active energy computation diagram
Theory of operation STPM01 [Eq. 6 - see (9)] [Eq. 7 - see (10)] After these two operations, another stage performs the subtraction between the results p2 and p1 and a division by 2, obtaining the active power: [Eq. 8 - see (11)] In this way, the AC part VIcos(2ωt + ϕ)/2 has been then removed from the instantaneous power. In the case of current sensors like “Rogowski coils”, which provide the rate of the instantaneous current signal (di/dt), the initial voltage signal differentiated stage will be switched off. In this case the signals coming from the A/D conversion and their consequent integrations will be: v(t) = Vsin ωt [Eq. 9] [Eq. 10] [Eq. 11][ [Eq. 12] The signals process flow will be the same as shown in the previous case, and even with the formulas above, the result will be the same. The absence of any AC component allows a very fast calibration procedure: it requires just to set (using the internal device programming registers) the voltage and current sensor conversion constants, using the effective voltage and current (Vrms, Irms) readings provided by the device built-in communication port, avoiding the time-averaged readings of the active power or need for line synchronization.
8.24.2 Reactive power
The reactive power is produced using the already computed signals. In case of shunt sensor the voltage signal is derived while the current signal is not. A first computation is to multiply )2cos( cos)()(1 tIVIVdttidt dvtp )2cos( cos)()()(2 tIVIVtitvtp cos ))()(()( 12 ϕ⋅⋅=/−/= IVtptptp )cos()()( ϕωω +⋅⋅−==′ tIdt tditi tVdttvtV ωω cos)()( ⋅−=⋅= ∫ )sin()()()( ϕω +⋅−==⋅′=′′ ∫ tItidttiti
STPM01 Theory of operation DS value of integrated voltage channel with the value of integrated current channel, which yields: [Eq. 13] The second is to multiply filtered DS value of voltage channel with the value of filtered current channel, [Eq. 14] From the above results, Q1(t) is proportional to 1/ω while Q2(t) is proportional to ω. The correct reactive power would result from the following formula: [Eq. 15] Since the above computation would need significant additional circuitry, the Reactive Power in the STPM01 is calculated using only the Q1(t) multiplied by ω, it means: [Eq. 16] The Reactive Power will present then a ripple at twice the line frequency. Since the average value of a sinusoid is 0, this ripple does not contribute to the reactive energy calculation over time, moreover, in the STPM01 the reactive power is not used for meter calibration or to generate the stepper pulses, then this ripple will not affect the overall system performances. In case of Rogowsky coil, the same procedure is applied, but the current channel will be proportional to the derived of the current and the differentiated is bypassed in the voltage channel, so we have: [Eq. 17] [Eq. 18] The reactive power is then calculated: [Eq. 19] () )2sin(sin2cos()sin()()()()()(1 ϕωϕωϕωωω +−⋅=⎟ () )2sin(sin2)sin(cos)()()(2 ϕωϕωϕωωω ++⋅⋅=+⋅=⋅′= tVItItVtitvtQ ϕωω sin2 1)()(2 VItQtQQ =⋅+⋅⋅= () )2sin(sin2)(2 1)( 13 ϕωϕω +−⋅=⋅⋅= tVItQtQ () () )2sin(sin2)sin()cos()()()()()(1 ϕωϕωϕωωω ++=+−⋅⎟ () () )2sin(sin2)cos()(sin)()()(1 ϕωϕωϕωωω +−⋅⋅−=+−⋅=′⋅= tVItIttVtitvtQ () )2sin(sin2)(2 1)( 13 ϕωϕω ++⋅=⋅⋅= tVItQtQ
Theory of operation STPM01
8.24.3 Apparent power and RMS values
The RMS values are calculated starting from the following formulas. Shunt or Current Transformer [Eq. 20] multiplying Eq 20 by ω, the IRMS value is obtained: [Eq. 21] The RMS voltage value is obtained as: [Eq. 22] For the Apparent Power another value is produced: [Eq. 23] Multiplying Eq.20 and Eq. 23, the Apparent power is produced: [Eq. 24] Rogowsky Coil In this case we have: [Eq. 25] while VRMS is calculated as in Eq. 22. The Apparent Power is simple calculated multiplying Eq.25 and Eq. 22. The DSP then performs the integration of the computed powers into energies. These integrators are implemented as Up/Down counters and they can rollover. 20-bit output buses of the counters are assigned as most significant part of energy data records. It is a responsibility of an application to read the counters at least every second not to miss any rollover. )(1 =∫ ω IdttIT T IIRMS = )(1
2 VdttvTV
T RMS == ∫ )(1 2 ω⋅=′∫ VdttvT T 222 VIVIS =⋅⋅ = ω ω )(1
2 IdttiTI
T RMS =′′= ∫
9 STPM01 Calibration
Energy meters based on STPM01 device are calibrated in a fast and easy way. The calibration is essentially based on the single calibration of the voltage and current channel considering their RMS values rather than on the frequency of output pulse signal. When the two channel are calibrated all the other measurement are calibrated too. This allows the calibration to be performed in only one point shortening the production time of the meter. This procedure is possible due to the below key points: – Device is compound of two independent meter channels for line voltage and current respectively. Each channel includes its own digital calibrator, to adjust the RMS in the range of ±12.5% in 256 steps, and digital filter, to remove any signal DC component. All final results are not subject to calibration procedure because they are achieved from such corrected signals by mathematical modules implemented by hardwired DSP . – Device computes different kind of energies: active, reactive and apparent. The active energy is produced without 2nd harmonic of line frequency. It also computes rms values of measured voltage and current. – Device produces an energy output pulse signal but information can also be read through Serial Port Interface, SPI, and communication channel. – Device has an embedded memory, 56 bits, used for configuration and calibration purposes. The value of these bits can be read or they can be changed temporarily or permanently through SPI communication channel. Let’s consider the basic information needed to start the calibration procedure: The following typical STPM01 parameters and constants are also known: Table 18. Line RMS voltage V n (230V) Line RMS current I n (5A) Power sensitivity P (LED: P=128000 pulses/kWh, Stepper Motor: PM=P/64= 2000 pulses/kWh) Shunt Sensor K S 0,42 mv/A Table 19. Parameter Value Tolerance Internal reference voltage V BG 1.23 V ± 2% Internal Calculation Frequency f M 223 Hz ± 50 ppm Amplification of voltage ADC A V 4± 1 % Amplification of current ADC A I 8, 16, 24, 32 ± 2% Gain of differentiator G DIF 0,6135 Gain of integrator G INT 0,815 Gain of decimation filter G DF 1.004 RMS Voltage register length B V 211 RMS Current register length B I 216 Constant D UD 217
As shown in Tab. 19, only analog parameter are object of calibration because introduce a certain error. Voltage ADC amplification Av is constant, while Ai is chosen according to used sensors. The calibration algorithm will firstly calculate the voltage divider ratio and, as final result, the correction parameters, called Kv and Ki, which applied to STPM01 voltage and current measures compensate small tolerances of analog components that affect energy calculation. Since Kv and Ki calibration parameters are the decimal representation of the corresponding configuration bytes CHV and CHP or CHS (respectively voltage channel, primary current channel and secondary current channel calibration bytes), at the end of calibration CHV and CHP or CHS (according to the current channel under calibration, primary or secondary respectively) bits' values are obtained. In the following procedure CHV, CHP and CHS will be indicated as Cv and Ci. Through hardwired formulas Kv and Ki tune measured values varying from 0,75 to 1 in 256 steps, according to the value of Cv and Ci (from 0 to 255). To obtain the greatest correction dynamic initially calibrators are set in the middle of the range, thus obtaining a calibration range of 12.5% per voltage or current channel: Calibrator’s value Kv = Ki = 0.875 Ci = Cv = 128 In this way it is possible to tune Kv and Ki having a precise measured: for example Cv=0 generates a correction factor of -12.5% (Kv=0.75) and Cv=255 determines a correction factor of +12.5% (Kv=1), and so on. According to what pointed out above, the following formulas, which relate Kv,i and Cv,i are obtained: Cv,i = 1024 * Kv,i - 768. The calibration procedure will output Cv and Ci values that will allow the above power sensitivity of the meter. This sensitivity is used to calculate target frequency at LED pin for nominal voltage and current values: X F = f * 64; with: f = PM * In * Vn / 3600000; From values above and for both chosen amplification factor AI=32 and initial calibration data, the following target values can be calculated: Target RMS reading for given In: XI = In * KS * AI * Ki * GINT * GDF * GDIF * BI / (VBG * 1000)=1573 Target RMS reading for given Vn: XV = f * BV * BI * DUD / (fM * XI)=852 The output of the voltage divider is then:
VDIV = (XV * VBG)/ (2 * GDIF * AV * Kv * GDF * GINT * BV)= 145,6 mV Choosing R2=500Ω (connected between VI and VSS), the R1 resistor (connected between VLINE and VIP) value is obtained: R1 = R2 * (Vn - VDIV) / VDIV = 789,3 Ω Indicating with IA and VA the real readings on the STPM01 rms registers of voltage and current, and with XI and XV ideal values of RMS current and voltage readings already calculated, the final values for calibrators can be calculated as: XV = (Kv * VA) / 0.875 XI = (Ki * IA) / 0.875 If the computed final calibration data would fall out of calibration data range, the Energy Meter should be recognized as bad or the given presumptions and calculations above should be checked. Otherwise, if the final data of calibrators would be written into Energy Meter, the rms readings should be very close to target values I and V and the frequency of LED output should be very close to target value f.
10 Schematic
Figure 28. STPM01 Application with one current transformer and one shunt (see user manual
Figure 29. STPM01 with 3X charge pump DC/DC converter
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOP ACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
DIM. mm. inch A 1.2 0.047 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 e 0.65 BSC 0.0256 BSC K0 ˚ 8 ˚0 ˚ 8 ˚ TSSOP20 MECHANICAL DATA c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 0087225C
DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel TSSOP20 MECHANICAL DATA
Table 20. Revision history 28-Sep-2004 1 Preliminary Data. 22-Dec-2005 2 Document Updating. 24-Oct-2006 3 The chapter 9 has been updated and the document has been reformatted. 06-Feb-2006 4 The Figure 11. has been changed.