STPM01

Programmable single phase energy metering IC with tamper detection

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 60

Technical content

Datasheet sections

• 1 Schematic diagram
• 2 Pin configuration
• 3 Maximum ratings
• 4 Functions
• 5 Electrical characteristi cs
• 6 Terminology
• 6.1 Measurement error
• 6.2 ADC offset error
• 6.3 Gain error
• 6.4 Power supply DC and AC rejection
• 6.5 Conventions
• 7 Typical performance characteristi cs
• 8 Theory of operation
• 8.1 General operation description
• 8.2 Analog inputs
• 8.4 Zero crossing detection
• 8.5 Period and line voltage measurement
• 8.6 Single wire meter mode (only Rogowsky coil sensor)
• 8.7 Power supply
• 8.8 Load monitoring
• 8.9 Error detection
• 8.10 Tamper detection module
• 8.10.1 Detailed operational description
• 8.11 Phase compensation
• 8.12 Clock generator

Features

■ Active, reactive, apparent energies and RMS values ■ Ripple free active energy pulsed output ■ Live and neutral monitoring for tamper detection ■ Easy and fast digital calibration in only one point over the whole current range ■ OTP for calibration and configuration ■ Integrated linear VREGs for digital and analog supply ■ Selectable RC or crystal oscillator ■ Support 50 ÷ 60 Hz – IEC62052-11, IEC62053- 2x specification ■ Less than 0.1 % error ■ Precision voltage reference: 1.23 V and 30 ppm/°C max

Description

The STPM01 is designed for effective measurement of active, reactive and apparent energy in a power line system using Rogowski coil, current transformer and shunt sensors. This device can be implemented as a single chip monophase energy meter or as a peripheral measurement in a microcontroller based monophase or 3-phase energy meter. The STPM01 consists, essentially, of two parts: the analog part and the digital part. The former, is composed by preamplifier and 1 st order Δ ∑ A/D converter blocks, band gap voltage reference, low drop voltage regulator, the latter, is composed by system control, oscillator, hard wired DSP and SPI interface. There is also an OTP block, which is controlled through the SPI by means of a dedicated command set. The configured bits are used for testing, configuration and calibration purpose. From a pair of Δ ∑ output signals coming from analog section, a DSP unit computes the amount of consummated active, reactive and apparent energy, RMS and instantaneous values of voltage and current. The results of computation are available as pulse frequency and states on the digital outputs of the device or as data bits in a data stream, which can be read from the device by means of SPI interface. This system bus interface is used also during production testing of the device and/or for temporary or permanent programming of bits of internal OTP . In the STPM01 an output signal with pulse frequency proportional to energy is generated, this signal is used in the calibration phase of the energy meter application allowing a very easy approach. When the device is fully configured and calibrated, a dedicated bit of OTP block can be written permanently in order to prevent accidental entering into some test mode or changing any configuration bit. TSSOP20 Table 1. Device summary

1 Schematic diagram

Figure 1. Block diagram

2 Pin configuration

Figure 2. Pin connections (top view) Table 2. Pin description

1 MON P O Programmable output pin, see Table 5

2 MOP P O Programmable output pin, see Table 5

3 SCS D IN Digital input/output pin, see Table 5

10 I IN1 A IN Negative input of primary current channel

11 I IP2 A IN Positive input of secondary current channel

12 I IN2 A IN Negative input of secondary current channel

13 V IP A IN Positive input of voltage channel

14 V IN A IN Negative input of voltage channel

15 SYN D I/O Programmable input/output pin, see Table 5

16 CLKIN A IN Crystal oscillator input or resi stor connection if RC oscillator is selected

17 CLKOUT A OUT Oscillator Output (RC or crystal)

18 SCL/NLC D I/O Programmable input/output pin, see Table 5

19 SDA/TD D I/O Programmable input/output pin, see Table 5

20 LED D O Programmable output pin, see Table 5

1. A: Analog, D: Digital, P: Power

3 Maximum ratings

Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 3. Absolute maximum ratings Table 4. Thermal data

1. This value is referred to single-layer PCB, JEDEC standard test board.

4 Functions

Table 5. Programmable pin functions MON Output for Stepper’s node (MB) If APL=0 then Watchdog signal. according to the value of KMOT configuration bit. value of KMOT configuration bit. secondary current channel is selected.

Table 6. Internal signal description the voltage channel is falling. Basically this signal is the sign of dv/dt. nominal band or the voltage register is below 64. the voltage register goes above 128. register but is also available on the SCLNLC pin when in standalone mode. BIL=1 no load condition, BIL=0 normal operation.

5 Electrical characteristics

and VSS, 100 nF to 1 uF between VCC and VSS unless otherwise specified. Table 7. Electrical characteristics

4 MHz, VCC = 5V 3 4

8 MHz, VCC = 5V 5 6

4 MHz, VCC = 5V 120

4 MHz, VCC = 5V 2

Table 7. Electrical characteristics (continued)

6 Terminology

6.1 Measurement error

The error associated with the energy measurement made by the STPM01 is defined as: Percentage error = [STPM01 (reading) - true energy] / true energy

6.2 ADC offset error

This is the error due to the DC component associated with the analog inputs of the A/D converters. Due to the internal automatic DC offset cancellation the STPM01 measurement is not affected by DC components in voltage and current channel. The DC offset cancellation is implemented in the DSP .

6.3 Gain error

The gain error is gain due to the signal channel gain amplifiers. This is the difference between the measured ADC code and the ideal output code. The difference is expressed as percentage of the ideal code.

6.4 Power supply DC and AC rejection

This parameter quantifies the STPM01 measurement error as a percentage of reading when the power supplies are varied. For the PSRRAC measurement, a reading at two nominal supplies voltages (3.3 and 5 V) is taken. A second reading is obtained with the same input signal levels when an ac (200 mV RMS/100 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading. For the PSRRDC measurement, a reading at two nominal supplies voltages (3.3 and 5V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ± 10 %. Any error introduced is again expressed as a percentage of the reading.

6.5 Conventions

The lowest analog and digital power supply voltage is named VSS which represent the system ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. Sinking current means that the current is flowing into the pin and then it is positive. Sourcing current means that the current is flowing out of the pin and then it is negative. Timing specifications of signal treated by a digital control part are relative to CLKOUT. This signal is provided from the crystal oscillator of 4.194 MHz nominal frequency or from the internal RC oscillator, eventually an external source of 4.194 MHz or 8.192 MHz can be used. Timing specifications of signals of the SPI interface are relative to the SCLNLC, there is no direct relationship between the clock (SCLNLC) of the SPI interface and the clock of the DSP block. A positive logic convention is used in all equations.

7 Typical performance characteristics

Figure 3. Supply current vs. supply voltage, Figure 4. RC oscillator frequency vs. V CC, Figure 5. RC oscillator: frequency jitter vs. Figure 6. Analog voltage regulator: line - load Figure 7. Digital voltage regulator: line - load Figure 8. Voltage channel linearity at

STPM01 Theory of operation Doc ID 10853 Rev 8 17/60

8 Theory of operation

8.1 General operation description

The STPM01 is able to perform active, reactive and apparent energy measurements, RMS and instantaneous values for voltage and current, line frequency information. Most of the functions are fully programmable using internal configuration bits accessible through SPI interface. The most important configuration bits are the two application bits (APL - see Table 16 for configuration register). Using these bits the STPM01 can be programmed as peripheral (APL = 0 or APL = 1) in microcontroller based meter systems or as standalone meter device (APL = 2 or APL = 3). In standalone mode, the STPM01 is able to drive a stepper motor with the MOP and MON pins, while some of the SPI pins (see Table 5) are used to provide information on tamper, no load and negative power. In peripheral mode, due to the fact that the stepper motor is not used, the MOP and MON pins are used to provide different information (see Table 5), while the SPI pins are used to communicate with the microcontroller. The STPM01 includes internal registers that hold the useful information for the meter system. Two kinds of active energy are available: the total active energy that includes all harmonic content called type 0 and the active energy limited to the 1st harmonic called type 1. This last energy value is obtained filtering the type 0 active energy. The resolution of both the two active energies is 20-bit. Reactive and Apparent energies are also available with a 20-bit resolution. STPM01 provides also the RMS values of voltage and current. Due to the modest dynamic variation of the voltage, the RMS value is stored with a resolution of 11 bit. While the RMS current value has a resolution of 16 bit. The momentary sampled value of voltage and current are available also with a resolution of 11 and 16 bit respectively. The line frequency value is stored with a resolution of 14 bits. Due to the proprietary energy computation algorithm, STPM01 calibration is very easy and fast allowing calibration in only one point over the whole current range. The calibration parameters are stored permanently in the OTP (one time programmable) cells, preventing calibration tampering.

8.2 Analog inputs

The STPM01 has one fully differential voltage input channel and two fully differential current input channels. The voltage channel consists of a differential amplifier with a gain of 4. The maximum differential input voltage for the voltage channel is ± 0.3 V. The two current channels are multiplexed (see tamper section for details) to provide a single input to a preamplifier with a gain of 4. The output of this preamplifier is connected to the input of a programmable gain amplifier (PGA) with possible gain selections of 2, 4, 6, 8. The total gain of the current channels are then 8, 16, 24, 32. The gain selections are made by writing to the gain register and it can be different for the two current channels. In case the tamper function is not used, the secondary current can be disabled.

with Shunt), the shunt Ks must always be equal to one fourth of the current transformer Ks. which gives the benefit to avoid any offset compensation. cancellation that make possible avoiding any manual offset calibration on the analog inputs. Table 8. Gain of voltage and current channels Table 9. Configuration of current sensors

32 Shunt 3 X

8.4 Zero crossing detection

Figure 14. First order ∑ Δ A/D converter

8.5 Period and line voltage measurement

on the status bit register (see Table 15). lower than fCLK/217 Hz and a BFR (base frequency range) error flag is set. must be repeated three consecutive times in order to set the BFR error flag. When the line frequency re-enters the nominal band, the BFR flag is automatically reset. This BFR error flag is also assembled as part of the 8-bit status register (see Table 15). Figure 15. ZCR signal

about the presence of the line voltage within the meter. single wire mode operation is selected (see Section 8.6). In fact, the effect of the BFR bit can be overridden by setting FRS configuration bit. because voltage RMS register value is below 64).

8.6 Single wire meter mode (only Rogowsky coil sensor)

Figure 16. LIN and BFR signal

predefined value for computing the energy without sensing it. nominal voltage value according to the NOM configuration bits.

8.7 Power supply

the necessary voltage for the analog part VDDA (3 V) and for the digital part VDDD (1.5 V). Table 10. Nominal voltage values

these capacitors must be located very close to the device. which give a high degree of immunity to false triggering due to noisy supplies.

8.8 Load monitoring

signal is also available in the status bit BIL. below a given value. This value can be set with the LTCH configuration bits. Figure 17. Bandgap temperature variation Table 11. No load detection thresholds

Theory of operation STPM01 24/60 Doc ID 10853 Rev 8 When a no load condition occurs (BIL=1) the integration of power is suspended and the tamper module is disabled. In standalone mode, if a no load condition is detected, the BIL signal blocks generation of pulses for stepper and forces SCLNLC pin to be low. If APL = 2 (see Section 8.14) the LED pin continues providing the high frequency pulses, while if APL = 3, the pulses are stopped as happens for MOP and MON. In peripheral mode, the BIL signal can be accessed only through the SPI interface.

8.9 Error detection

In addition to the no load condition and the line frequency band, the integration of power can be suspended also due to detected error on the source signals. There are two kinds of error detection circuits involved. The first checks all the ∑ Δ signals from the analog part if any is stacked at 1 or 0 within the 1/128 of fCLK period of observation. In case of detected error the corresponding ∑ Δ signal is replaced with an idle ∑ Δ signal, which represents a constant value 0. All error and other resolved flags are treated as bits of a device status and can be read out by means of SPI interface. Another error condition occurs if the MOP, MON and LED pin outputs signals are different from the internal signals that drive them. This can occur if some of this pin is forced to GND or to some other imposed voltage value. In this case the internal status bit PIN is activated providing the information that some hardware problem has been detected, for example the stepper motor has been mechanically blocked.

8.10 Tamper detection module

The STPM01 is able to measure the current in both live and neutral wire with a time domain multiplexing approach on a unique sigma delta modulator. This mechanism is adopted to implement anti-tamper function. If this function is selected (see Table 9), the live and neutral wire currents are monitored; when the difference between the two measurements exceeds a rated threshold the STPM01 enters the "tamper state", while in "normal state" the two measurements are below the threshold. In particular, both channels are not observed all the time, rather a time multiplex mechanism is used. During the observation time of each channel, its active energy is calculated. A tamper condition occurs when the absolute value of the difference between the two active energy values is greater than a certain percentage of the averaged energy during the activated tamper module (see Equation 1: ). This percentage value can be selected between two different values (12.5 % and 6.25 %) according to the value of the configuration bit CRIT. The tamper condition is detected when the following formula is satisfied: Equation 1 EnergyCH1 - EnergyCH2 > K CRIT (EnergyCH1 + EnergyCH2)/2; where KCRIT can be 12.5 % or 6.25 %. The detection threshold is much higher than the accuracy difference of the current channels, which should be less than 0.2 %, but, some headroom should be left for possible transition effect, due to accidental synchronism of actual load current change with the rhythm of taking the energy samples.

In single wire mode, the apparent energy rather than the active is used for tamper detection. condition is activated, the tamper module is disabled and its state is preset to normal.

8.10.1 Detailed operational description

load currents should not differ more than the accuracy difference of the channels does. Sixty-four periods of line voltage is used as a tamper checking period. selected channel but the frozen values. switched back to primary current channel and the integration for tamper detection is started. The timings of MUX and INH signals are shown in Figure 18 below. MUX and INH signals change according to Figure 19 below. Figure 18. Timings of tamper module - Primary channel selected Figure 19. Timings of tamper module - Secondary channel selected

Theory of operation STPM01 26/60 Doc ID 10853 Rev 8 samples, called B and A respectively, the criteria of tamper is calculated and the channel with higher current is selected, resulting in a new tamper state. If four consecutive new results of criteria happen, i.e. after elapsed 5.12 s at 50 Hz, the meter will enter into tamper state. Thus, the channel with the higher current will be selected for the energy calculation. If samples of power A and B would have different signs, the Tamper would be on all the time but, the channel with bigger power would be still selected for the final integration of energy. If a tamper status has been detected, the multiplex ratio will be 56:8 if the primary channel energy is greater than the secondary one, otherwise it will be 8:56. The detected tamper condition is stored in the BIT status bit. If BIT = 0 tamper is not detected, if BIT = 1 a tamper condition has been detected. In standalone mode the BIT flag is also available in the SDATD pin.

8.11 Phase compensation

The STPM01 is does not introduce any phase shift between voltage and current channel. However, the voltage and current signals come from transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The STPM01 provides a means of digitally calibrating these small phase errors through a introducing delays on the voltage or current signal. The amount of phase compensation can be set using the 4 bits of the phase calibration register (CPH). The default value of this register is at value of 0 which gives 0° phase compensation. When the 4 bits give a CPH of 15 (1111) the introduced compensation is +0.576°. This compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. The resolution step of the phase compensation is 0.038°.

8.12 Clock generator

All the internal timing of the STPM01 is based on the CLKOUT signal. This signal can be generated in three different ways: 1. RC: this oscillator mode can be selected us ing the RC configuration bit. If RC = 1 the STPM01 will run using the RC oscillator. A resistor connected between CLKIN and ground will set the RC current. For 4 MHz operation the suggested settling resistor is 12 kΩ; The oscillator frequency can be compensated using the CRC configuration bit (see Table 16) 2. Quartz: If RC = 0 the oscillator will work wit h an external crystal. The suggested circuit is depicted in Figure 20; 3. External clock: keeping RC=0, it is also possible to feed the CLKOUT pin with an external oscillator signal The clock generator is powered from analog supply and is responsible for two tasks. The first one is to retard the turn on of some function blocks after POR in order to help smooth start of external power supply circuitry by keeping off all major loads. The second task of the clock generator is to provide all necessary clocks for analog and digital parts. Within this task, the MDIV configuration bit is used to inform the device about

8.12.1 RC Startup procedure

To use the device with RC oscillator the configuration bit RC (see Table 16) must be set. the DSP is inactive. In this condition it is not possible to set RC or any other configuration bit.

• Set the mode signal BANK;
• Perform a software reset;
• Read the registers: BANK mode signal should be checked and the records should show something (not 000000F0);
• Set the mode signal RD;
• Read the registers through SPI just to check that RD mode signal has been set;
• Clear the mode signal BANK;
• DO NOT perform a reading, and write configuration bit RC; In this way the RC oscillator is started. If the registers are read again, it can be seen that RD and RC bits are set, and BANK is cleared. Once the RC startup procedure is complete, the device is clocked and active and it is possible to permanently write the RC bit. For details on mode signals refer to Chapter 8.20, for SPI operations refer to Chapter 8.21.

Figure 20. Different oscillator circuits (a): with quartz; (b): internal oscillator; (c): with external

8.13 Resetting the STPM01

dedicated command (see SPI section for remote reset command details). in a reset state for about 125 ms after a reset condition. When the reset is performed through SPI no delayed turn on is generated. the OTP shadow latches (see paragraph 16 for OTP shadow latches description). malfunction of metering device will be detected.

8.14 Energy to frequency conversion (standalone)

register and the number of pulses provided per each kWh (P) can be defined as. will have a fixed width of 31.25 ms. calibration time of the meter. Table 12. Different settings for LED signal

1 P/128

2 P/32

3 P/256

while 0xFFFFF represents 8 Wh.

8.15 Driving a stepper motor (standalone)

are possible for the driving signals according to the configuration bits LVS and KMOT. The mono-flop limits the length of the pulses according to the LVS bit value. them has only a half of selected frequency. Table 13. Configuration of MOP and MON pins

When a no-load condition is detected MOP and MON are held low.

8.16 Using STPM01 in microcontr oller based meter (peripheral)

according to the description below. DDA voltage is below 2.5 V, but after VDDA goes above 2.5 V this signal starts to run. Figure 21. Positive energy stepper driving signals Figure 22. Negative energy stepper driving signals

be reset by metering device because it would exit from the sleep mode. channel is actually selected.

8.17 Status bits

Table 14. LED pin configuration in peripheral mode

0 AW Type 0 (1) P [kWh]

1 AW Type 1 (1) P [kWh]

3 SW P [kVAh]

1. * Type0 is the Wide band Active Energy and Type1 is the fundam ental Active Energy if FUND=0, if FUND=1 they are

SDATD pin. All the other signals can be read only through SPI interface.

8.18 Programming the STPM01

makes total of 32 bits or 4 bytes. Table 15. Status bit description

0 BIL No load condition

2 BFR Line frequency range

3 BIT Tamper condition

4 MUX Current channel selection

5 LIN Trend of the line voltage

LIN=0: line voltage is going from the minimum to the maximum value. LIN=1: line voltage is going from the maximum to the minimum value.

6 PIN Output pins check

output pin is forced to 1 or 0.

7 HLT Data Validity

HLT=0: the data records reading are valid.

configuring and programming the STPM01.

8.19 Configuration bits

paired elements, one is latch, the OTP shadow, and another is the OTP antifuse element. the CFG signals are used to keep certain configuration and calibration values of device. Figure 23. STPM01 data records map

example, this is extensively exercised during production tests. interface. The procedure to write the configuration bits is described in the SPI section. Table 16. Configuration bits map

and type1 (first 20 bits of DFP register) active energy. Table 16. Configuration bits map (continued)

2 RESERVED

BGTC 2 Bandgap Temperature compensation bits. See Figure 17 for details. 4-bit unsigned data for compensation of phase error, 0°+0.576°. compensation is 0°, when CPH=15 the compensation is 0.576°. 8-bit unsigned data for voltage channel calibration. 8-bit unsigned data for primary current channel calibration. 8-bit unsigned data for secondary current channel calibration.

8.20 Mode signals

command (RRR) is sent through SPI. 2-bit unsigned data for calibration of RC oscillator. 2-bit modifier of nominal voltage for Single Wire Meter.

1. IMPORTANT: This bit represents the MSB of the decimal value indicated in the description column.

long as the VOTP voltage reads more than 3 V, the signal RD should be set. and in the OTP antifuse element. sent to STPM01 when the TSTD bit has been set. Table 17. Mode signals description

0 BANK

0 MOP and MON operates normally 0111001x 72 or 73

1 MOP and MON provides the driving signals to implement a

3 Reserved

4 CSEL

0 Current Channel 1 selected when tamper is disabled 0111100x 78 or 79

1 Channel 2 selected when tamper is disabled 1111100x F8 or F9

0 The 56 Configuration bits originated by OTP antifuses 0111101x 7A or 7B

1 The 56 Configuration bits originated by shadow latches 1111101x FA or FB

0 Any writing in the configuration bits is recorded in the

1 Any writing in the configuration bits is recorded both in the

STPM01 Theory of operation Doc ID 10853 Rev 8 39/60 – BANK: it is used to activate RC oscillator (see Chapter 8.12.1).

8.21 SPI interface

The SPI interface supports a simple serial protocol, which is implemented in order to enable a communication between some master system (microcontroller or PC) and the device. Three tasks can be performed with this interface: - remote resetting the device, - reading data records, - writing the Mode bits and the configuration bits (temporarily or permanently); Four pins of the device are dedicated to this purpose: SCS, SYN, SCLNCN, SDATD. SCS, SYN and SCLNLC are all input pins while SDATD can be input or output according if the SPI is in write or read mode. A high level signal for these pins means a voltage level higher than 0.75 x V CC, while a low level signal means a voltage value lower than 0.25 x VCC. The internal register are not directly accessible, rather a 32 bit of transmission latches are used to pre-load the data before being read or written to the internal registers. The condition in which SCS, SYN and SCLNLC inputs are set to high level determines the idle state of the SPI interface and no data transfer occurs. – SCS: as already described in the document, when STPM01 is in standalone mode, the SYN, SCLNLC and SDATD are used also for providing information on the meter status (see Table 5) and are not used for SPI communication. The SCS pin allows using the above pins for SPI communication even when the STPM01 is working in standalone mode, in fact SCS pin enables SPI operation when low. In this section, the SYN, SCLNLC and SDATD operation as part of the SPI interface is described. – SYN: this pin operates different functions according to the status of SCS pin. When SCS is low the SYN pin status select if the SPI is in read (SYN=1) or write mode (SYN=0). When SCS is high and SYN is also high the results of the input or output data are transferred to the transmission latches. – SCLNLC: it is basically the clock pin of the SPI interface. This pin function is also controlled by the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal. When SCS is high, SCLNLC is also high determining the idle state of the SPI. – SDATD is the Data pin. If SCS is low, the operation of SDATD is dependent on the status of SYN pin. if SYN is high SDATD is the output of serial bit data (read mode) if SYN is low SDATD is the input of serial bit data signal (write mode). If SCS is high SDATD is input of idle signal. Any pin above has internal weak pull up device of nominal 15 µA. This means that when some pin is not forced by external signals, the state of pin is logic high. A high state of any input pin above is considered as an idle (not active) state. For the SPI to operate correctly the STPM01 must be correctly supplied as described in the power supply section. Idle state of SPI module is recognized when the signals of pins SYN, SCS, SCLNLC and SDATD are in a logic high state. Any SPI operations should start from such idle state. The exception to this rule is when STPM01 has been put into mode of standalone application. In such mode it can happen that states of pins SCLNLC, SDATD and SYN are not high due to states of corresponding internal status bits. When SCS is active (low), signal SDATD should change its state at trailing edge of signal SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC. The first valid bit of SDATD is always started with activation of signal SCLNLC.

8.21.1 Remote reset

the 30 ms retard restart of analog module and the 120 ms retard restart of digital module. This signal doesn’t clear the mode signals.

8.22 Reading data records

can be as short as 30 ns. There are two phases of reading, called latching and shifting. measurement clock, i.e. more than 500 ns at 4 MHz. can be aborted at any time by deactivation of SCS (see Figure 24). Figure 24. Timing for providing remote reset request

1. All the time intervals must be longer than 30 ns. t 7 → t8 is the reset time, this interval must be longer than 30 ns as well.

incorrectly read one would be lost. byte is read out as least significant bit (LSB) first.

8.23 Writing procedure

mode bits the addresses are the ones indicated in the Mode Signal paragraph. makes total 8 bits of command byte. channel calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111. Figure 27. Timing for writing configuration and mode bits

STPM01 Theory of operation Doc ID 10853 Rev 8 43/60 t1 → t2 (> 30 ns): SPI out of idle state t2 → t3 (> 30 ns): SPI enabled for write operation t3: data value is placed in SDA t4: SDA value is stable and shifted into the device t3 → t5 (> 10 µs): writing clock period t3 → t5: 1 bit data value t5 → t6: 6 bits address of the destination latch t6 → t7: 1 bit EXE command t8: end of SPI writing t9: SPI enters idle state The same procedure should be applied for the mode signals, but in this case the 6-bits address must be taken from the Table 17. The LSB of command is also called EXE bit because instead of data bit value, the corresponding serial clock pulse is used to generate the necessary latching signal. This way the writing mechanism does not need the measurement clock in order to operate, which makes the operation of SPI module of STPM01 completely independent from the rest of device logic except from the signal POR. Commands for changing system signals should be sent during active signals SCS and SYN as it is shown in the Figure 27. The SYN must be put low in order to disable SDATD output driver of STPM01 and make the SDATD as an input pin. A string of commands can be send within one period of active signals SCS and SYN or command can be followed by reading the data record but, in this case, the SYN should be deactivated in order to enable SDATD output driver and a SYN pulse should be applied before activation of SCS in order to latch the data. Interfacing the standard 3-wire SPI with STPM01 SPI. Due to the fact a 2-wire SPI is implemented in STPM01 it is clear that sending any command from a standard 3-wire SPI would require 3-wire to 2-wire interface, which should produce a proper signal on SDATD from host signals SDI, SDO and SYN. A single gate 3- state buffer could be omitted by an emulation of SPI just to send some command. On a microcontroller this would be done by the following steps: 1. disable the SPI module; 2. set SDI pin which is connected to SDATD to be output; 3. activate SYN first and then SCS; 4. apply new bit value to SDI and activate SCL; 5. deactivate SCL; 6. repeat the last two steps seven times to complete one byte transfer; 7. repeat the last three steps for any remaining byte transfer; 8. set SDI pin to be input; 9. deactivate SCS and the SYN; 10. enable the SPI module; In case of precharge command (0xFF), emulation above is not necessary. Due to the pull up device on the SDATD pin of the STPM01 the processor needs to perform the following steps:

Theory of operation STPM01 44/60 Doc ID 10853 Rev 8 1. activate SYN first in order to latch the results; 2. after at least 1µs activate SCS; 3. write one byte to the tran smitter of SPI (this will produce 8 pulses on SCL with SDI=1); 4. deactivate SYN; 5. optionally read the data records (the sequence of reading will be altered; 6. deactivate SCS; Permanent writing of the CFG bits In order to make a permanent set of some CFG bits, the following procedure should be conducted: 1. collect all addresses of CFG bits to be permanently set into some list; 2. clear all OTP shadow latches; 3. set the system signal RD; 4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP; 5. wait for VOTP voltage is stable; 6. set one OTP shadow latch from the list; 7. set the system signal WE; 8. wait for 300 µs; 9. clear the system signal WE; 10. clear the OTP shadow latch which was set in step 6; 11. until all wanted CFG bits are permanently set, repeat steps 5 to 11; 12. disconnect the current source; 13. wait for VOTP voltage is less than 3 V; 14. clear the system signal RD; 15. read all data records, in the last two of them there is read back of CFG bits; 16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1 to 16. For steps of set or clear apply the timing shown in Figure 27 with proper signal on the SDATD. For step 15 apply the timing shown in Figure 26. For permanent set of the TSTD bit, which will cause no more writing to the Configuration bits, the procedure above must be conducted in such way that steps 6 to 13 are performed in series during single period of active SCS because the idle state of SCS would make the signal TSTD immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal RD and so, connecting all gates of 3V NMOS sense amplifiers of already permanently set CFG bits to the V OTP source.

8.24 Energy calculation algorithm

Inside the STPM01 the computing section of the measured active power uses a completely new signal patented process approach. This approach allows the device to reach high performances in terms of accuracy. The signals, coming from the sensors, for the instantaneous voltage: Equation 2 v(t) = Vsin ωt; where V is the peak voltage and ω is related to the line frequency and the instantaneous current:

between voltage and current.

8.24.1 Active power

Figure 28. Active energy computation diagram

Theory of operation STPM01 46/60 Doc ID 10853 Rev 8 Equation 6 dv/dt → v(t) = V ⋅sin ωt; [see Figure 28 - 7] i(t) → [see Figure 28 - 8] Now four signals are available. Combining (pairing) them by means of two multiplying stages two results are obtained: Equation 7 [see Figure 28 - 9] Equation 8 [see Figure 28 - 10] After these two operations, another stage performs the subtraction between the results p2 and p1 and a division by 2, obtaining the active power: Equation 9 [see Figure 28 - 11] In this way, the AC part VIcos(2ωt + ϕ)/2 has been then removed from the instantaneous power. In the case of current sensors like “Rogowski coils”, which provide the rate of the instantaneous current signal (di/dt), the initial voltage signal differentiated stage will be switched off. In this case the signals coming from the A/D conversion and their consequent integrations will be: Equation 10 v(t) = Vsin ωt )tcos(Idt)t(i)t(I ϕ+ω⋅ω−=⋅= ∫ )t2cos(IV cosIVdt)t(idt dv)t(p1 )t2cos(IV cosIV)t(i)t(v)t(p2 cosIV ))t(p)t(p()t(p 12 ϕ⋅⋅=/−/= )tcos(Idt )t(di)t(i ϕ+ω⋅ω⋅−==′

STPM01 Theory of operation Doc ID 10853 Rev 8 47/60 Equation 11 Equation 12 The signals process flow will be the same as shown in the previous case, and even with the formulas above, the result will be the same. The absence of any AC component allows a very fast calibration procedure: it requires just to set (using the internal device programming registers) the voltage and current sensor conversion constants, using the effective voltage and current (V RMS, IRMS) readings provided by the device built-in communication port, avoiding the time-averaged readings of the active power or need for line synchronization.

8.24.2 Reactive power

The reactive power is produced using the already computed signals. In case of shunt sensor the voltage signal is derived while the current signal is not. A first computation is to multiply DS value of integrated voltage channel with the value of integrated current channel, which yields: Equation 13 The second is to multiply filtered DS value of voltage channel with the value of filtered current channel, Equation 14 From the above results, Q1(t) is proportional to 1/ ω while Q2(t) is proportional to ω. The correct reactive power would result from the following formula: Equation 15 Since the above computation would need significant additional circuitry, the Reactive Power in the STPM01 is calculated using only the Q1(t) multiplied by ω, it means: tcosVdt)t(v)t(V ω⋅ω−=⋅= ∫ )tsin(I)t(idt)t(i)t( ϕ+ω⋅−==⋅′= ∫ () )t2sin(sin2 VItcos(I)tsinV()t(I)t(v)t(Idt)t(v)t(Q1 ϕ+ω−ϕ⋅ω=⎟ () )t2sin(sin2 VI)tsin(ItcosV)t(i)t(v)t(Q2 ϕ+ω+ϕ⋅ω⋅=ϕ+ω⋅ωω=⋅′= ϕ=ω⋅+ω⋅⋅= sin2 VI1)t(Q)t(Q2 1Q 21

Theory of operation STPM01 48/60 Doc ID 10853 Rev 8 Equation 16 The reactive power will present then a ripple at twice the line frequency. Since the average value of a sinusoid is 0, this ripple does not contribute to the reactive energy calculation over time, moreover, in the STPM01 the reactive power is not used for meter calibration or to generate the stepper pulses, then this ripple will not affect the overall system performances. In case of Rogowsky coil, the same procedure is applied, but the current channel will be proportional to the derived of the current and the differentiated is bypassed in the voltage channel, so we have: Equation 17 Equation 18 The reactive power is then calculated: Equation 19

8.24.3 Apparent power and RMS values

The RMS values are calculated starting from the following formulas. Shunt or current transformer Equation 20 multiplying Equation 20 by ω, the IRMS value is obtained: () )t2sin(sin2 VI)t(Q2 1)t(Q 13 ϕ+ω−ϕ⋅=ω⋅⋅= () () )t2sin(sin2 VI)tsin(I)tcos(V)t(i)t(Vdt)t(idt)t(v)t(Q1 ϕ+ω+ϕω=ϕ+ω−⋅⎟ () () )t2sin(sin2 VI)tcos(I)t(tsinV)t(i)t(v)t(Q1 ϕ+ω−ϕ⋅ω⋅−=ϕ+ωω−⋅ω=′⋅= () )t2sin(sin2 VI)t(Q2 1)t(Q 13 ϕ+ω+ϕ⋅=ω⋅⋅= Idt)t(IT T

STPM01 Theory of operation Doc ID 10853 Rev 8 49/60 Equation 21 The RMS voltage value is obtained as: Equation 22 For the apparent power another value is produced: Equation 23 Multiplying Equation 20: and Equation 23: , the apparent power is produced: Equation 24 Rogowsky coil In this case we have: Equation 25 while VRMS is calculated as in Equation 22: . The apparent power is simple calculated multiplying Equation 25: and Equation 22: . The DSP then performs the integration of the computed powers into energies. These integrators are implemented as up/down counters and they can rollover. 20-bit output buses of the counters are assigned as most significant part of energy data records. It is a responsibility of an application to read the counters at least every second not to miss any rollover. IIRMS = Vdt)t(vT T RMS == ∫ Vdt)t(vT T 2 ω⋅=′∫ VI V IS =ω⋅⋅ Idt)t(iT T RMS =′′= ∫

9 STPM01 calibration

calibration to be performed in only one point shortening the production time of the meter. range of ±12.5 % in 256 steps, and digital filter, to remove any signal DC component. values of measured voltage and current. through serial port interface, SPI, and communication channel. permanently through SPI communication channel. Table 18. Working point settings Table 19. Device constants

As shown in Table 18, only analog parameter are object of calibration because introduce a certain error. Voltage ADC amplification Av is constant, while Ai is chosen according to used sensors. The calibration algorithm will firstly calculate the voltage divider ratio and, as final result, the correction parameters, called Kv and Ki, which applied to STPM01 voltage and current measures compensate small tolerances of analog components that affect energy calculation. Since Kv and Ki calibration parameters are the decimal representation of the corresponding configuration bytes CHV and CHP or CHS (respectively voltage channel, primary current channel and secondary current channel calibration bytes), at the end of calibration CHV and CHP or CHS (according to the current channel under calibration, primary or secondary respectively) bits' values are obtained. In the following procedure CHV, CHP and CHS will be indicated as Cv and Ci. Through hardwired formulas Kv and Ki tune measured values varying from 0,75 to 1 in 256 steps, according to the value of Cv and Ci (from 0 to 255). To obtain the greatest correction dynamic initially calibrators are set in the middle of the range, thus obtaining a calibration range of 12.5 % per voltage or current channel: Calibrator’s value Kv = Ki = 0.875 Ci = Cv = 128 In this way it is possible to tune Kv and Ki having a precise measured: for example Cv = 0 generates a correction factor of -12.5 % (Kv = 0.75) and Cv = 255 determines a correction factor of +12.5 % (Kv = 1), and so on. According to what pointed out above, the following formulas, which relate Kv, i and Cv, i are obtained: Cv,i = 1024 * Kv,i - 768. The calibration procedure will output Cv and Ci values that will allow the above power sensitivity of the meter. This sensitivity is used to calculate target frequency at LED pin for nominal voltage and current values: X F = f * 64; with: f = PM * In * Vn / 3600000; From values above and for both chosen amplification factor AI=32 and initial calibration data, the following target values can be calculated: Target RMS reading for given In: XI = In * KS * AI * Ki * GINT * GDF * GDIF * BI / (VBG * 1000) = 1573 Target RMS reading for given Vn: XV = f * BV * BI * DUD / (fM * XI) = 852 The output of the voltage divider is then:

VDIV = (XV * VBG)/ (2 * GDIF * AV * Kv * GDF * GINT * BV)= 145,6 mV Choosing R2 = 500 Ω (connected between VI and VSS), the R1 resistor (connected between VLINE and VIP) value is obtained: R1 = R2 * (Vn - VDIV) / VDIV = 789,3 Ω Indicating with IA and VA the real readings on the STPM01 RMS registers of voltage and current, and with XI and XV ideal values of RMS current and voltage readings already calculated, the final values for calibrators can be calculated as: XV = (Kv * VA) / 0.875 XI = (Ki * IA) / 0.875 If the computed final calibration data would fall out of calibration data range, the energy meter should be recognized as bad or the given presumptions and calculations above should be checked. Otherwise, if the final data of calibrators would be written into energy meter, the RMS readings should be very close to target values I and V and the frequency of LED output should be very close to target value f.

1. Maximize the signal to noise ratio in the voltage channel,
2. Choose the current to voltage conversion ratio Ks and the voltage divider ratio in a way
3. Choose Ks to take advantage of the whole current dynamic range according to desired

maximum current and resolution. should be as close as possible to those shown in Table 20.

• P = 64000 imp/KWh
• INOM = 5 A
• IMAX = 60 A. Typical values for the current sensors sensitivity, also used in the reference schematic below, are shown in Table 21. Note: If the device is used in configuration PST = 7 (primary channel with CT, secondary channel with Shunt), the shunt Ks must always be equal to one fourth of the current transformer Ks. Additional considerations on the application design, suggestions for noise and crosstalk reduction can be found in the AN2317.

Table 20. Resistor divider ratio Table 21. Current channel typical components

Figure 29. STPM01 reference schematic with one current transformer and one shunt

Figure 30. STPM01 with 3X charge pump DC-DC converter

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Dim. mm. inch. A 1.2 0.047 b 0.19 0.30 0.007 0.012 c0 . 0 9 0.20 0.004 0.007 9 e 0.65 B SC 0.0256 B SC K0 ° 8°0 ° 8° TSSOP20 mechanical data c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 0087225C

Dim. mm. inch. A 330 12. 992 C 12. 8 13.2 0.504 0.51 9 D 20.2 0.7 95 N6 0 2 . 362 T 22.4 0. 882 Ao 6. 8 7 0.26 8 0.276 Bo 6. 9 7.1 0.272 0.2 80 Ko 1.7 1. 9 0.067 0.075 Po 3.9 4.1 0.15 3 0.161 P 11. 9 12.1 0.46 8 0.476 Tape & reel TSSOP20 mechanical data

Table 22. Document revision history 28-Sep-2004 1 Preliminary data. 22-Dec-2005 2 Document updated. 24-Oct-2006 3 The chapter 9 updated. 06-Feb-2006 4 Modified Figure 11. 12-Jan-2009 5 Modified address 11 Table 16 on page 34. 03-Apr-2009 6 Modified Figure 20 on page 27. 09-Jun-2011 8 Modified: Table 7 on page 11.