STPIC44L02

STPIC44L02 STMICROELECTRONICS | Alldatasheet

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Technical content

■ 4-CHANNEL SERIAL-IN PARALLEL-IN LOW SIDE PRE-FET DRIVER ■ DEVICES ARE CASCADABLE ■ INTERNAL 55V INDUCTIVE LOAD CLAMP AND VGS PROTECTION CLAMP FOR EXTERNAL POWER FETS ■ INDEPENDENT SHORTED-LOAD AND SHORT-TO-BATTERY FAULT DETECTION ON ALL GATE TERMINALS ■ INDEPENDENT OFF-STATE OPEN-LOAD FAULT SENSE ■ OVER-BATTERY-VOLTAGE LOCKOUT PROTECTION AND FAULT REPORTING ■ UNDER-BATTERY VOLTAGE LOCKOUT PROTECTION ■ ASYNCRONOUS OPEN-GATE FAULT FLAG ■ DEVICE OUTPUT CAN BE WIRED OR WITH MULTIPLE DEVICES ■ FAULT STATUS RETURNED THROUGH SERIAL OUTPUT TERMINAL ■ INTERNAL GLOBAL POWER-ON RESET OF DEVICE AND EXTERNAL RESET TERMINAL ■ HIGH IMPEDANCE CMOS COMPATIBLE INPUTS WITH HYSTERESIS ■ TRANSITION FROM THE GATE OUTPUT TO A LOW DUTY CYCLE PWM MODE WHEN A S H O R T E DL O A DF A U L TO C C U R S

DESCRIPTION

The STPIC44L02 is a low-side predriver that provides serial and parallel input interfaces to control four external FET power switches. It is mainly designed to provide low-frequency switching, inductive load applications such as solenoids and relays. Fault status is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted load short to battery detection. The STPIC44L02 offers a battery over voltage and undervoltage detection and shutdown. If a fault occurs while using the STPIC44L02, the channel transitates into a low duty cycle, pulse width modulated (PWM) signal as long as the fault is present. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver are minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transitate CS from high to low to activate the serial input interface. When this occurs, SDO, is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Data is clocked into the serial registers on low to high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted load and open load flags (bits 0-3) for each of the four output channels. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS is transitated from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. CSmust be transitated high after all of the serial data has been clocked into the device. A low to high transition of CS transfers the last four bits of serial data to the STPIC44L02

4 CHANNEL SERIAL AND PARALLEL

output buffer that puts SDO in a high impedance state and clears and reenables the fault register. The STPIC44L02 was designed to allow the serial input interfaces of multiple devices to be cascated together to simplify the serial interface of the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0-3) output asynchronously. SCLK or CS is not required for parallel control. A 1 on the parallel input turns the respective channel on, where as a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predriver monitors the drain voltage for each channel to detect shorted load or open load fault conditions, in the on and off state respectively. These devices offer the option of using an internally generated fault reference voltage or an externally supplied fault reference voltage through V COMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting V COMPEN to VCC . The drain voltage is compared to the fault reference when the channel is turned on to detect shorted load conditions and when the channel is off to detect open load conditions. If a fault occurs, the channel transitates into a low duty cycle, pulse width modulated (PWM) signal as long as the fault is present. Shorted load fault conditions must be present for at least the shorted load deglicth time, t (STBDG) , to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this datasheet. The device provides protection from over battery voltage and under battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervotlage threshold, all channels are disabled and a fault flag is generated. Battery voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery voltage fault has been corrected. When an over battery/under battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted load conditions. Fault reporting for open and shorted load conditions are reenabled after the battery fault condition has been corrected. This device provides inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of V CC and turn on voltage of the external FET. The predriver also provides a gate to source voltage (V GS ) clamp to protect the gate source terminals of the power FET from exceeding their rated voltages. An external active low RESET is provided to clear all register and flags in the device. GATE(0-3) outputs are disabled after RESET has been pulled low. The device provide pull-down resistors on all inputs except CS and RESET . A pull-up resistor is used on CSand RESET . ORDERING CODES Type Package Comments STPIC44L02PTR SSOP24 (Tape & Reel) 1350 parts per reel

Figure 1 :Schematic Diagram

PIN No SYMBOL I/O NAME AND FUNCTION 1F L T I Fault Flag. FLT is a logic level open-drain output that provides a real time fault flag for shorted-load, open-load, over-battery voltage, under-battery voltage faults. The device can be ORed with FLT terminals on other devices for interrupt handling. FLT requires an external pull-up resistor. 2 VCOMPEN I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an external fault reference (1) to be used in the shorted and open load fault detection circuitry. 3 VCOMP I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and open load fault detection circuitry. IN0 IN1 IN2 IN3 I Parallel gate driver. IN0 trough In3 are real-time controls for the gate pre drive circuitry. They are CMOS compatible with hysteresis. 8C S I Chip select. A high to low transition on CSenables SDO, latches fault data into the serial interface, and refreshes FLT. When CS is high, the fault register can change fault status. On the falling edge of CS, fault data is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of CS, serial data is latched in to the output control register. 9 SDO O Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high state. 10 SDI I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a particular gate output on and a 0 turns it off. 11 SCLK I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of SDO on the falling edge of the serial clock.

12 V CC I Logic Supply Voltage

13 GND I Ground

I FET drain inputs. DRAIN0 through DRAIN3 are used for both open load and short circuit fault detection at the drain of the external FETs. They are also used for inductive transient protection. GATE0 GATE1 GATE2 GATE3 O Gate drive output. GATE0 through GATE3 outputs are derived from the VBAT supply voltage. Internal clamps prevent voltages on these nodes from exceeding the VGS rating of most FETs. 22 RESET I Reset. A high-to low transition of RESETclears all registers and flags. Gate outputs turn off and the FLTflag is cleared.

23 NC Not Connected

BAT I Battery Supply Voltage

Figure 2 :Pin Configuration ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltage value are with respect to GND RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Logic Supply Voltage (See Note 1) -0.3 to 7 V VBAT Battery Supply Voltage -0.3 to 60 V VI Logic Input Voltage Range -0.3 to 7 V VO Output Voltage (SDO and FLT) -0.3 to 7 V V O Output Voltage -0.3 to 15 V VI Logic Input Voltage Range -0.3 to 7 V VDS Drain to Source Voltage -0.3 to 60 V TC Operating Case Temperature Range -40 to +125 °C TJ Maximum Junction Temperature 150 °C Tstg Storage Temperature Range -40 to +150 °C Symbol Parameter Min. Min. Max. Unit VCC Logic Supply Voltage 4.5 5 5.5 V VBAT Battery Supply Voltage 8 24 V VIH High Level Input Voltage 0.85V CC VCC V VIL Low Level Input Voltage 0 0.15V CC V ts Set-up Time, SDI High Before SCLK↑ 10 ns th Hold Time, SDI High After SCLK↑ 10 ns TC Operating Case Temperature -40 125 °C

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise specified.) Symbol Parameter Test Conditions Min. Typ. Max. Unit IBAT Supply Current All Outputs OFF, V BAT = 12V 50 150 250 µA ICC Supply Current All Outputs OFF, V BAT = 5.5V 0.5 1.5 3 mA V(ovsd) Over Battery Voltage Shutdown Gate Disabled (see figure 21) 32 34 36 V Vhys(ov) Over Battery Voltage Reset Hysteresys 0.1 0.3 0.5 V V(uvsd) Under Battery Voltage Shutdown Gate Disabled (see figure 20) 4.1 4.8 5.4 V Vhys(uv) Under Battery Voltage Reset Hysteresys 50 150 300 mV VG Gate Drive Voltage V BAT =8t o2 4 V I O =1 0 0µA 7 13.5 V VBAT = 5.5 to 8V IO =1 0 0µA5 8 V IO(H) Maximum Current Output For Drive Terminal Pull-Up VO = GND 0.5 1.8 2.5 mA IO(L) Maximum Current Output For Drive Terminal Pull-Down V O = 7V 0.5 1.2 2.5 mA V (stb) Short to Battery, Shorted Load, Open Load Detection Voltage VCOMPEN = L 1.1 1.25 1.4 V Vhys(stb) Short to Battery Hysteresys 30 mV VD(open) Open Load OFF State Detection Voltage Threshold VCOMPEN = L 1.1 1.25 1.4 V Vhys(open) Open Load Hysteresys 60 mV II(open) Open Load Off State Detection Current VDRAIN =V REF = 1.25V 30 60 80 µA VDRAIN = 24V (see figure 24) 250 µA II(PU) Input Pull-up Current V CC =5 V V I=0 1 0 µA II(PD) Input Pull-down Current VCC =5 V V I=5 V 1 0 µA Vhys Input Voltage Hysteresys VCC = 5V 0.6 0.85 1.1 V VO(SH) High Level Serial Output Voltage IO = 1mA 0.8V CC V VO(SL) Low Level Serial Output Voltage IO = 1mA 0.1 0.4 V IOZ(SD) 3-State Current Serial Data Output VCC = 0 to 5.5V -10 1 10 µA VO(CFLT) Fault Interrupt Output Voltage IO = 1mA 0.1 0.5 V VI(COMP) Fault External Reference Voltage VCOMPEN =H 1 3 V VC Output Clamp Voltage dc < 1% t W =1 0 0µs 4 75 56 3V

SWITCHING CHARACTERISTICS (VCC =5V, VBAT =5V, TC = 25°C, unless otherwise specified.) Note 1: The td1 is referred to the falling edge of the first clock after the CSfalls down Symbol Parameter Test Conditions Min. Typ. Max. Unit t(STBFM) Short to Battery, Shorted Load, Open Load Fault Mask Time (see figures 16, 17) 60 µs t(STBDG) Short to Battery, Shorted Load, Deglitch Time (see figures 16, 17) 12 µs tPLH Propagation Turn-On Delay Time, CSor IN0-IN3 to Gate0-Gate3 C (gate)= 400pF 3.5 µs tPHL Propagation Turn-Off Delay Time, CSor IN0-IN3 to Gate0-Gate3 C (gate)= 400pF 4 µs tr1 Rise Time, Gate0-Gate3 C (gate)= 400pF 1.5 µs tf1 Fall Time, Gate0-Gate3 C (gate)= 400pF 2 µs f(SCLK) Serial Clock Frequency 10 MHz trf(SB) Refresh Time Short to Battery (see figure 16) 10 ms tW) Refresh pulse width Short to Battery (see figure 16) 68 µs tsu1 Setup Time CS↓ to SCLK↓ (see note 1) (see figure 4) 10 ns tpd1 Propagation Delay Time CS to SDO Valid R L =1 0 KΩ C L = 200pF (see figure 6) 40 ns tpd2 Propagation Delay Time SCLK to SDO Valid 20 ns tpd3 Propagation Delay Time CS to SDO 3-State R L =1 0 KΩ C L = 50pF (see figure 6) 2 µs tr2 Rise Time, SDO 3-State to SDO Valid R L =1 0 KΩ to GND CL = 200pF Over Battery Fault (see figure 7) 30 ns tf2 Fall Time, SDO 3-State to SDO Valid R L =1 0 KΩ to GND CL = 200pF No Fault (see figure 8) 20 ns tr3 Rise Time, FLT R L =1 0 KΩ C L = 50pF (see figure 9) 1.2 µs tf3 Rise Time, FLT R L =1 0 KΩ C L = 50pF (see figure 9) 15 ns

The STPIC44L02 monitors the drain voltage of each channel to detect shorted load conditions. The onboard deglitch timer starts running when the gate output to the power FET transitates from the off state to the on state. The timer provides a 60µs deglitch time, t (STBFM) ,t oa l l o wt h ed r a i n voltage to stabilize after the power FET has been turned on (see figure 16 and 17). The deglitch delay time is only enabled for the first 60µs after the FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference voltage. When it is greater than the reference voltage for at least the short to battery deglitch time, t (STBDG) FLT flags the microcontroller that a fault condition exists and gate output is automatically shut off until the error condition has been corrected. An overheating condition on the FET occurs when the controller continually tries to reenable the output under shorted load fault conditions. When a shorted load fault is detected, the gate output is transitated into a low duty cycle PWM signal to protect the FET from overheating. The PWM rate is defined as t (SB) and the pulse width is defined as tW . The gate output remains in this state until the fault has been corrected or until the controller disables the gate output. The microcontroller can read the serial port on the predriver to isolate the channel that reported the fault condition. Fault bits 0-3 distinguish faults for each of the output channels. When a shorted load occurs, the STPIC44L02 automatically retries the output and the fault clears after the fault condition has been corrected. Figure 16 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on and the deglitch timer starts running. Under normal operation, T1 turns on and the drain operates below the reference point set at U1. The output of U1 is low and a fault condition is not flagged. Figure 14 :Open Load Test Circuit

DIM. mm. inch A 2 0.079 A1 0.05 0.002 b 0.22 0.38 0.009 0.015 c 0.09 0.25 0.004 0.010 e 0.65 BSC 0.0256 BSC K0 ˚ 8 ˚ 0 ˚ 8 ˚ SSOP24 MECHANICAL DATA c Eb A2A D PIN 1 IDENTIFICATION LK e 0053237/C

DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Ao 8.4 8.6 0.331 0.339 Bo 8.7 8.9 0.343 0.351 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel SSOP24 MECHANICAL DATA

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