Datasheet - STPD01 - Programmable buck converter for USB power delivery
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 43
Technical content
Datasheet sections
- 1 Application schematic
- 2 Pin configuration (top through view)
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Block diagram
- 6 Typical performance characteristics
- 7 Operation description
- 7.1 Enable
- 7.1.1 Digital enable
- 7.2 Cable drop compensation
- 7.2.1 Output current monitor
- 7.3 Auto discharge
- 7.4 Power-on
- 7.5 Vout transition
- 7.6 Clock dithering
- 7.7 Programmable watchdog
- 7.8 Protections
- 7.8.1 Overvoltage protection
- 7.9 Interrupt functionality
- 7.10 Switching frequency
- 7.11 Pulse skip
- 7.12 Bus timing
- 7.12.1 Read and write commands
- 7.12.2 I2C address selection
- 8 Control register description
- 8.1 Register map
- 8.2 Register description
- 8.2.1 Register 0x00
- 8.2.2 Register 0x01
- 8.2.3 Interrupt registers: 0x02, 0x03, 0x04
- 8.2.4 Register 0x05
- 8.2.5 Register 0x06
- 9 Application notes
- 9.1 Board layout guidelines
Features
- Input voltage range 6.0 V to 26.4 V
- Internal power MOS synch rectification
- Internal compensation
- I2C bus controlled
- Vout settings: 3 V to 20 V with 20 mV (min.) steps
- Slew rate control (max. 30 mV/us)
- Cable drop compensation
- Iout settings: 0.1 A to 3 A with 50 mA steps
- Embedded discharge function
- Two programmable switching frequencies with optional clock dithering
- Watchdog timer set by I2C
- Configurable interrupt pin
- Soft-start
- Power-on pin
- Programmable constant current limit
- OVP, IPEAK and overtemperature protections
- Short-circuit protection
- Undervoltage lockout
- Available in QFN24L 3 x 4 package
Applications
- AC adapters
- USB hubs
- PC monitors
- Smart TV
- USB-PD power distribution
Description
The STPD01 is a programmable synchronous buck converter suitable to provide power supply in applications following USB power delivery specifications. The device provides those voltages required by USB power delivery systems as stated in USB PD 3.0 spec up to 60 W output power (20 V, 3 A). The different levels of output voltage and current limitation can be set dynamically through I2C interface. Overvoltage, overcurrent and overtemperature protections are included in the device. A programmable watchdog improves the robustness and the safety of the complete system. Finally, the device is available in QFN24L 3 x 4 mm2. Product status link STPD01 Product summary Order code STPD01PUR Programmable buck converter for USB power delivery STPD01 Datasheet DS13473 - Rev 5 - June 2025 For further information, contact your local STMicroelectronics sales office.
1 Application schematic
Figure 1. STPD01 typical application schematic Table 1. Bill of material
2 Pin configuration (top through view)
Figure 2. Pin configuration (top through view) Table 2. Pin description
1 SDA I2C data
2 SCL I2C clock
3 ADD I2C address selection (cannot be left floating)
4 INT Interrupt pin (open drain output)
7 VCC Analog supply input
8 PVIN Power supply input
9 PVIN Power supply input
10 PGND Power ground
11 PGND Power ground
12 PGND Power ground
13 LX Switching node
14 LX Switching node
15 LX Switching node
18 VREG Internal LDO regulator voltage pin (connect 1 μF capacitor between this pin and GND)
22 CDC Cable drop compensation programming pin
24 SGND Signal ground
EP Exposed pad for heat dissipation, to be electrically connected to Power ground STPD01 Pin configuration (top through view) DS13473 - Rev 5 page 4/43
3 Maximum ratings
Table 3. Absolute maximum ratings Table 4. Thermal data
- Standard FR4 4 layer PCB board.
4 Electrical characteristics
Table 5. Recommended operating conditions Table 6. Electrical characteristics
Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit Ivalley Inductor current limit thresholds ANegative 3.5 OVP Overvoltage protection threshold (VSNS/Vnom) VSNS sensed voltage vs. nominal vout set in the reg 0x00 1.1 1.15 V/V OVP deglitch 5 ms OVP masking time during Vout transition or fault Start-to-end transition 275 300 ms CCth Constant current threshold (Iout/Ilim) Rsense = 25 mΩ, 1% precision, 0.5<Iout<3 A 1.00 A/A SCP Short-circuit protection Percentage of VSNS 20 % Short-circuit timer 300 ms OTP Overtemperature protection threshold(2) 165 °C OTP hysteresys 30 °C TW Thermal warning Reg 0x02 150 °C TW hysteresys 10 °C η Efficiency(2) Vout = 5 V, Iout = 1.5 A, Fsw=500 kHz 89 Vout = 9 V, Iout = 1.5 A, Fsw=500 kHz 93 Vout = 15 V, Iout = 1.5 A, Fsw=500 kHz 95 Vout = 20 V, Iout = 1.5 A, Fsw=500 kHz 96 SCLf SCL clock frequency 400 kHz Cable drop compensation RCDC1 = 10 kΩ, RCDC2 = 24 kΩ, RSENSE = 25 mΩ, ILOAD = 1 A 450 mV Cable drop tolerance -30 +30 % Cable drop saturation 1 V ISNS+, ISNS- Bias current VISNS+ = VISNS- = 20 V 100 µA EN ON threshold 1.2 V OFF threshold 0.35 IEN Enable current EN = GND 3 5 µA Logic section (SCL, SDA pins) VOL Low level output voltage ISINK = 2 mA 0.2 V VIH High level threshold voltage 1.2 V VIL Low level threshold voltage 0.35 V Ilk Leakage current Vpullup = 3.3 V 1 uA INT, PON pins Vod Output voltage ISINK = 2 mA 0.1 V Iod Leakage current Vpullup = 5 V 1 uA 1. Cumulative current from PVIN and VCC. 2. Not tested in production. STPD01
5 Block diagram
Figure 3. STPD01 block diagram
6 Typical performance characteristics
Figure 4. Efficiency (Vin = Vcc = 24 V, CC = 0x1F, Fsw = 500kHz) Figure 5. System PLOSS (Vin = Vcc = 24 V, CC = 0x1F, Fsw = 500 kHz) Figure 6. Efficiency (Vin = Vcc = 24 V, CC = 0x1F, Fsw = 750 kHz)
7 Operation description
7.1 Enable
7.1.1 Digital enable
the digital core completely. core is kept partially ON to allow the I2C to wake up the device. Table 7. Functional modes
7.2 Cable drop compensation
where the parameter k is 18 and RCDC2 depends on the cable resistance, with RCDC1 being typically 10 kOhm. can be achieved by a proper choice of RCDC1 and CCDC.
Figure 32. Cable drop configuration
7.2.1 Output current monitor
This formula is valid for ILOAD of more than about 300 mA. since the policy manager can read the current provided to the load regardless of I2C access.
7.3 Auto discharge
on a 60 mA current sink which discharges the LX node. digital En bit is set, but it is always active when EN pin is pulled low.
7.4 Power-on
The pin can be left floating if not used.
Figure 33. Deglitch time
7.5 Vout transition
reported in the EC table (see Table 6. Electrical characteristics). margin of 500 mV (max.) is allowed for about 300 ms and OVP is masked in order to avoid false alarms. Figure 34. Transition envelope for positive voltage Figure 35. Transition envelope for negative voltage Figure 36. Placement of source bulk capacitance
minimum value (total) of 10 uF.
7.6 Clock dithering
7.7 Programmable watchdog
STPD01 address, otherwise the registers 0x00, 0x01 and 0x05 are reset at their default values. The interrupt is reset after the first I2C access. This watchdog function can be disabled setting the bit 1 in register 0x06.
7.8 Protections
Table 8. Protections threshold. See Section 7.8.1: Overvoltage protection for more details. limit the output current. The VOUT drops below the programmed level. activated if enabled by the dedicated bit. 135 °C with default output voltage value. Active as soon as the device is in regulation (at the ends of the soft-start). switching off both HS and LS MOSFET. voltage value. The VOUT bits (reg 0x00) and Ilim bits (reg 0x01) are reset.
Protection Function INT pin STATUS Pon pin STATUS IPK (inductor peak current) Active as soon as the device is enabled and PVIN/VCC voltage valid is present (above the UVLO level), even during the soft-start. The condition is checked cycle-bye-ycle on the high-side and triggered once the current cross the IPK threshold. The device reacts switching asynchronously (independent from oscillator frequency) between Ipk and Ivalley with a given slope, dependent on L and Cout. LOW HIGH
7.8.1 Overvoltage protection
Overvoltage protection behaves in different ways depending on the state of the device. Case A) OV during Vout transition
- In case an OV occurs during a Vout transition, the output voltage must be reset to 5 V (Vsafe). Therefore, the following process applies: OV event longer than deglitch time => REG 0x00 = 0x64 => after blanking time, the half-bridge is put in high impedance if the OV condition is still present. In case OV lasts less than deglitch time, the event is filtered. Case B) OV during steady-state
- Case B1) Vout=5 V If OV event is detected, the half-bridge is just put in high impedance until the condition disappears.
- Case B2) Vout different than 5 V The following process applies: OV event longer than deglitch time => REG 0x00 = 0x64 => after blanking time, the half-bridge is put in high impedance if the OV condition is still present. In case OV lasts less than deglitch time, the event is filtered.
7.9 Interrupt functionality
The interrupt output is activated on the edge of the fault and is reset once the fault disappears. To keep track of the fault, the corresponding bit in the INT_LTCH register is set. Such interrupt management process allows multiple interrupt tracking. The I2C master reads the INT_LTCH register and optionally can read the INT_STAT to check if some fault is still active.
7.10 Switching frequency
The STPD01 allows two possible programmable switching frequencies (by I2C): 500 kHz (default) and 750 kHz (reg 0x05 bit 2). STPD01 Operation description DS13473 - Rev 5 page 21/43
7.11 Pulse skip
sleep period is a function of the load. the proper regulation to light load (or no load conditions). selected to optimize the efficiency at light loads.
7.12 Bus timing
As shown in the figure below, the data on the SDA line must be stable during the high semi-period of the clock. The high and low-state of the data line can only change when the clock signal on the SCL line is low. Figure 37. Data transfer validity shown in Figure 38. START and STOP commands. Figure 38. START and STOP commands SCL clock. The acknowledge bit is used to indicate a successful byte transfer.
The master then generates further SCL cycles to either transmit data to the slave or receive data from the slave. wait for a new start command.
7.12.1 Read and write commands
consists of eight bits with most significant bit first and least significant bit last. consecutive registers during one write command. Figure 39. Write command Figure 40. Read command The master sends a “Repeated Start” after sending the register address and before resending the slave address. The “Repeated Start” is defined as SDA transition from 1 to 0 with SCL high.
7.12.2 I2C address selection
The I2C address can be selected using the ADD pin to allow multiple devices to be connected on the same bus.
Table 9. I2C address configuration
8 Control register description
8.1 Register map
Table 10. Configuration bits Table 11. Register map summary R: read; R/W: read and write; R/C: cleared when read.
8.2 Register description
8.2.1 Register 0x00
The register 0x00 is used to set the output voltage configuration. Its default value (reset) is 0x64. Table 12. 0x00 register description
value (V) Hex value Voltage value (V) Hex value Voltage value (V) Hex value Voltage value (V) Hex value Voltage value (V) 0x23 3.7 0x53 4.66 0x89 5.74 0xBF 10.5 0x24 3.72 0x54 4.68 0x8A 5.76 0xC0 10.6 0x25 3.74 0x55 4.7 0x8B 5.78 0xC1 10.7 0x26 3.76 0x56 4.72 0x8C 5.8 0xC2 10.8 0x27 3.78 0x57 4.74 0x8D 5.82 0xC3 10.9 0x28 3.8 0x58 4.76 0x8E 5.84 0xC4 11 0x29 3.82 0x59 4.78 0x8F 5.86 0xC5 11.2 0x2A 3.84 0x5A 4.8 0x90 5.88 0xC6 11.4 0x2B 3.86 0x5B 4.82 0x91 5.9 0xC7 11.6 0x2C 3.88 0x5C 4.84 0x92 6 0xC8 11.8 0x2D 3.9 0x5D 4.86 0x93 6.1 0xC9 12 0x2E 3.92 0x5E 4.88 0x94 6.2 0xCA 12.2 0x2F 3.94 0x5F 4.9 0x95 6.3 0xCB 12.4 0x30 3.96 0x60 4.92 0x96 6.4 0xCC 12.6 0x31 3.98 0x61 4.94 0x97 6.5 0xCD 12.8 0x32 4 0x62 4.96 0x98 6.6 0xCE 13 0x33 4.02 0x63 4.98 0x99 6.7 0xCF 13.2 0x34 4.04 0x64 5 0x9A 6.8 0xD0 13.4 0x35 4.06 0x65 5.02 0x9B 6.9 0xD1 13.6 STPD01 Control register description DS13473 - Rev 5 page 27/43
8.2.2 Register 0x01
Table 13. 0x01 register description 0x1E or 0x1F disables the constant current function.
8.2.3 Interrupt registers: 0x02, 0x03, 0x04
Table 14. Interrupt register description
0 Overvoltage protection
1 Constant current function
2 Short-circuit protection
3 Power-on
4 Watchdog
5 Overtemperature protection Junction temperature 165 °C
6 Overtemperature warning Junction temperature 145 °C
7 Inductor peak current protection
8.2.4 Register 0x05
The register 0x05 is used for services and in particular: Bit Function Notes
0 Discharge
0: OFF 1: ON (default)
1 Dithering
0: OFF (default) 1: ON
2 Switching frequency
0: 500 kHz (default) 1: 750 kHz 4:3 Cable drop compensation 00: OFF (default) 10: Full 01: N/A 11: N/A
5 Not used -
7:6 Watchdog timer 00: 100 ms (default) 01: 500 ms 10: 1 s 11: 5 s Default value (reset) is 0x01.
8.2.5 Register 0x06
The register 0x06 is only used for digital enable. Bit Function Notes
0 Digital enable
0: OFF 1: ON (default)
1 Watchdog enable
0: OFF (default) 1: ON 7:2 To be defined To be defined Default value (reset) is 0x01. STPD01 Control register description DS13473 - Rev 5 page 29/43
9 Application notes
9.1 Board layout guidelines
The DC-DC converter area is very sensitive, and it is necessary to pay attention to the layout of this part. The DC- DC converter generates GND noise that can get coupled on surrounding ground reducing the sensitivity, and high-frequency components can be coupled onto RF part. So, to ensure a correct layout it is necessary to:
- Provide efficient filtering by placing capacitors as close as possible
- Reduce parasitic ensuring wide and short connections. Four-layer boards A four-layer board is strongly recommended. Put the ground layer very close to the top layer to obtain a good ground plane reference. A thickness between the top layer and ground layer of 0.2 mm or 0.3 mm is suggested. Put a ground plane internally to reduce the coupling between the traces If it is not possible to use a four-layer board, it is necessary to fill the area under the phase node of the board with ground metal to reduce or eliminate radiation emissions. Board routing and wiring should not be placed in this region to prevent coupling effects and to ensure a good ground reference plane to the RF parts. Ground plane Any switch mode power supply requires a good PCB layout in order to achieve the maximum performance. Component placement, and GND trace routing and width are the major issues. Basic rules commonly used for DC-DC converters for good PCB layout should be followed. All traces carrying current should be drawn on the PCB as short and as thick as possible. This should be done to minimize resistive and inductive parasitic effects, and increase system efficiency. Suggested PCB (ring) ground plane to avoid spikes on the output voltage. Good soldering of the exposed pad helps on this issue. Connect all the ground metallization and/or layers with as many vias as possible. Ground vias between layers should be added liberally throughout the RF portion of the PCB. This helps prevent accrual of parasitic ground inductance due to ground-current return paths. The vias also help to prevent cross-coupling from RF and other signal lines across the PCB. The layers assigned to system bias (DC supply) and ground must be considered in terms of the return current for the components. The general guidance is not to have signals routed on layers between the bias layer and the ground layer. Capacitors placing Particular care has to be taken in the placement of the supply voltage filtering capacitors. It is, in fact, important to ensure efficient filtering placing these capacitors as close as possible from their dedicated pins on the VIN (C6), VCC (C5), VREG (C1), VHDRIVE (C3), VBOOT (C14) and VSNS (C16). STPD01 Application notes DS13473 - Rev 5 page 30/43
techniques. Do not route the Vref trace near noisy traces or planes. techniques. Do not route the Vref trace near noisy traces or planes. sense lines pass through noisy areas, such as switch nodes. Figure 43. RSNS Kelvin connection (sx sense in the same layer, at dx with vias top to bottom) forecasted to go below the DC value for short AC pulses, the source current must be limited to a max. of 10 mA. area having a shape as square as possible and not interrupted by other copper traces.
Figure 44. Thermal aspects
9.2 Selecting components for the application
voltage ripple a low ESR capacitor is required. where ΔI is the ripple current and FSW is the switching frequency. where TON is the ON time of the internal switch, given by D · T. value for the output current.
- Switching losses due to the RDS(on). These are equal to: P HS = R DS on I OU T
2 D (6)
P LS = R D S o n I O U T 2 1 − D (7) where D is the duty cycle of the application. Note: The duty cycle is theoretically given by the ratio between VOUT and VIN, but in practice it is significantly higher than this value to compensate for the losses of the whole application. For this reason, the switching losses related to the RDS(on) increase compared to an ideal case.
- On and OFF switching losses. These are given by the following relation: P SW = V I N I OU T T ri s e + T f al l
2 F SW (8)
where Trise and Tfall are the overlap times of the voltage across the power switch and the current flowing into it during the turn-on and turn-off phases.
- Quiescent current losses: P Q = V I N × I I N (9) where IN is the supply current. P TOT = P Q + P SW + P HS + P L S (10) The junction temperature of the device is: T J = T A + R t ℎ J − A ⋅ P TOT (11) where TA is the ambient temperature and RthJ-A is the junction to ambient thermal resistance. Considering that the device, mounted on the board with a good ground plane, has a thermal resistance junction to ambient (RthJ-A) of about 31 °C/W. It is also possible to estimate the junction temperature directly from the efficiency measures acquired on a stationary application condition. Considering that the power losses are given by: PL OSS = PI N − PO U T (12) Neglecting the AC losses of the selected inductor, the power losses are given by: PL OSS = V I N ⋅ I I N − VOU T ⋅ I OU T − DC R 1 ⋅ I OU T (13) Therefore, the junction temperature TJ can be calculated as: T J = T A + R t ℎ J A ⋅ PL OSS (14) STPD01 Application notes DS13473 - Rev 5 page 34/43
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 QFN24L (3 x 4 x 1.0 mm) package information Figure 45. QFN24L (3 x 4 x 1.0 mm) package outline Table 15. QFN24L (3 x 4 x 1.0 mm) mechanical data
Package information
DS13473 - Rev 5 page 35/43
Min. Typ. Max. A1 0.00 0.02 0.05 A3 0.20 REF. b 0.15 0.20 0.25 D 3.00 BSC E 4.00 BSC e 0.40 BSC D2 1.65 1.80 1.90 E2 2.65 2.80 2.90 K 0.15 L 0.25 0.35 0.45 N 24 Note: N is the total number of terminals. Dimension b applies to metallized terminal. If the terminal has a radius on its end dimension b should not be measured in that radius area. Figure 46. QFN24L (3 x 4 x 1.0 mm) recommended footprint DS13473 - Rev 5 page 36/43
Revision history
Table 16. Document revision history 02-Oct-2020 1 Initial release. 07-Apr-2021 2 Updated: DC and Cable drop values in Table 6, VAUX in Table 9 and Figure 45. Updated Table 6. Electrical characteristics and Figure 7. System PLOSS (Vin = Vcc = 24 V, CC = 0x1F, Fsw = 750 kHz). 16-Jun-2022 4 Updated Table 8. Protections. 09-Jun-2025 5 Updated Section 8.2.2.
Contents
DS13473 - Rev 5 page 39/43