STP9NC65 STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 650V - 0.75Ω - 8A TO-220/TO-220FP PowerMesh™II MOSFET ■ TYPICAL R DS (on) = 0.75 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ NEW HIGH VOLTAGE BENCHMARK ■ GATE CHARGE MINIMIZED

DESCRIPTION

The PowerMESH ™ II is the evolution of the first generation of MESH OVERLAY™. The layout re- finements introduced greatly improve the Ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness.

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVES ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed TYPE V DSS R DS(on) ID STP9NC65 650 V < 0.90 Ω 8 A STP9NC65FP 650 V < 0.90 Ω 8 A Symbol Parameter Value Unit STP9NC65 STP9NC65FP VDS Drain-source Voltage (VGS = 0) 650 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 650 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 8 8(*) A ID Drain Current (continuos) at TC = 100°C 5 5(*) A IDM (● ) Drain Current (pulsed) 32 32(*) A PTOT Total Dissipation at TC = 25°C 140 40 W Derating Factor 1.12 0.32 W/°C dv/dt (1) Peak Diode Recovery voltage slope 3.5 V/ns VISO Insulation Withstand Voltage (DC) - 2000 V Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤8A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. INTERNAL SCHEMATIC DIAGRAM TO-220 TO-220FP (Available Upon Request)

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 0.89 3.12 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 850 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 650 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 234V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 4.5 A 0.75 0.90 Ω ID(on) On State Drain Current V DS > ID(on) x RDS(on)max, VGS =1 0 V Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 4.5A 10 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 1400 pF C oss Output Capacitance 196 pF C rss Reverse Transfer Capacitance 31 pF

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 325 V, ID = 4.5 A R G = 4.7Ω VGS = 10 V (see test circuit, Figure 3) 28 ns tr Rise Time 15 ns Q g Total Gate Charge VDD = 520V, ID = 9 A, VGS = 10V 44 62 nC Q gs Gate-Source Charge 10.5 nC Q gd Gate-Drain Charge 19.5 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) Turn-Off Delay Time VDD = 325V, ID = 4.5 A, R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 3) 53 ns tf Fall Time 30 ns tr(Voff) Off-voltage Rise Time VDD = 520V, ID = 9 A, R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 5) 15 ns tf Fall Time 12 ns tc Cross-over Time 24 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 8 A ISDM (2) Source-drain Current (pulsed) 32 A VSD (1) Forward On Voltage ISD = 8 A, VGS = 0 1.6 V trr Reverse Recovery Time ISD = 9 A, di/dt = 100A/µs VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 610 ns Q rr Reverse Recovery Charge 5.14 µC IRRM Reverse Recovery Current 17 A Safe Operating Area for TO-220 Safe Operating Area for TO-220FP

Thermal Impedance for TO-220 Output Characteristics Transconductance Static Drain-source On Resistance Thermal Impedance for TO-220FP Transfer Characteristics

Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Capacitance Variations Source-drain Diode Forward Characteristics Gate Charge vs Gate-source Voltage

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C

DIM. mm inch A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 A B D E H G ¯ F 123F2 TO-220FP MECHANICAL DATA

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