STP8NK80Z_07 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 15
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuit
- 4 Package mechanical data
- 5 Revision history
Features
■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeatability
Description
The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Application ■ Switching applications Figure 1. Internal schematic diagram Table 1. Device summary
1 Electrical ratings
Table 2. Absolute maximum ratings
- Limited only by maximu m temperature allowed
- Pulse width limited by safe operating area
Table 3. Thermal data Table 4. Avalanche characteristics
2 Electrical characteristics
Table 5. On/off states Table 6. Dynamic
- Pulsed: pulse duration=300µs, duty cycle 1.5%
- C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
Table 7. Source drain diode
- Pulsed: pulse duration=300µs, duty cycle 1.5%
- Pulse width limited by safe operating area
Table 8. Gate-source zener diode
- The built-in back-to-back Zener diodes have specif ically been designed to enhance not only the device’s
usage of external components.
2.1 Electrical characterist ics (curves)
Figure 2. Safe operating area for TO-220 Figure 3. Thermal impedance for TO-220 Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP Figure 6. Safe operating area for TO-247 Figure 7. Thermal impedance for TO-247
3 Test circuit
Figure 19. Unclamped inductive load test Figure 20. Unclamped inductive waveform Figure 21. Switching times test circuit for Figure 22. Gate charge test circuit Figure 23. Test circuit for inductive load
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
A 4.40 4.60 0.17 3 0.181 b 0.61 0. 88 0.024 0.0 34 b1 1.14 1.70 0.044 0.066 c0 . 4 9 0.70 0.01 9 0.027 D 15.25 15.75 0.6 0.62 D1 1.27 0.050 E 10 10.40 0. 393 0.409 e 2.40 2.70 0.0 94 0.106 e1 4. 95 5.15 0.1 94 0.202 F1 . 2 3 1.32 0.04 8 0.051 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.0 94 0.107 L1 3 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L302 8.90 1.1 37 ∅P 3.75 3.85 0.147 0.151 Q2 . 6 5 2 . 95 0.104 0.116
A B D E H G F 123F2 L4L5 DIM. mm. inch A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 TO-220FP MECHANICAL DATA
DIM. mm. inch A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 0.620 e5 . 4 5 0 . 2 1 4 L 14.20 14.80 0.560 0.582 L1 3.70 4.30 0.14 0.17 L2 18.50 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S5 . 5 0 0 . 2 1 6 TO-247 MECHANICAL DATA
5 Revision history
Table 9. Revision history