STP85NF3LL STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 30V - 0.006Ω - 85A TO-220/I2PAK LOW GATE CHARGE STripFET™ POWER MOSFET ■ TYPICAL R DS (on) = 0.0075 Ω (@4.5V) ■ OPTIMAL R DS(ON) x Qg TRADE-OFF @4.5V ■ CONDUCTION LOSSES REDUCED ■ SWITCHING LOSSES REDUCED

DESCRIPTION

This application specific Power MOSFET is the third genaration of STMicroelectronics unique “ Single Feature Size” strip-based process. The re- sulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high effi- ciency are of paramount importance.

APPLICATIONS

■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS (● ) Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STP85NF3LL STB85NF3LL-1 30 V 30 V < 0.008 Ω < 0.008 Ω 85 A 85 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 30 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 30 V VGS Gate- source Voltage ± 15 V ID Drain Current (continuos) at TC = 25°C 85 A ID Drain Current (continuos) at TC = 100°C 60 A IDM (● ) Drain Current (pulsed) 340 A PTOT Total Dissipation at TC = 25°C 110 W Derating Factor 0.73 W/°C Tstg Storage Temperature –65 to 175 °C Tj Max. Operating Junction Temperature 175 °C TO-220 1 2 3 I2PAK INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 1.36 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 30 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 10 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 15V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 1V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 40 A 0.006 0.008 Ω VGS = 4.5V, ID = 40 A 0.0075 0.0095 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 40 A 30 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2210 pF C oss Output Capacitance 635 pF C rss Reverse Transfer Capacitance 138 pF

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 15V, ID = 30A R G = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) 22 ns tr Rise Time 130 ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 24V, ID = 60A, VGS = 4.5V 12.5 40 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off-Delay Time Fall Time VDD = 15V, ID = 30A, R G =4 . 7Ω, VGS = 4.5V (see test circuit, Figure 3) 36.5 36.5 ns ns td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp =24V, ID =30A R G =4 . 7Ω, VGS = 4.5V (see test circuit, Figure 5) ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 85 A ISDM (1) Source-drain Current (pulsed) 340 A VSD (2) Forward On Voltage ISD = 85A, VGS = 0 1.3 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 85A, di/dt = 100A/µs, VDD = 15V, Tj = 150°C (see test circuit, Figure 5) 105 3.4 ns nC A Thermal ImpedenceSafe Operating Area

Gate Charge vs Gate-source Voltage Capacitance Variations Static Drain-source On Resistance Transfer Characteristics

Source-drain Diode Forward Characteristics Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C

DIM. mm inch A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 E 10 10.4 0.393 0.409 L 13.1 13.6 0.515 0.531 L1 3.48 3.78 0.137 0.149 L2 1.27 1.4 0.050 0.055 L B D E A CA1 e P011P5/E TO-262 (I2PAK) MECHANICAL DATA

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