STP80N05-09 STMICROELECTRONICS | Alldatasheet

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N - CHANNEL ENHANCEMENT MODE ”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR n ULTRA HIGH DENSITY TECHNOLOGY n TYPICAL R DS(on) =7 m Ω n AVALANCHE RUGGED TECHNOLOGY n LOW GATE CHARGE n HIGH CURRENT CAPABILITY n 175 oC OPERATING TEMPERATURE

APPLICATIONS

n HIGH CURRENT, HIGH SPEED SWITCHING n DC-DC & DC-AC CONVERTER ABSOLUTE MAXIMUM RATINGS INTERNAL SCHEMATIC DIAGRAM March 1997 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDS Drain-source Voltage (VGS =0 ) 5 0 V VDGR Drain- gate Voltage (RGS =2 0k Ω )5 0 V V GS Gate-source Voltage ± 20 V ID Drain Current (continuous) at Tc =2 5 oC8 0 A ID Drain Current (continuous) at Tc =1 0 0oC6 0 A IDM (•) Drain Current (pulsed) 320 A Ptot Total Dissipation at Tc =2 5 oC 150 W Derating Factor 1 W/ oC dV/dt(1) Peak Diode Recovery voltage slope 5 V/ns Tstg Storage Temperature -65 to 175 oC Tj Max. Operating Junction Temperature 175 oC (•) Pulse width limited by safe operating area ( 1)ISD ≤ 60 A, di/dt≤ 200 A/ms, VDD ≤ V(BR)DSS,TJ ≤ TJMAX TYPE V DSS R DS(on) ID STP80N05-09 50 V < 0.009 Ω 80 A TO-220

Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 62.5 0.5 300 oC/W oC/W oC/W oC AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ <1 % ) 60 A E AS Single Pulse Avalanche Energy (starting Tj =2 5 oC, ID =I AR ,V DD =2 5V ) 600 mJ ELECTRICAL CHARACTERISTICS (Tcase =2 5oC unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID =2 5 0µ AV GS = 0 50 V IDSS Zero Gate Voltage Drain Current (VGS =0 ) VDS =M a xR a t i n g VDS = Max Rating T c =1 2 5oC µ A µ A IGSS Gate-body Leakage Current (VDS =0 ) VGS = ± 20 V ± 100 nA ON (∗) Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS =V GS ID =2 5 0µA2 3 4 V R DS(on) Static Drain-source On Resistance VGS = 10V I D =4 0A 0 . 0 0 7 0 . 0 0 9 Ω ID(on) On State Drain Current VDS >I D(on) xR DS(on)max VGS =1 0V 80 A DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (∗) Forward Transconductance VDS >I D(on) xR DS(on)max ID = 40 A 25 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS =2 5V f=1M H z V GS =0 5 9 0 0 900 230 pF pF pF STP80N05-09

ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Time Rise Time VDD =3 0V I D =4 0A R G =4 . 7 Ω V GS =1 0V (see test circuit, figure 3) 160 200 ns ns (di/dt)on Turn-on Current Slope VDD =4 8V I D =8 0A R G =50 Ω VGS =1 0V (see test circuit, figure 5)

240 A/ µs

VDD =4 0V I D =8 0A V GS = 10 V 230 280 nC nC nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time V DD =4 8V I D =4 0A R G =4 . 7 Ω V GS =1 0V (see test circuit, figure 5) 175 240 230 300 ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) 320 A A V SD (∗) Forward On Voltage I SD =8 0A V GS =0 1 . 5 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 80 A di/dt = 100 A/ µs VR =3 0V T j =1 5 0oC (see test circuit, figure 5) 125 0.6 ns µC A (∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5% (•) Pulse widthlimited by safe operating area Safe Operating Area Thermal Impedance STP80N05-09

Static Drain-source On Resistance Output Characteristics Transconductance Gate Charge vs Gate-source Voltage STP80N05-09

Normalized On Resistance vs Temperature Turn-off Drain-source Voltage Slope Normalized Gate Threshold Voltage vs Temperature Turn-on Current Slope Cross-over Time STP80N05-09

Switching Safe Operating Area Source-drain Diode Forward Characteristics Fig. 1:Unclamped Inductive Load Test Circuit Accidental Overload Area Fig. 2:Unclamped Inductive Waveform STP80N05-09

Fig. 3:Switching Times Test Circuits For Resistive Load Fig. 5:Test Circuit For Inductive Load Switching And DIode Recovery Times Fig. 4:Gate Charge test Circuit STP80N05-09

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C STP80N05-09

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