STP7NK30Z STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
N-CHANNEL 300V - 0.80Ω - 5A TO-220/TO-220FP Zener-Protected SuperMESH™Power MOSFET I TYPICAL R DS (on) = 0.80Ω I EXTREMELY HIGH dv/dt CAPABILITY I 100% AVALANCHE TESTED I GATE CHARGE MINIMIZED I VERY LOW INTRINSIC CAPACITANCES I VERY GOOD MANUFACTURING REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip- based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is tak- en to ensure a very good dv/dt capability for the most demanding applications. Such series comple- ments ST full range of high voltage MOSFETs in- cluding revolutionary MDmesh™ products.
APPLICATIONS
I HIGH CURRENT, HIGH SPEED SWITCHING I IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC I LIGHTING ORDER CODES TYPE V DSS R DS(on) ID Pw STP7NK30Z STF7NK30Z 300 V 300 V <0 . 9Ω <0 . 9Ω 50 W 20 W PART NUMBER MARKING PACKAGE PACKAGING STP7NK30Z P7NK30Z TO-220 TUBE STF7NK30Z F7NK30Z TO-220FP TUBE TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM
(/circle6 ) Pulse width limited by safe operating area (1) ISD ≤5.7A, di/dt≤200A/µs, VDD ≤ V(BR)DSS ,Tj≤ TJMAX. (*) Limited only by maximum temperature allowed THERMAL DATA AVALANCHE CHARACTERISTICS GATE-SOURCE ZENER DIODE PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. Symbol Parameter Value Unit STP7NK30Z STF7NK30Z VDS Drain-source Voltage (VGS =0 ) 300 V VDGR Drain-gate Voltage (RGS =2 0kΩ ) 300 V VGS Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC =2 5°C 55 ( * ) A ID Drain Current (continuous) at TC = 100°C 3.2 3.2 (*) A IDM (/circle6 ) Drain Current (pulsed) 20 20 (*) A PTOT Total Dissipation at TC =2 5°C 50 20 W Derating Factor 0.4 0.16 W/ °C VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 2800 V dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns VISO Insulation Withstand Voltage (DC) - 2500 V Tj Tstg Operating Junction Temperature Storage Temperature - 5 5t o1 5 0 - 5 5t o1 5 0 TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 2.50 6.25 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tjmax) EAS Single Pulse Avalanche Energy (starting Tj=2 5°C, ID =IAR ,VDD =5 0V ) 130 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 30 V
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF DYNAMIC SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. C oss eq.is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS . Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID =1 mA, VGS = 0 300 V IDSS Zero Gate Voltage Drain Current (VGS =0 ) VDS =M a xR a t i n g VDS =M a xR a t i n g ,TC = 125°C µA µA IGSS Gate-body Leakage Current (VDS =0 ) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS =V GS ,ID = 50µA 3 3.75 4.5 V R DS(on) Static Drain-source On Resistance VGS =1 0 V ,ID = 2.5 A 0.80 0.90 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs(1) Forward Transconductance V DS =15 V,ID = 2.5 A 2.5 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS =2 5 V ,f=1M H z ,VGS = 0 380 pF pF pF C oss eq.(3) Equivalent Output Capacitance VGS =0 V ,VDS = 0V to 400V 30 pF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD =2 0 0V ,ID =4 . 5A R G =4 . 7Ω VGS =1 0V (Resistive Load see, Figure 3) ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD =3 2 0 V ,ID =5A , VGS =1 0 V 4.5 7.6 17 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit t d(off) tf Turn-off Delay Time Fall Time VDD =2 0 0V ,ID =1 . 5 A R G =4 . 7Ω VGS =1 0V (Resistive Load see, Figure 3) ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time V DD =3 2 0 V ,ID =5 A , R G =4 . 7Ω, VGS = 10V (Inductive Load see, Figure 5) 8.5 8.5 ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) A A VSD (1) F o r w a r dO nV o l t a g eISD =5A ,V GS =0 1.6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5 A, di/dt = 100A/µs VDD =4 0 ,Tj= 150°C (see test circuit, Figure 5) 154 716 9.3 ns nC A
Safe Operating Area for TO-220FPSafe Operating Area for TO-220 Thermal Impedance for TO-220FPThermal Impedance for TO-220 Transfer CharacteristicsOutput Characteristics
Gate Charge vs Gate-source Voltage Normalized On Resistance vs Temperature Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Transconductance Static Drain-source On Resistance
Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature
Fig. 5:Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4:Gate Charge test Circuit Fig. 2:Unclamped Inductive WaveformFig. 1:Unclamped Inductive Load Test Circuit Fig. 3:Switching Times Test Circuit For Resistive Load
DIM. mm. inch A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L30 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 TO-220 MECHANICAL DATA
A B D E H G F 123F2 L4L5 DIM. mm. inch A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 TO-220FP MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com