STP7NC40

STP7NC40 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

N-CHANNEL 400V - 0.75Ω - 6A TO-220 PowerMESH™II MOSFET (1)ISD ≤6A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. ■ TYPICAL R DS (on) = 0.75Ω ■ EXCEPTIONAL dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ LOW GATE CHARGE

DESCRIPTION

The PowerMESH™II is the evolution of the first gen- eration of MESH OVERLAY™. The layout refine- ments introduced greatly improve the Ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness.

APPLICATIONS

■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS (● ) Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STP7NC40 400 V < 1 Ω 6 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 400 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 400 V VGS Gate- source Voltage ± 30 V ID Drain Current (continuos) at TC = 25°C 6A ID Drain Current (continuos) at TC = 100°C 4A IDM (● ) Drain Current (pulsed) 24 A PTOT Total Dissipation at TC = 25°C 100 W Derating Factor 0.8 W/°C dv/dt(1) Peak Diode Recovery voltage slope 3 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C TO-220 INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 1.25 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 320 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 400 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 234V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 3 A 0.75 1 Ω ID(on) On State Drain Current V DS > ID(on) x RDS(on)max, VGS =1 0 V Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 3 A 5.1 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 530 pF C oss Output Capacitance 90 pF C rss Reverse Transfer Capacitance 15 pF

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 200V, ID = 3 A R G = 4.7Ω VGS = 10V (see test circuit, Figure 3) 11 ns tr Rise Time 15 ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 320V, ID =6A, VGS = 10V 8.5 23 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp =320V, ID = 6 A R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 5) ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 6 A ISDM (2) Source-drain Current (pulsed) 24 A VSD (1) Forward On Voltage ISD = 6 A, VGS = 0 1.6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 6 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 280 1.4 ns µC A Safe Operating Area Thermal Impedence

Gate Charge vs Gate-source Voltage Capacitance Variations Transconductance Static Drain-source On Resistance Output Characteristics Transfer Characteristics

Source-drain Diode Forward Characteristics Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C

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