N-channel 68 V, 0.010 , 80 A, TO-220 STripFET™ II Power MOSFET

Document overview

  • Manufacturer or author: STMICROELECTRONICS
  • PDF pages: 12

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Revision history

Features

■ Exceptional dv/dt capability ■ 100% avalanche tested Application ■ Switching applications

Description

This Power MOSFET series realized with STMicroelectronics unique STripFET™ process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable in advanced high-efficiency switching applications. Figure 1. Internal schematic diagram Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area
  2. I SD ≤ 80 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, TJ ≤ TJMAX

Table 3. Thermal data

  1. 1.6mm from case for 10 sec

2 Electrical characteristics

Table 4. On/off states Table 5. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BV DSS vs temperature Figure 7. Static drain-source on resistance

0 ID(A)

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs Figure 12. Source-drain diode forward

0 Qg(nC)

12 VDD=34V

0 Qg(nC)100

3 Test circuits

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test Figure 17. Unclamped inductive waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Obsolete Product(s) - Obsolete Product(s)

A 4.40 4.60 0.17 3 0.181 b 0.61 0. 88 0.024 0.0 34 b1 1.14 1.70 0.044 0.066 c0 . 4 9 0.70 0.01 9 0.027 D 15.25 15.75 0.6 0.62 D1 1.27 0.050 E 10 10.40 0. 393 0.409 e 2.40 2.70 0.0 94 0.106 e1 4. 95 5.15 0.1 94 0.202 F1 . 2 3 1.32 0.04 8 0.051 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.0 94 0.107 L1 3 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L302 8.90 1.1 37 ∅P 3.75 3.85 0.147 0.151 Q2 . 6 5 2 . 95 0.104 0.116 Obsolete Product(s) - Obsolete Product(s)

5 Revision history

Table 8. Document revision history