STB6N52K3 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

■ 100% avalanche tested ■ Extremely high dv/dt capability ■ Gate charge minimized ■ Very low intrinsic capacitance ■ Improved diode reverse recovery characteristics ■ Zener-protected Application Switching applications

Description

These devices are made using the SuperMESH3™ Power MOSFET technology that is obtained via improvements applied to STMicroelectronics’ SuperMESH™ technology combined with a new optimized vertical structure. The resulting product has an extremely low on resistance, superior dynamic performance and high avalanche capability, making it especially suitable for the most demanding applications. Figure 1. Internal schematic diagram

5 A 70 W

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area

Table 3. Thermal data

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

Table 6. Switching times

integrity. These integrated Zener diodes thus avoid the usage of external components. Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

Table 8. Gate-source Zener diode

2.1 Electrical characteristi cs (curves)

Figure 2. Safe operating area for TO-220, Figure 3. Thermal impedance for TO-220, Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP Figure 6. Safe operating area for DPAK Figure 7. Thermal impedance for DPAK

Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Gate charge vs gate-source voltage Figure 11. Static drain-source on resistance Figure 12. Capacitance variations Figure 13. Output capacitance stored energy

0 Qg(nC)

3 Test circuits

Figure 19. Switching times test circuit for Figure 20. Gate charge test circuit Figure 21. Test circuit for inductive load Figure 22. Unclamped Inductive load test Figure 23. Unclamped inductive wavefo rm Figure 24. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Table 9. D²PAK (TO-263) mechanical data

Figure 25. D²PAK (TO-263) drawing

Table 10. DPAK (TO-252) mechanical data

Figure 26. DPAK (TO-252) drawing

Figure 27. TO-220FP drawing Table 11. TO-220FP mechanical data

Table 12. TO-220 type A mechanical data

Figure 28. TO-220 type A drawing

5 Packaging mechanical data

Figure 29. D²PAK footprint (a) Table 13. D²PAK (TO-263) tape and reel mechanical data

Figure 30. DPAK footprint (b) Table 14. DPAK (TO-252) tape and reel mechanical data

6 Revision history

Table 15. Document revision history 03-Sep-2008 1 Initial release. – Document status promoted from preliminary data to datasheet.