STP60NH2LL STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Appendix A
  • 5 Package mechanical data
  • 6 Revision history

N-channel 24V - 0.010Ω - 40A TO-220 STripFET™ Power MOSFET General features ■ RDS(ON) * Qg industry’s benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device

Description

The STP60NH2LL utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved.

Applications

■ Switching application Internal schematic diagram Type VDSS (@Tjmax) RDS(on) ID STP60NH2LL 24V <0.011 Ω 40A(1) 1. Value limited by wire bonding TO-220 Order codes Part number Marking Package Packaging STP60NH2LL P60NH2LL TO-220 Tube

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Guaranteed when external Rg=4.7 Ω and tf < tfmax
  2. Pulse width limited by safe operating area

Table 2. Thermal data

2 Electrical characteristics

Table 3. On/off states Table 4. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%
  2. Qoss = Coss* ∆ Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A

Table 5. Source drain diode

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test Figure 17. Unclamped inductive wavefo rm Figure 18. Switching time waveform

4 Appendix A

  • The low side (SW2) device requires:
  • Very low RDS(on) to reduce conduction losses
  • Small Qgls to reduce the gate charge losses
  • Small Coss to reduce losses due to output capacitance
  • Small Qrr to reduce losses on SW1 during its turn-on
  • The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
  • voltage to avoid the cross conduction phenomenon;
  • The high side (SW1) device requires:
  • Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate
  • Small Qg to have a faster commutation and to reduce gate charge losses
  • Low RDS(on) to reduce the conduction losses.

Figure 19. Buck converter: power losses estimation

Table 6. Power losses calculation

  1. Dissipated by SW1 during turn-on

Table 7. Parameters meaning

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L30 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 TO-220 MECHANICAL DATA

6 Revision history

Table 8. Revision history 31-May-2005 1 First release. 06-Sep-2006 2 The document has been reformatted. 31-Jan-2007 3 Typo mistake on Table 1.