STP4N52K3 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 21

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

■ 100% avalanche tested ■ Extremely high dv/dt capability ■ Gate charge minimized ■ Very low intrinsic capacitance ■ Improved diode reverse recovery characteristics ■ Zener-protected Application ■ Switching applications

Description

These SuperMESH3™ Power MOSFETs are the result of improvements applied to STMicroelectronics’ SuperMESH™ technology, combined with a new optimized vertical structure. These devices boast an extremely low on- resistance, superior dynamic performance and high avalanche capability, rendering them suitable for the most demanding applications. Figure 1. Internal schematic diagram

2.5 A (1)

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area

Table 3. Thermal data

  1. When mounted on 1inch sq FR-4 board, 2 oz Cu

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. is defined as a constant equivalent capac itance giving the same charging time as C oss when VDS

increases from 0 to 80% VDSS. Table 6. Switching times

Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: Pulse duration = 300 μs, duty cycle 1.5%

Table 8. Gate-source Zener diode

  1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area for TO-220 Figure 3. Thermal impedance for TO-220 Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP Figure 6. Safe operating area for DPAK, IPAK Figure 7. Thermal impedance for DPAK, IPAK

Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Normalized B VDSS vs temperature Figure 11. Static drain-source on-resistance Figure 12. Capacitance variations Figure 13. Gate charge vs gate-source voltage

2.35 VGS=10V

Figure 14. Normalized gate threshold voltage Figure 15. Normalized on-resistance vs Figure 16. Source-drain diode forward Figure 17. Maximum avalanche energy vs

1.0 TJ=-50°C

3 Test circuits

Figure 18. Switching times test circuit for Figure 19. Gate charge test circuit Figure 20. Test circuit for inductive load Figure 21. Unclamped Inductive load test Figure 22. Unclamped inductive waveform Figure 23. Switching time waveform

4 Package mechanical data

Table 9. DPAK (TO-252) mechanical data

Table 10. TO-220FP mechanical data

Figure 26. TO-220FP drawing

Table 11. TO-220 type A mechanical data

Figure 27. TO-220 type A drawing

Table 12. IPAK (TO-251) mechanical data

Figure 28. IPAK (TO-251) drawing

5 Packaging mechanical data

Table 13. DPAK (TO-252) tape and reel mechanical data

6 Revision history

Table 14. Document revision history 09-Nov-2010 1 First release. Updated packages order in Table 1: Device summary. Minor text changes on the cover page.