STP410N4F7AG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 13
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 TO-220 package information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID PTOT STP410N4F7AG 40 V 1.8 mΩ 180 A 365 W Designed for automotive applications and AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packing STP410N4F7AG 410N4F7 TO-220 Tube AM01475v1_Tab D(2, TAB) G(1) S(3)
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at Tcase = 25 °C 180 A Drain current (continuous) at Tcase = 100 °C 180 IDM(2) Drain current (pulsed) 720 A PTOT Total dissipation at Tcase = 25 °C 365 W EAS(3) Single pulse avalanche energy 1.9 J Tstg Storage temperature range -55 to 175 °C Tj Operating junction temperature range Notes: (1) Current is limited by package, the current capability of the silicon is 350 A at 25 °C. (2) Pulse width is limited by safe operating area. (3)Tj ≤ 175 °C, Iav=80A Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 0.41 °C/W Rthj-amb Thermal resistance junction-ambient max 62.5
2 Electrical characteristics
(Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 40 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 40 V µA VGS = 0 V, VDS = 40 V, Tcase = 125 °C(1) 100 IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 200 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 90 A 1.5 1.8 mΩ Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V - 11700 - pF Coss Output capacitance - 3500 - Crss Reverse transfer capacitance - 390 - Qg Total gate charge VDD = 20 V, ID = 180 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 140 - nC Qgs Gate-source charge - 65 - Qgd Gate-drain charge - 27 - Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 20 V, ID = 90 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and ) - 35 - ns tr Rise time - 200 - td(off) Turn-off delay time - 110 - tf Fall time - 44 -
Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD(1) Source-drain current 180 A VSD(2) Forward on voltage VGS = 0 V, ISD = 90 A - 1.3 V trr Reverse recovery time ISD = 180 A, di/dt = 100 A/µs, VDD = 32 V, Tj = 25 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 74.4 ns Qrr Reverse recovery charge - 115 nC IRRM Reverse recovery current - 3.1 A Notes: (1) Current is limited by package, the current capability of the silicon is 350 A at 25 °C. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
Test circuits STP410N4F7AG
3 Test circuits
Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 TO-220 package information
Figure 19: TO-220 type A package outline
Table 8: TO-220 type A mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95
5 Revision history
Table 9: Document revision history Date Revision Changes 25-May-2016 1 First release.