STP24DP05 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Datasheet sections
- 1 Summary description
- 1.1 Pin connection and description
- 2 Electrical ratings
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Recommended operating conditions
- 3 Electrical characteristics
- 4 Block diagram
- 5 Equivalent circuit and outputs
- 6 Timing diagrams
- 7 Feature description
- 7.1 DG: gradual outputs delay
- 7.2 Error detection condition
- 7.3 Phase one: “entering in detection mode”
- 7.4 Phase two: “error detection”
- 7.5 Phase three: “resuming to normal mode”
- 7.6 Shift registers data flow control
- 7.7 EFLAG/TFLAG - output detection and overtemperature monitoring
- 8 Typical application sc hematic
- 9 Typical characteristics
- 10 Package mechanical data
- 11 Revision history
Features
■ Low voltage power supply down to 3 V ■ 8 x 3 constant current output channels ■ Adjustable output current through external resistors ■ Short and open output error detection ■ Serial data IN/Parallel data OUT ■ Shift register data flow registers control ■ Accepts 3.3 V and 5 V micro driver ■ Output current: 5-80 mA ■ 25 MHz clock frequency ■ High thermal efficiency package
Description
The STP24DP05 is a monolithic, low voltage, low current power 24-bit shift register designed for LED panel displays. The device contains a 8 x 3-bit serial-in, parallel-out shift register that feeds a 8 x 3-bit D-type storage register. In the output stage, twenty-four regulated current sources were designed to provide 5-80 mA constant current to drive the LEDs. The 8x3 shift registers data flow sequence order can be managed with two dedicated pins. The STP24DP05 has a dedicated pin to activate the outputs with a sequential delay, that will prevent inrush current during outputs turn-ON. The device detection circuit checks 3 different conditions that can occur on the output line: short to GND, short to V O or open line. The data detection results are loaded in the shift registers and shifted out via the serial line output. The detection functionality is activated with a dedicated pin or as alternative, through a logic sequence that allows the user to enter or exit from detection mode. Through three external resistors, users can adjust the output current for each 8-channel group, controlling in this way the light intensity of LEDs. The STP24DP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 25 MHz, makes the device suitable for high data rate transmission. The 3.3 V of voltage supply is useful for applications that interface any micro from 3.3 V. TQFP48 Table 1. Device summary
1 Summary description
1.1 Pin connection and description
Figure 1. Pin connection Table 2. Current accuracy
3.3 V to 5 V 25 °C
Table 3. Pin description
2 SDI Serial data input
35 SDO Serial data output
4 CLK Clock for serial data
3 LE\\DM Data latch in both SH register
5 DM Detection mode pin
8 TF Thermal flag (open drain)
29 EF Error detection flag (open drain)
9 DG Gradual delay
32 OE-B
33 OE-G Output enable for G1 - 8
34 OE-R\\DM Output enable for R1 - 8
28 REXTR Control outputs R1 - 8
27 REXTG Control outputs G1 - 8
26 REXTB Control outputs B1 - 8
10 DF0 Data banks flow bit 0
11 DF1 Data banks flow bit 1
31 VDD Supply voltage terminal
2 Electrical ratings
2.1 Absolute maximum ratings
Table 4. Absolute maximum ratings Table 5. Thermal data
2.3 Recommended operating conditions
Table 6. Recommended operating conditions
- If the device is connected in ca scade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
25 MHz
3 Electrical characteristics
Table 7. Electrical characteristics
Table 8. Switching characteristics (VDD = 5 V, T = 25 °C, unless otherwise specified.)
- In order to achieve high cascade data transfe r, please consider tr/tf timings carefully.
4 Block diagram
Figure 2. Block diagram
5 Equivalent circuit and outputs
Figure 3. OExx terminal Figure 4. LE\\DM terminal Figure 5. CLK, SDI terminal
6 Timing diagrams
Figure 8. Timing diagram Note: The latches circuit holds data when the LE terminal is low.
1 When LE\\DML terminal is at high level, latch circuit hold the data it passes from the input to
2 When either OE-R\\DM , OE-G, OE-B terminals are at low level, output terminals R\\G\\B1 to
R\\G\\B8 respond to the data, either ON or OFF .
3 When either OE-R\\DM , OE-G, OE-B terminals are at high level, it switches off all the data on
the output terminal R\\G\\B1 to R\\G\\B8.
Figure 9. Clock, serial-in, serial-out
7 Feature description
7.1 DG: gradual outputs delay
This feature prevents large inrush current and reduces the bypass capacitors. delay and R3, G3, B3, has 40 ns delay, etc.
7.2 Error detection condition
Table 9. Typical gradual delay time table Table 10. Detection conditions (VDD = 3.3 to 5 V, IO = 20 mA, tA = 25 °C) Table 11. Typical current threshold values to detect LED open line
Figure 12. Detection circuit
7.3 Phase one: “enterin g in detection mode”
Figure 13. EDM timing diagram using DM pin Table 12. SPI sequence to enter in detection mode - truth table
rise front of CLK the SDI data are ready for the sampling.
7.4 Phase two: “error detection”
The eight data bits must be set “1“ in order to set ON all the outputs during the detection. LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 14. SPI sequence to enter in detection mode - time diagram Figure 15. Detection diagram
7.5 Phase three: “resuming to normal mode”
"resume mode" sequence, it is not possible to insert consecutive equal sequence.
7.6 Shift registers data flow control
Table 13. SPI sequence to resume in normal mode - truth table Table 14. Shifter register data flow control
7.7 EFLAG/TFLAG - output de tection and overtemperature
The open-drain output EFLAG and TFLAG are used to report the STP24DP05 error flags. external resistor. When an error is detected, the internal switch is turned on, to GND. Figure 16. TF and EF test circuit
8 Typical application schematic
Figure 17. Typical application schematic
9 Typical characteristics
Figure 18. Typical external resistor values vs output current capabilities Figure 19. Typical dropout voltage vs output current Table 15. Typical external resistor values vs output current capabilities Table 16. Typical dropout voltage vs output current
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 20. TQFP48 mechanical data
Figure 21. TQFP48 tape and reel
Table 17. Document revision history