STP100NF04L

STP100NF04L STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 40V - 0.0036 Ω - 100A TO-220 STripFET™ II POWER MOSFET ■ TYPICAL R DS (on) = 0.0036 Ω ■ LOW THRESHOLD DRIVE ■ 100% AVALANCHE TESTED ■ LOGIC LEVEL DEVICE

DESCRIPTION

This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low on- resistance, rugged avalanche characteristics and less critical alignment steps therefore a remark- able manufacturing reproducibility.

APPLICATIONS

■ HIGH CURRENT, HIGH SWITCHING SPEED ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS ■ SOLENOID AND RELAY DRIVERS TYPE VDSS R DS(on) ID STP100NF04L 40 V <0.0042 Ω 100 A TO-220 ABSOLUTE MAXIMUM RATINGS (•) Pulse width limited by safe operating area. (*) Current Limited by package (1) ISD ≤100A, di/dt ≤240A/µs, VDD ≤ 32V, Tj ≤ TJMAX (2) Starting Tj = 25 oC, IAR = 50A, VDD = 30V Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 40 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 40 V VGS Gate- source Voltage ± 16 V ID (*) Drain Current (continuos) at TC = 25°C 100 A ID Drain Current (continuos) at TC = 100°C 70 A IDM (•) Drain Current (pulsed) 400 A Ptot Total Dissipation at TC = 25°C 300 W Derating Factor 2 W/°C dv/dt (1) Peak Diode Recovery voltage slope 3.6 V/ns EAS (2) Single Pulse Avalanche Energy 1.4 J Tstg Storage Temperature -65 to 175 °C Tj Max. Operating Junction Temperature 175 °C INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF ON (*) DYNAMIC Rthj-case Rthj-amb Tj Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ 0.5 62.5 300 °C/W °C/W Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 40 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS I D = 250 µA 1V R DS(on) Static Drain-source On Resistance VGS = 10 V I D = 50 A VGS = 4.5 V I D = 50 A 0.0036 0.0040 0.0042 0.0065 Ω Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (*) Forward Transconductance VDS = 15 V I D = 20 A 50 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25V, f = 1 MHz, VGS = 0 6400 1300 190 pF pF pF

(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 20 V I D = 50 A R G = 4.7 Ω V GS = 4.5 V (Resistive Load, Figure 3) 270 ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 32V ID = 100A VGS = 4.5V 72 28.5 90 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit t d(off) tf Turn-off Delay Time Fall Time VDD = 20 V D = 50 A R G = 4.7Ω, V GS = 4.5 V (Resistive Load, Figure 3) ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time V clamp = 32 V I D = 100 A R G = 4.7Ω, V GS = 4.5 V (Inductive Load, Figure 5) 125 160 ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit I SD ISDM (•) Source-drain Current Source-drain Current (pulsed) 100 400 A A VSD (*) Forward On Voltage ISD = 100A V GS = 0 1.3 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 100 A di/dt = 100A/µs VDD = 20 V T j = 150°C (see test circuit, Figure 5) 240 5.5 ns nC A ELECTRICAL CHARACTERISTICS (continued) Thermal ImpedanceSafe Operating Area

Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage Temperature. . .

Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C

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