STQ1NK60ZR-AP_07 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuit
- 4 Package mechanical data
- 5 Revision history
Features
■ 100% avalanche tested ■ Extremely high dv/dt capability ■ Gate charge minimized ■ ESD improved capability ■ New high voltage benchmark
Description
The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. Application ■ Switching applications Figure 1. Internal schematic diagram Table 1. Device summary
1 Electrical ratings
Table 2. Absolute maximum ratings
- Pulse width limited by safe operating area
Table 3. Thermal resistance
- When mounted on 1 inch² FR-4 board, 2 Oz Cu
Table 4. Avalanche data
2 Electrical characteristics
Table 5. On/off states Table 6. Dynamic
- Pulsed: pulse duration=300µs, duty cycle 1.5%
- C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
Table 7. Switching times Table 8. Source drain diode
- Pulse width limited by safe operating area
- Pulsed: pulse duration=300µs, duty cycle 1.5%
Table 9. Gate-source zener diode
- The built-in back-to-back Zener diodes have sp ecifically been designed to enhance not only the device’s
usage of external components.
2.1 Electrical characterist ics (curves)
Figure 2. Safe operating area for IPAK Figure 3. Thermal impedance for IPAK Figure 4. Safe operating area for TO-92 Figure 5. Thermal impedance for TO-92 Figure 6. Safe operating area for SOT-223 Figure 7. Thermal impedance for SOT-223
3 Test circuit
Figure 20. Switching times test circuit for Figure 21. Gate charge test circuit Figure 22. Test circuit for inductive load Figure 23. Unclamped inductive load test Figure 24. Unclamped inductive wavefo rm Figure 25. Switching time waveform
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
DIM. mm. inch A 4.32 4.95 0.170 0.194 b 0.36 0.51 0.014 0.020 D 4.45 4.95 0.175 0.194 E 3.30 3.94 0.130 0.155 e 2.41 2.67 0.094 0.105 e1 1.14 1.40 0.044 0.055 L 12.70 15.49 0.50 0.610 R 2.16 2.41 0.085 0.094 S1 0.92 1.52 0.036 0.060 W 0.41 0.56 0.016 0.022 V5 ° 5 ° TO-92 MECHANICAL DATA
DIM. mm. inch A1 4.45 4.95 0.170 0.194 T3 . 3 0 3 . 9 4 0 . 1 3 0 0 . 1 5 5 T1 1.6 0.06 T2 2.3 0.09 d0 . 4 1 0 . 5 6 0 . 0 1 6 0 . 0 2 2 delta H -2 2 -0.08 0.08 W 1 7 . 51 8 1 90 . 6 9 0 . 7 1 0 . 7 4 W2 0.5 0.02 H 1 8 . 52 0 . 5 0 . 7 20 . 8 0 H1 25 0.98 t0 . 9 0 . 0 3 5 L1 1 0 . 4 3 l1 3 0.11 delta P -1 1 -0.04 0.04 TO-92 AMMOPACK
DIM. mm inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 0.033 B5 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A C H D LL2 1 3 = = B E G = = = = TO-251 (IPAK) MECHANICAL DATA 0068771-E
DIM. mm mils e4 0.32 12.6 C CB E L a b f g c d P008B SOT-223 MECHANICAL DATA
5 Revision history
Table 10. Revision history 15-Feb-2005 7 Modified Figure 4.