STM32C011D4U3

STM32C011X4 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 94

Technical content

Datasheet sections

• 1 Introduction
• 2 Description
• 3 Functional overview
• 3.1 Arm ® Cortex®-M0+ core with MPU
• 3.2 Memory protection unit
• 3.3 Embedded flash memory
• 3.4 Embedded SRAM
• 3.5 Boot modes
• 3.6 Cyclic redundancy check calculation unit (CRC)
• 3.7 Power supply management
• 3.7.1 Power supply schemes
• 3.7.2 Power supply supervisor
• 3.7.3 Voltage regulator
• 3.7.4 Low-power modes
• 3.7.5 Reset mode
• 3.8 Interconnect of peripherals
• 3.9 Clocks and startup
• 3.10 General-purpose inputs/outputs (GPIOs)
• 3.11 Direct memory access controller (DMA)
• 3.12 DMA request multiplexer (DMAMUX)
• 3.13 Interrupts and events
• 3.13.1 Nested vectored interrupt controller (NVIC)
• 3.13.2 Extended interrupt/event controller (EXTI)
• 3.14 Analog-to-digital converter (ADC)
• 3.14.1 Temperature sensor
• 3.14.2 Internal volt age reference (VREFINT)
• 3.15 Timers and watchdogs
• 3.15.1 Advanced-control timer (TIM1)
• 3.15.2 General-purpose timers (TIM3, 14, 16, 17 )
• 3.15.3 Independent watchdog (IWDG)
• 3.15.4 System window watchdog (WWDG)

Datasheet sections

• 5.3.16 Temperature sensor characteristics
• 5.3.17 Timer characteristics
• 5.3.18 Characteristics of communication interfac es
• 6 Package information
• 6.1 SO8N package information
• 6.2 WLCSP12 package information
• 6.3 TSSOP20 package information
• 6.4 UFQFPN20 package information
• 7 Ordering information
• 8 Important security notice
• 9 Revision history

Features

• Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 48 MHz
• -40°C to 85°C/105°C/125°C operating temperature
• Memories – Up to 32 Kbytes of flash memory with protection – 6 Kbytes of SRAM with HW parity check
• CRC calculation unit
• Reset and power management – Voltage range: 2.0 V to 3.6 V – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Low-power modes: Sleep, Stop, Standby, Shutdown
• Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 48 MHz RC oscillator (±1 %) – Internal 32 kHz RC oscillator (±5 %)
• Up to 18 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os
• 3-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 13 ext. channels) – Conversion range: 0 to 3.6 V
• 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
• Calendar RTC with alarm
• Communication interfaces – One I 2C-bus interface supporting Fast- mode Plus (1 Mbit/s) with extra current sink, supporting SMBus/PMBus and wakeup from Stop mode – Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature – One SPI (24 Mbit/s) with 4- to 16-bit programmable bitframe, multiplexed with I 2S interface
• Development support: serial wire debug (SWD)
• All packages ECOPACK 2 compliant

Table 1. Device summary

3.18 Universal synchronous/asynchronous re ceiver transmitter (USART) . . . 24

5.3.6 Wakeup time from low-power modes and voltage scaling

Table 39. LSE oscillator characteristics (f

Introduction STM32C011x4/x6 8/94 DS13866 Rev 3

1 Introduction

This document provides information on STM32C011x4/x6 microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes. Information on memory mapping and control registers is object of reference manual. Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (o r its subsidiaries) in the US and/or elsewhere.

2 Description

and appliance domains and ready for the Internet of Things (IoT) solutions. protection), DMA, an extensive range of system functions, enhanced I/Os, and peripherals. modes allows the design of low-power applications. The devices are housed in packages with 8 to 20 pins. Table 2. STM32C011x4/x6 family device features and peripheral counts

1. The number in brackets denotes the count of SPI interfaces configurable as I2S interface.
2. Depends on order code. Refer to Section 7: Ordering information for details.

Figure 1. Block diagram

STM32C011x4/x6 Functional overview

3 Functional overview

3.1 Arm ® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU). The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Owing to embedded Arm core, the STM32C011x4/x6 devices are compatible with Arm tools and software. The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.13.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded flash memory

STM32C011x4/x6 devices feature up to 32 Kbytes of embedded flash memory available for storing code and data.

• Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: th e flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug fe atures (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

3.4 Embedded SRAM

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5 Boot modes

• boot from User flash memory
• boot from System memory
• boot from embedded SRAM The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the flash memory reprogramming through one of the following interfaces:
• USART on pins PA9/PA10
• I2C-bus on pins PB6/PB7

Table 3. Access status versus readout protection level and execution modes

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

STM32C011x4/x6 Functional overview

3.6 Cyclic redundancy che ck calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32C011x4/x6 devices require a 2.0 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals: VDD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin. The minimum voltage of 2.0 V corresponds to power-on reset release threshold VPOR(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold VPDR(min) of 1.96 V.

• VDDA = 2.0 V (1.96) (ADC) to 3.6 V VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.
• VDDIO1 = VDD VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage. VREF+ is internally connected with VDD.
• VCORE An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the power supply for digital peripherals, SRAM and flash memory. The flash memory is also supplied with VDD.

Figure 2. Power supply overview

3.7.2 Power supply supervisor

rising VDD and other four for falling VDD.

3.7.3 Voltage regulator

An embedded linear voltage regulator supplies most of the digital circuitry in the device. impedance state, such as to bring its current consumption close to zero.

3.7.4 Low-power modes

• Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode In Stop mode, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the V CORE are stopped. The HSE and HSI48 VDDA domain RTC domain A/D converter Standby circuitry (Wakeup logic, IWDG) Voltage regulator Core SRAM Digital peripherals LSE 32KHz RCC BDCR register RTC I/O ring VCORE domain Temp. sensor Reset block HSI48 Flash memory VDDIO1 VDD domain VCORE VSS VDD VDDA VREF+ VSSA VSS VDD

STM32C011x4/x6 Functional overview stop. The HSI48 can be restarted by a peripheral with wake-up capability requiring HSI48. The LSE and LSI can be kept running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as system clock.

• Standby mode The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The regulator is switched off to power down V CORE domain. The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The RTC is switched off. For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, register contents are lost, except for 16-bit backup registers whose contents are kept. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge), or when a failure is detected on LSE (CSS on LSE).
• Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The HSI48 and LSI RC- oscillators and HSE crystal oscillator are also powered down. The RTC is off. The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. SRAM and register contents are lost. The device exits Shutdown mode upon external reset event (NRST pin), or wakeup event (WKUP pin, configurable rising or falling edge).

3.7.5 Reset mode

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

3.9 Clocks and startup

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• System clock source: the clock following sources can deliver SYSCLK system clock: – 4-48 MHz high-speed oscillator with exter nal crystal or ceramic resonator (HSE). The HSE can also be configured in bypass mode for an external clock. – 48 MHz high-speed internal RC oscillato r (HSI48), trimmable by software. – LSE - a low-speed oscillator wit h external crystal (32768 Hz) – LSI - an internal low-s peed RC oscillator (32 kHz)

Table 4. Interconnect of peripherals

STM32C011x4/x6 Functional overview

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with exte rnal crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.
• Peripheral clock sources: several peripherals ( I2S, USARTs, I2C, ADC) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE or LSE clock failure, the system clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software interrupt is generated. The CCS feature can be enabled by software.
• Clock output: – MCO (microcontroller clock output) provides one of the internal clocks for external use by the application – LSCO (low speed clock output) provides LSI or LSE in all low-power modes . Several prescalers allow the application to configure AHB and APB domain clock frequencies, 48 MHz at maximum.

3.10 General-purpose in puts/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions. Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory a ccess controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture. With 3 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU. Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests. Main features of the DMA controller:

• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to- peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable: – Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

Functional overview STM32C011x4/x6 18/94 DS13866 Rev 3 – Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2). – Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size. – Support of transfers from/to peripherals to/from memory with circular buffer management – Programmable number of data to be transferred: 0 to 2 16 - 1

• Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request mu ltiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow. The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored inte rrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management. The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset. If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

STM32C011x4/x6 Functional overview ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency. Features of the NVIC:

• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode. The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels. The channels can be independently masked. The EXTI controller can capture pulses shorter than the internal clock period. A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32C011x4/x6 devices. The ADC has up to 13 external channels and 2 internal channels (temperature sensor, voltage reference). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of 2.5 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase. The ADC can be served by the DMA controller. It can operate in the whole V DD supply range. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. output voltage into a digital value. is suitable only for relative temperature measurements. accessible in read-only mode.

3.14.2 Internal voltage reference (V REFINT)

engineering bytes. It is accessible in read-only mode.

3.15 Timers and watchdogs

advanced-control, general-purpose and basic timers. Table 5. Temperature sensor calibration values Table 6. Internal voltage reference calibration values Table 7. Timer feature comparison

3.15.1 Advanced-control timer (TIM1)

• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.15.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

3.15.2 General-purpose time rs (TIM3, 14, 16, 17)

or act as a simple timebase.

• TIM3 This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter and 16-bit prescaler. It has four independent channels for input capture/output compare, PWM or one-pulse mode output. It can operate in combination with other general-purpose timers via the Timer Link feature for synchronization or event chaining. It can generate independent General- purpose TIM3 16-bit Up, down, up/down 48 MHz Integer from 1 to 216 Yes 4 - TIM14 16-bit Up 48 MHz Integer from 1 to 216 No 1 - TIM16 TIM17 16-bit Up 48 MHz Integer from 1 to 216 Yes 1 1

Table 7. Timer feature comparison (continued)

Functional overview STM32C011x4/x6 22/94 DS13866 Rev 3 DMA request and support quadrature encoders. Its counter can be frozen in debug mode.

• TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.
• TIM16, TIM17 These are general-purpose timers featuring: – 16-bit auto-reload upcounter and 16-bit prescaler – 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

3.15.3 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.15.4 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

3.15.5 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter. Features of SysTick timer:

• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

3.16 Real-time clock (RTC)

The device embeds an RTC located in the RTC domain and supplied from VCORE. The RTC is an independent BCD timer/counter.

STM32C011x4/x6 Functional overview Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy
• Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin
• Multiple clock sources and references: – a 32.768 kHz external crystal (LSE) – an external resonato r or oscillator (LSE) – the internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) – the high-speed external clock (HSE) divided by 32 The RTC operates in Run, Sleep, and Stop mode. RTC events (Alarm, Timestamp) can generate an interrupt and wake the device up from the low-power modes.

3.17 Inter-integrated ci rcuit interface (I2C)

The device embeds one I2C peripheral. Refer to Table 8 for the features. The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

• I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes , multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Clock stretching
• SMBus specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I communication speed to be independent of the PCLK reprogramming
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

3.18 Universal synchronous/asynch ronous receiver transmitter

communicate at speeds of up to 6 Mbit/s. Table 8. I2C implementation

• start bit detection
• any received data frame
• a specific programmed data frame All USART interfaces can be served by the DMA controller.

3.19 Serial peripheral interface (SPI)

peripherals support NSS pulse mode, TI mode and hardware CRC calculation. The SPI peripherals can be served by the DMA controller. Table 9. USART implementation

3.20 Development support

3.20.1 Serial wire debug port (SW-DP)

Table 10. SPI/I2S implementation

4 Pinouts, pin description and alternate functions

Figure 3. STM32C011JxM SO8N pinout Figure 4. STM32C011DxY WLCSP12 ballout

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified. Table 11. Terms and symbols used in Table 12 (continued) Table 12. Pin assignment and description

2 C4 4 2 VDD/VDDA S - - - -

3 E4 5 3 VSS/VSSA S - - - -

4 F3 6 4 PF2-NRST I/O - - MCO, TIM1_CH4 NRST

6 E2 17 15 PA12 [PA10] I/O FT (1)

8 C2 19 17 PA14-BOOT0 I/O FT (2)

Table 12. Pin assignment and description (continued)

1. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.
2. Upon reset, these pins are configured as SWD alternate functions, and the internal pull-up on PA13 pin and the internal

pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping (AF0 to AF7)

Table 14. Port A alternate function mapping (AF8 to AF15) Table 15. Port B alternate function mapping (AF0 to AF7) Table 16. Port B alternate function mapping (AF8 to AF15) Table 17. Port C alternate function mapping (AF0 to AF7) Table 18. Port C alternate function mapping (AF8 to AF15)

Table 19. Port F alternate function mapping

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS. information scope are to be ignored. commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

the selected temperature range). mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

are given only as design guidelines and are not tested. error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage

5.1.6 Power supply scheme

Figure 9. Power supply scheme functionality of the device.

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

conditions for extended periods may affect device reliability. Table 20. Voltage characteristics

1. V IN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the inte rnal pull-up/pull-down resistors must be disabled.

Table 21. Current characteristics

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum

1. A positive injection is induced by V IN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be

exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.

1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative

injected currents (instantaneous values). Table 22. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

5.3.2 Operating conditions at power-up / power-down

temperature condition summarized in Table 23.

5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 23. Table 23. General operating conditions

1. When RESET is released func tionality is guaranteed down to VPDR min.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The T A(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided

that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.5: Thermal characteristics.

1. Temperature range digit in the order code. See Section 7: Ordering information.

Table 24. Operating conditions at power-up / power-down Table 25. Embedded reset and power control block characteristics

5.3.4 Embedded voltage reference

1. Specified by design – Not tested in production.

Table 25. Embedded reset and power control block characteristics (continued) Table 26. Embedded internal voltage reference

1. The shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design – Not tested in production.

Figure 11. VREFINT vs. temperature

5.3.5 Supply current characteristics

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0490 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS Unless otherwise stated, values given in Table 27 through Table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. MSv40169V1 1.185 1.19 1.195 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 -40 -20 0 20 40 60 80 100 120 V Mean Min Max

Table 27. Current consumption in Run mode from flash memory at different die temperatures

1. Evaluated by characterization – Not tested in production.
2. V DD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Prefetch and cache enabled when fetching from flash memory.

48 MHz

Table 28. Current consumption in Run mode from SRAM at different die temperatures

1. Evaluated by characterization – Not tested in production.
2. V DD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Code compiled with high optim ization for space in SRAM.

Table 29. Typical current consumption in Run depending on code executed

16 MHz

2 MHz

1. V DD = 3.0 V, all peripherals disabled
2. Prefetch and cache enabled when fetching from flash
3. Reduced code used for characterization results provided in Table 27.

Table 29. Typical current consumption in Run depending on code executed (continued)

Table 30. Current consumption in Sleep mode

1. Evaluated by characteriza tion – Not tested in production.

Table 31. Current consumption in Stop mode

2 V 605 630 675 765 640 850 1100 1600

2.4 V 605 630 675 765 640 850 1100 1600

3 V 605 630 675 765 640 850 1200 1600

3.6 V 605 635 680 770 640 850 1200 1600

1. Evaluated by characterization – Not tested in production.

Table 32. Current consumption in Standby mode

1. Evaluated by characterization – Not tested in production.

Table 33. Current consumption in Shutdown mode

1. Evaluated by characterization – Not tested in production.

STM32C011x4/x6 Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 34: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where I SW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIO1 is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW VDDIO1 fSW C××=

• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 20: Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Table 34. Current consumption of peripherals

Table 34. Current consumption of peripherals (continued) Table 35. Low-power mode wakeup times(1)

12 MHz

1. Evaluated by characterization – Not tested in production.

5.3.7 External clock source characteristics

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. Figure 12 for recommended clock input waveform. Figure 12. High-speed external clock source AC timing diagram In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. Figure 13 for recommended clock input waveform. Table 36. High-speed external user clock characteristics(1)

1. Specified by design – Not tested in production.

Table 37. Low-speed external user clock characteristics(1)

Figure 13. Low-speed external clock source AC timing diagram (frequency, package, accuracy).

1. Specified by design – Not tested in production.

Table 37. Low-speed external user clock characteristics(1) (continued) Table 38. HSE oscillator characteristics(1)

design guide for ST microcontrollers” available from the ST website www.st.com.

1. Specified by design – Not tested in production.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the t SU(HSE) startup time
4. t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is

Table 38. HSE oscillator characteristics(1) (continued)

Figure 14. Typical application with an 8 MHz crystal

1. R EXT value depends on the crystal characteristics.

design guide for ST microcontrollers” available from the ST website www.st.com.

8 MHz

Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

1. Specified by design – Not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
3. t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

Figure 15. Typical application with a 32.768 kHz crystal

5.3.8 Internal clock source characteristics

conditions. The provided curves are characterization results, not tested in production. Table 40. HSI48 oscillator characteristics

1. Based on characterization results, not tested in production
2. Specified by design – Not tested in production.

Figure 16. HSI48 frequency versus temperature Table 41. LSI oscillator characteristics

1. Evaluated by characterization – Not tested in production.
2. Specified by design – Not tested in production.

Table 42. Flash memory characteristics(1)

1. Specified by design – Not tested in production.
2. Values provided also apply to devices wi th less flash memory than one 32 Kbyte bank

Table 42. Flash memory characteristics(1) (continued) Table 43. Flash memory endurance and data retention

1. Evaluated by characterization – Not tested in production..
2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization. While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 44. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers)

Table 44. EMS characteristics

to prevent unrecoverable errors occurring (see application note AN1015). IEC 61967-2 standard which specifies the test board and the pin loading.

5.3.11 Electrical sens itivity characteristics

stressed in order to determine its performance in terms of electrical sensitivity. conforms to the ANSI/JEDEC standard. Table 45. EMI characteristics

48 MHz /

0.1 MHz to 30 MHz 3 3

30 MHz to 130 MHz 5 -2

130 MHz to 1 GHz 1 -1

1 GHz to 2 GHz 7 8

Table 46. ESD absolute maximum ratings

1. Evaluated by characterization – Not tested in production.

• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard.

5.3.12 I/O current in jection characteristics

are performed on a sample basis during device characterization. the I/O pin, one at a time, the device is checked for functional failures. oscillator frequency deviation). leakage current is caused by positive injection. Table 47. Electrical sensitivity Table 48. I/O current injection susceptibility(1)

1. Evaluated by characterization – Not tested in production.
2. The injection current value is applicable when the sw itchable diode is activated, NA when not activated.

5.3.13 I/O port characteristics

I/Os are designed as CMOS- and TTL-compliant. Table 49. I/O static characteristics

1. Refer to Figure 17: I/O input characteristics.
2. Specified by design – Not tested in production.
3. This parameter represents the pad leakage of the I/O itse lf. The total product pad leakage is provided by the following

formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

1. Pull-up and pull-down resistors are designed with a true re sistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

Figure 17. I/O input characteristics ±15 mA with relaxed VOL/VOH.

• The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 20: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 20: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). MSv37613V1 Tested in production CMOS requirement Vih min = 0.7xV DDIOx Based on simulation Vih min = 0.61xV DDIOx +0.05 for 1.08<V DDIOx <1.62 or 0 .49xV DDIOx+0.26 for V DDIOx>1.62 Based on simulation Vil max =0.43xV DDIOx -0.1 for 1.08<V DDIOx<1.62 or 0.39xV DDIOx-0.06 for V DDIOx >1.62 Tested in production CMOS requirement Vil max = 0.3xVdd TTL requirement Vih min = 2V TTL requirement Vil max = 0.8V

Table 50. Output voltage characteristics(1)

1. The I IO current sourced or sunk by the device must always respect the absolute maximum rating specified inTable 20:

respect the absolute maximum ratings ∑IIO.

1. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
2. Specified by design – Not tested in production.

Table 51. I/O AC characteristics(1)(2)

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0490 reference manual for a description of GPIO Port configuration register.

1. Specified by design – Not tested in production.
2. The fall time is defined between 70% and 30% of the output waveform, according to I
3. This value represents the I/O c apability but the maximum system frequency is limited to 48 MHz.

Table 51. I/O AC characteristics(1)(2) (continued)

Figure 18. I/O AC characteristics definition(1)

1. Refer to Table 51: I/O AC characteristics.

5.3.14 NRST input characteristics

in Table 23: General operating conditions. Table 52. NRST pin characteristics

1. Specified by design – Not tested in production..
2. The pull-up is designed with a true resist ance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

Figure 19. Recommended NRST pin protection

1. The reset network protects t he device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in

Table 52: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

1. The external capacitor on NRST must be placed as close as possible to the device.

5.3.15 Analog-to-digital converter characteristics

conditions summarized in Table 23: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 53. ADC characteristics(1)

1. Specified by design – Not tested in production.
2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate

functions for further details. Table 53. ADC characteristics(1) (continued)

Table 54. Maximum ADC RAIN .

1. Specified by design – Not tested in production.

Table 55. ADC accuracy(1)(2)

1. Evaluated by characterization – Not tested in production.
2. ADC DC accuracy values are measured after internal calibration.

Figure 20. ADC accuracy characteristics Figure 21. Typical connection diagram using the ADC

1. Refer to Table 53: ADC characteristics for the values of RAIN and CADC.
2. C parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

1. Refer to Table 49: I/O static characteristics for the values of Ilkg.
2. Refer to Figure 2: Power supply overview.

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme.

1 LSB ideal

5.3.16 Temperature sensor characteristics

5.3.17 Timer characteristics

characteristics (output compare, input capture, external clock, PWM output). Table 56. TS characteristics

1. Specified by design – Not tested in production.
2. Evaluated by characterization – Not tested in production.

DDA = 3.3 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Table 57. TIMx(1) (2)characteristics

1. TIMx , is used as a general term to refer to the TIM1 and TIM17 timers.
2. Specified by design – Not tested in production.

5.3.18 Characteristics of communication interfaces

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the minimum shown in the following table. The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins

Table 58. IWDG min/max timeout period at 32 kHz LSI clock(1)

1. The exact timings further depend on the phase of the APB inte rface clock versus the LSI clock, which causes an

uncertainty of one RC period. Table 59. Minimum I2CCLK frequency

port characteristics for the I2C I/Os characteristics.

• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 60. I2C analog filter characteristics(1)

1. Specified by design – Not tested in production.
2. Spikes shorter than the limiting duration are suppressed.

Table 61. SPI characteristics(1)

Figure 22. SPI timing diagram - slave mode and CPHA = 0

1. Evaluated by characterization – Not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t v(SO) and tsu(MI) which has to fit into SCK low

Table 61. SPI characteristics(1) (continued)

Figure 25. I2S slave timing diagram (Philips protocol) Table 62. I2S characteristics(1)

1. Evaluated by characterization – Not tested in production.

1. Measurement points are done at CMOS levels: 0.3 V DDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previ ously transmitted byte. No LSB transmit/receive is sent before the first

Figure 26. I2S master timing diagram (Philips protocol)

1. Evaluated by characterization – Not tested in production.
2. LSB transmit/receive of the previ ously transmitted byte. No LSB transmit/receive is sent before the first

• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART). MSv39720V1 CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) 10% 90%

Table 63. USART characteristics

6 Package information

specifications, grade definitions and product status are available at: www.st.com.

6.1 SO8N package information

SO8N is an 8-lead 4.9 x 6 mm plastic small-outline package with 150 mils body width. Figure 27. SO8N – Outline Table 64. SO8N – Mechanical data

Figure 28. SO8N – Footprint example

1. Dimensions are expr essed in millimeters.

The printed markings may differ depending on the supply chain. operations, are not indicated below.

1. Values in inches are converted fr om mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
3. Dimension “E1” does not includ e interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25 mm per side. Table 64. SO8N – Mechanical data (continued)

Figure 29. SO8N package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.2 WLCSP12 package information

Figure 30. WLCSP12 – Outline

1. Dimension is measured at the maximum bum p diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of

axis perpendicular to datum Z of each ball must lie within this tolerance zone.

Table 65. WLCSP12 – Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal

and tolerances values of A1 and A2.

1. Back side coating. Nominal di mension is rounded to the 3rd decimal place resulting from process
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Calculated dimensions are rounded to the 3rd decimal place
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of

axis perpendicular to datum Z of each ball must lie within this tolerance zone.

1. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.

therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

6.3 TSSOP20 pac kage information

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch. Figure 33. TSSOP20 – Outline Table 67. TSSOP20 – Mechanical data

Figure 34. TSSOP20 – Footprint example

1. Dimensions are expr essed in millimeters.

The printed markings may differ depending on the supply chain. operations, are not indicated below.

1. Values in inches are converted fr om mm and rounded to four decimal digits.
2. Dimension “D” does not include mold fl ash, protrusions or gate burrs. Mold flash, protrusions or gate burrs

shall not exceed 0.15 mm per side.

1. Dimension “E1” does not include interlead flash or pr otrusions. Interlead flash or protrusions shall not

Table 67. TSSOP20 – Mechanical data (continued)

Figure 35. TSSOP20 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.4 UFQFPN20 package information

UFQFPN20 is a 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 36. UFQFPN20 – Outline

Figure 37. UFQFPN20 – Footprint example

1. Dimensions are expr essed in millimeters.

Table 68. UFQFPN20 – Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

The printed markings may differ depending on the supply chain. operations, are not indicated below. Figure 38. UFQFPN20 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

STM32C011x4/x6 Ordering information

7 Ordering information

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office. Example STM32 C 011 F 6 P 6 xyy Device family STM32 = Arm® based 32-bit microcontroller Product type C = general-purpose Device subfamily 011 = STM32C011 Pin count J = 8 D = 12 F = 20 Flash memory size 4 = 16 Kbytes 6 = 32 Kbytes Package type U = UFQFPN Y = WLCSP P = TSSOP M = SO˽N Temperature range 6 = -40 to 85°C (105°C junction) 7 = -40 to 105°C (125°C junction) 3 = -40 to 125°C (130°C junction) Options TR = tape and reel packing = tray packing other = 3-character ID incl. custom Flash code and packing information

Important security notice STM32C011x4/x6 92/94 DS13866 Rev 3

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

9 Revision history

Table 69. Document revision history 14-Sep-2022 2 Fixed typo errors.

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