STM1403 STMICROELECTRONICS | Alldatasheet
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Figure 1. Package Table 1. Device Options Note: 1. SAL, RST, PFO, and BLD are Open Drain.
- Normal Mode: Low when VOUT is internally switched to VCC and High when VOUT is internally switched to battery.
- Pin 9 is the VREF pin for STM1403A. It is the VTPU pin for STM1403B/C.
VTPU (internally switched VCC or VBAT ). when SAL is driven low (activated). holds the cryptographic codes). profile, 16-pin QFN package. Figure 2. Logic Diagram Note: 1. VREF only for STM1403A; VTPU for STM1403B/C.
- Normal Mode: Low when VOUT is internally switched to
VCC and High when VOUT is internally switched to battery.
- SAL, RST, PFO, and BLD are Open Drain.
Table 2. Signal Names
- Normal Mode: Low when VOUT is internally switched to
VCC and High when VOUT is internally switched to battery.
- SAL, RST, PFO, and BLD are Open Drain.
- VREF only for STM1403A; VTPU for STM1403B/C.
Figure 3. QFN16 Connections Note: See PIN DESCRIPTIONS, page 9 of the full datasheet for details.
- Normal Mode: Low when VOUT is internally switched to VCC and High when VOUT is internally switched to battery.
- SAL, RST, PFO, and BLD are Open Drain.
- VREF only for STM1403A; VTPU for STM1403B/C.
Figure 4. Block Diagram Note: 1. BAT54J (from STMicroelectronics) recommended.
- Required for battery-reverse charging protection.
REF only for STM1403; VTPU for STM1403B/C.
There are four (4) high-impedance physical tamper detect input pins, 2 normally set to High (NH) and 2 normally set to Low (NL). Each input is designed with a glitch immunity. These inputs can be connected externally to several types of actua- tor devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its state to change will trigger the security alarm (SAL ) and drive it to active-low. Once the tamper condition no longer exists, the SAL will return to its normal High state. TP 1 and TP3 are set Normally to High (NH). They are connected externally through a closed switch or a high-impedance resistor to V OUT (in the case of STM1403A) or VTPU (in the case of STM1403B/ C), A tamper condition will be detected when the input pin is pulled low. If not used, tie the pin to V OUT or VTPU . TP 2 and TP4 are set Normally to Low (NL). They are connected externally through a high-imped- ance resistor or a closed switch to VSS . A tamper condition will be detected when the input pin is pulled high. If not used, tie the pin to V SS . Supply Voltage The internally switched supply voltage, VINT (ei- ther VCC input or VBAT input) is continuously mon- itored. If VINT should exceed the over voltage trip point, VHV (set at 4.2V, typical), or should go below the under voltage trip point, VLV (set at 2.0v, typi- cal). SAL will be driven active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal High state. When no tamper condition exists, SAL is normally High. When a tamper is detected, the SAL is activated (driven low), independent of the part type. VOUT can be driven to one of three states, depending on which variant of STM1403 is being used (see De- vice Options, page 1): ■ ON; ■ High-Z; or ■ Ground (VSS ). Note: The STM1403 must be initially powered above V RST to enable the tamper detection alarms. For example, if the battery is on while VCC = 0V, no alarm condition can be detected until VCC rises above VRST (and trec expires). From this point on, alarms can be detected either on battery or V CC . This is done to avoid false alarms when the device goes from no power to its operational state.
Table 3. Ordering Information Scheme (see Figure 5., page 7 for Marking Information)
Figure 5. Topside Marking Information
REVISION HISTORY
Table 4. Document Revision History
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