STLUX

STLUX STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 STLUX family features list
• 3 Introducing SMED
• 4 System architecture
• 5 Product overview
• 5.1 SMED (state machine event driven): configurable PWM generator
• 5.1.1 SMED coupling schemes
• 5.1.2 Connection matrix
• 5.2 Internal controller (CPU)
• 5.2.1 Architecture and registers
• 5.2.2 Addressing
• 5.2.3 Instruction set
• 5.2.4 Single wire interface module (SWIM)
• 5.2.5 Debug module
• 5.3 Basic peripherals
• 5.3.1 Vectored interrupt controller
• 5.3.2 Timers
• 5.4 Flash program and data E 2PROM
• 5.4.1 Architecture
• 5.4.2 Write protection (WP)
• 5.4.3 Protection of user boot code (UBC)
• 5.4.4 Readout protection (ROP)
• 5.5 Clock controller
• 5.5.1 Internal 16 MHz RC oscillator (HSI)
• 5.5.3 Internal 96 MHz PLL
• 5.5.4 External clock inpu t/crystal oscillator (HSE)

Datasheet sections

• 8.2.1 General purpose I/O GPIO0 register map
• 8.2.2 General purpose I/O GPIO1 register map
• 8.2.3 Miscellaneous registers
• 8.2.4 Flash and E
• 8.2.5 Reset register
• 8.2.6 Clock and clock controller
• 8.2.7 WWDG timers
• 8.2.8 IWDG timers
• 8.2.9 AWU timers
• 8.2.10 Inter-integrated circuit interface (I
• 8.2.11 Universal asynchronous receiver/transmitt er (UART)
• 8.2.12 System timer registers
• 8.2.13 Auxiliary timer registers
• 8.2.14 Digital addressable lighting interface (DALI)
• 8.2.15 DALI noise rejection filter registers
• 8.2.16 Analog-to-digital converter (ADC)
• 8.2.17 State machine event driven (SMEDs)
• 8.2.18 CPU register
• 8.2.19 Global configuration register
• 8.2.20 Interrupt controller
• 8.2.21 SWIM control register
• 9 Interrupt table
• 10 Option bytes
• 10.1 Option byte register overview
• 10.2 Option byte register description

Datasheet sections

• 12.3.11 Analog comparator characteristics
• 12.3.12 DAC characteristics
• 12.4 EMC characteristics
• 12.4.1 Electrostatic discharge (ESD)
• 12.4.2 Static latch-up
• 13 Thermal characteristics
• 14 Package information
• 14.1 TSSOP38 package information
• 14.2 VFQFPN32 package information
• 14.3 TSSOP28 package information
• 15 STLUX development environment
• 16 Order codes
• 17 Revision history

Features

 Up to 6 programmable PWM generators (SMEDs - “State Machine Event Driven”) – 10 ns event detection and reaction – Max.1.3 ns PWM resolution – Single, coupled and two coupled operational modes – Up to 3 internal/external events per SMED  DALI (digital addressable lighting interface) – Interrupt driven hardware encoder – Bus frequency: 1.2, 2.4 or 4.8 kHz – IEC 60929 and IEC 62386 compliant plus 24-bit frame extension – Configurable noise rejection filter – Reverse polarity on Tx/Rx lines  4 analog comparators – 4 internal 4-bit references – 1 external reference – Less than 50 ns propagation time – Continuous comparison cycle  ADCs (up to 8 channels) – 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent – Sequencer functionality – Input impedance: 1 M  – Configurable gain value: x1 and x4  Integrated microcontroller – Advanced STM8 ® core with Harvard architecture and 3-stage pipeline –M a x . fCPU: 16 MHz – Multiple low power modes  Memories – Flash and E 2PROM with read while write (RWW) and error correction code (ECC) – Program memory: 32 Kbytes Flash; data retention 15 years at 85 °C after 10 kcycles at 25 °C – Data memory: 1 Kbyte true data E 2PROM; data retention:15 years at 85 °C after 100 kcycles at 85 °C – RAM: 2 Kbytes  Clock management – Internal 96 MHz PLL – Low power oscillator circuit for external crystal resonator or direct clock input – Internal, user-trimmable 16 MHz RC and low power 153.6 kHz RC oscillators – Clock security system with clock monitor  Basic peripherals – System and auxiliary timers – IWDG/WWDG watchdog, AWU, ITC  I/O – GPIO with highly robust design, immune against current injection – Fast digital input DIGIN, with configurable pull-up  Communication interfaces – UART asynchronous with SW flow control and boot loader support 2C master/slave fast-slow speed rate  Operating temperature: -40 °C up to 105 °C Table 1. Device summary

12.3.9 I

Table 24. I

Table 72. Supply base current consumption at V

1 Description

The STLUX™ family of controllers is a part of the STMicroelectronics® digital devices tailored for lighting and power conversion applications. The STLUX controllers have been successfully integrated in a wide range of architectures and applications, starting from simple buck converters for driving multiple LED strings, boost for power factor corrections, half-bridge resonant converters for high power dimmable LED strings and up to full bridge controllers for HID lamp ballasts.

2 STLUX family features list

Table 2. STLUX features list

1. DIGIN2 - DIGIN3 are connected to the same pin.
2. DIGIN0-DIGIN1 are connected on the same pin; DIGIN2-DIGIN 3 are connected to the same pin; DIGIN4 - DIGIN5 are
3. CPP0, CPP1 and CPM3 are connected on the same pin; CPP2 and CPP3 are connected to the same pin.

3 Introducing SMED

The heart of the STLUX family is the SMED (state machine event driven) technology which allows the device to pilot six independently configurable PWM clocks with a maximum resolution of 1.3 ns. A SMED is a powerful autonomous state machine, which is programmed to react to both external and internal events and may evolve without any software intervention. The SMED reaction time can be as low as 10.4 ns, giving the STLUX the ability of operating in time critical applications. The SMED offers superior performance when compared to traditional, timer based, PWM generators. Each SMED is configured via the STLUX internal microcontroller. The integrated controller extends the STLUX reliability and guarantees more than 15 years of both operating lifetime and memory data retention for program and data memory after cycling. A set of dedicated peripherals complete the STLUX:  4 analog comparators with configurable references and 50 ns max. propagation delay. It is ideal to implement zero current detection algorithms or detect current peaks.  10-bit ADC with configurable op amp and 8-channel sequencer.  DALI: hardware interface that provides full IEC 60929 and IEC 62386 slave interface.  96 MHz PLL for high output signal resolution. Documentation This datasheet contains the description of features, pinout, pin assignment, electrical characteristics, mechanical data and ordering information.  For information on programming, erasing and protection of the internal Flash memory, please refer to the STM8S reference in the programming manual “How to program STM8S and STM8A Flash program memory and data EEPROM” (PM0051).  For information on the debug and SWIM (single wire interface module) refer to the “STM8 SWIM communication protocol and debug module” user manual (UM0470).  For information on the STM8 core, please refer to the “STM8 CPU programming manual” (PM0044).  For information on the SMED configurator please refer to the “STLUX™ SMED configurator 1.0" user manual (UM1760).  For information on the STLUX385A peripheral library please refer to the “Description of STLUX385A peripheral library” user manual (UM1753).  For information on the STLUX385A examples kit please refer to the “Description of STLUX385A examples kit” user manual (UM1763).

4 System architecture

Figure 1. STLUX internal design configure, for every state, which system events will trigger a transaction to a new state. is required since the SMED automatically reacts to system events. the PWM maximum resolution is 1.3 ns. each other or they can be grouped together to form a more powerful state machine. been implemented in the STLUX architecture.

Figure 2. Internal block diagram

1. The number of channels depends on the specific STLUX device.

5 Product overview

Section 5.1 describes the features implemented in the product device.

5.1 SMED (state machine even t driven): configurable PWM

The SMED is an advanced programmable PWM generator signal. The SMED (state machine event driven) is a state machine device controllable by both external events (primary I/O signals) and internal events (counter timers), which generates an output signal (PWM) depending on the evolution of the internal state machine. The PWM signal generated by the SMED is therefore shaped by external events and not only by a simple timer. This mechanism allows to generate controlled high frequency PWM signals. The SMED is also autonomous: once it has been configured by the STLUX internal controller, the SMED can operate without any software interaction. The STLUX family provides 6 SMED units. Multiple SMEDs can operate independently from each other or they can be grouped together to form a more powerful state machine. The main features of a SMED are described here below:  Configurable state machine generating a PWM signal  More than 10.4 ns PWM native resolution  Up to 1.3 ns PWM resolution when using SMED dithering  6 states available in each SMED: IDLE, S0, S1, S2, S3 plus a special HOLD state  Transactions triggered by synchronous and asynchronous external events or an internal timer  Each transaction can generate an interrupt  Fifteen registers available to configure the state machine behavior  Four 16-bit configurable time registers, one for each running state (T0, T1, T2, T3)  Internal resources accessible through the processor interface  Eight interrupt request lines

5.1.1 SMED coupling schemes

The SMED coupling extends the capability of the single SMED, preserving the independence of each “Finite State Machine” (FSM) programmed state evolution. The coupling scheme allows the SMED pulse signals to be interleaved on their own PWM or on a merged single PWM output. The STLUX supports the following coupled configuration schemes:  Single SMED configuration  Synchronous coupled SMEDs  Asynchronous coupled SMEDs  Synchronous two coupled SMEDs  Asynchronous two coupled SMEDs  External controlled SMED

SMDx_GLBCONF and SMDx_DRVOUT bit fields of MSC_SMEDCFGxy registers. An outline of the SMED subsystem is shown in Figure 3. Figure 3. Coupled SMED overview

1. The PWM5 output pin is not present on the STLUX325A.
2. The PWM4 and PWM5 output pins are not present on the STLUX285A.

5.1.2 Connection matrix

signals, SW events, and three PWM internal feedback signals as shown in Figure 4.

Figure 4. SMED subsystem overview

Figure 5. STLUX285A SMED subsystem overview one of possible four connection matrix signals for each SMED input event In_Sig (Y).

Note: Each SMED input has independent connection matrix selection signals. Table 3. Connection matrix interconnection

0 CP0 DIG0 DIG2 DIG5

1 CP1 DIG0 DIG3 CP3

2 CP2 DIG1 DIG4 SW0

0 CP1 DIG1 DIG3 DIG0

1 CP2 DIG1 DIG4 CP3

2 CP0 DIG2 DIG5 SW1

0 CP2 DIG2 DIG4 DIG1

1 CP0 DIG2 DIG5 PWM0

2 CP1 DIG3 DIG0 SW2

0 CP0 DIG3 DIG5 DIG2

1 CP1 DIG3 DIG0 PWM1

2 CP2 DIG4 DIG1 SW3

0 CP1 DIG4 DIG0 DIG3

1 CP2 DIG4 DIG1 PWM5

2 CP0 DIG5 DIG2 SW4

0 CP2 DIG5 DIG1 DIG4

1 CP0 DIG5 DIG2 CP3

2 CP1 DIG0 DIG3 SW5

5.2 Internal controller (CPU)

The STLUX family integrates a programmable STM8 controller acting as a device supervisor. The STM8 is a modern CISC core and has been designed for code efficiency and performance. It contains 21 internal registers (six of them directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

5.2.1 Architecture and registers

 Harvard architecture with 3-stage pipeline  32-bit wide program memory bus with single cycle fetching for most instructions  X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations  8-bit accumulator  24-bit program counter with 16-Mbyte linear memory space  16-bit stack pointer with access to a 64-Kbyte stack  8-bit condition code register with seven condition flags updated with the results of last executed instruction

5.2.2 Addressing

 20 addressing modes  Indexed indirect addressing mode for lookup tables located in the entire address space  Stack pointer relative addressing mode for efficient implementation of local variables and parameter passing

5.2.3 Instruction set

 80 instructions with 2-byte average instruction size  Standard data movement and logic/arithmetic functions  8-bit by 8-bit multiplication  16-bit by 8-bit and 16-bit by 16-bit division  Bit manipulation  Data transfer between the stack and accumulator (push/pop) with direct stack access  Data transfer using the X and Y registers or direct memory-to-memory transfers

5.2.4 Single wire interface module (SWIM)

The single wire interface module (SWIM), together with the integrated debug module (DM), permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated in all device operation modes and can be connected to a running device (hot plugging).The maximum data transmission speed is 145 byte/ms. The SWIM pin is a multifunction signal. For further details refer to Table 8: Port P2 I/O multiplexing signal in Section 7.4 on page 39.

5.2.5 Debug module

The non-intrusive debugging module is fully controllable by the external target emulator. Besides memory and peripheral operation, the CPU operation can also be monitored in real-time by means of shadow registers.  R/W of RAM and peripheral registers in real-time  R/W for all resources when the application is stopped  Breakpoints on all program memory instructions (software breakpoints), except for the interrupt vector table  Two advanced breakpoints and 23 predefined breakpoint configurations

5.3 Basic peripherals

Section 5.3.1 and Section 5.3.2 describe the basic peripherals accessed by the internal CPU controller.

5.3.1 Vectored interrupt controller

 Nested interrupts with three software priority levels  21 interrupt vectors with hardware priority  Two vectors for 12 external maskable or un-maskable interrupt request lines  Trap and reset interrupts

5.3.2 Timers

The STLUX family provides several timers which are used by software and do not interact directly with the SMED and the PWM generation. System timers The system timer consists of a 16-bit autoreload counter driven by a programmable prescaled clock and operating in one shoot or free running operating mode. The timer is used to provide the IC time base system clock, with an interrupt generation on timer overflow events. Auxiliary timer The auxiliary timer is a light timer with elementary functionality. The time base frequency is provided by the CCO clock logic (configurable with a different source clock and prescale division factors), while the interrupt functionality is supplied by an interrupt edge detection logic similarly to the solution adopted for the Port P0/P2. The timer has the following main features:  Free running mode  Up counter  Timer prescaler 8-bit  Interrupt timer capability: – Vectored interrupt – Interrupt IRQ/NM I or polling mode  Timer pulse configurable as a clock output signal via the CCO primary pin

Thanks to the great configurability of the CCO frequency, the timer can cover a wide range of interval time to fit better the target application requirements. Auto-wakeup timer The AWU timer is used to cyclically wake-up the IC device from the active halt state. The AWU frequency time base fAWU can be selected between the following clock sources: LSI (153.6 kHz) and the external clock HSE scaled down to 128-kHz clock. By default the fAWU clock is provided by the LSI internal source clock. Watchdog timers The watchdog system is based on two independent timers providing a high level of robustness to the applications. The watchdog timer activity is controlled by the application program or by suitable option bytes. Once the watchdog is activated, it cannot be disabled by the user program without going through reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which causes the application program to break the normal operating sequence. The window function can be used to adjust the watchdog intervention period in order to match the application timing perfectly. The application software must refresh the counter before timeout and during a limited time window. If the counter is refreshed outside this time window, a reset is issued. Independent watchdog timer The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures. It is clocked by the 153.6 kHz LSI internal RC clock source. By properly setting the hardware watchdog feature associated option bits, the watchdog is automatically enabled at power- on, and generates a reset unless the key register is written by software before the counter reaches the end of the count.

5.4 Flash program and data E 2PROM

Embedded Flash and E2PROM with the memory ECC code correction and protection mechanism preventing embedded program hacking.  32 Kbyte of single voltage program Flash memory  1 Kbyte true (not emulated) data E2PROM  Read while write: writing in the data memory is possible while executing code program memory  The device setup is stored in a user option area in the non-volatile memory.

5.4.1 Architecture

Figure 6. Flash and E2PROM internal memory organizations

5.4.2 Write protection (WP)

5.4.3 Protection of us er boot code (UBC)

in increments of 512 bytes by programming the UBC and nUBC option bytes. protected so to prevent unwanted modification.

5.4.4 Readout protection (ROP)

The STLUX family provides a readout protection of the code and data memory which can be activated by an option byte setting. The readout protection prevents reading and writing program memory, data memory and option bytes via the debug module and SWIM interface. This protection is active in all device operation modes. Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data memory contents.

5.5 Clock controller

The clock controller distributes the system clock provided by different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. The main clock controller features are:  Clock sources  Internal 16-MHz and 153.6-kHz RC oscillators  External source clock: – Crystal/resonator oscillator – External clock input  Internal PLL at 96 MHz (not used as the f MASTER source clock)  Reset: after the reset the microcontroller restarts by default with the HSI internal clock scaled at 2 MHz (16 MHz/8). The clock source and speed can be changed by the application program as soon as the code execution starts.  Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.  Clock management: to reduce power consumption, the clock controller can stop the clock to the core or individual peripherals.  Wakeup: in case the device wakes up from low power modes, the internal RC oscillator (16 MHz/8) is used for a quick startup. After a stabilization time, the device brings back the clock source that was selected before Halt mode was entered.  Clock security system (CSS): the CSS permits monitoring of external clock sources and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.  Configurable main clock output (CCO): this feature permits to output an internal clock source signal for application usage.

5.5.1 Internal 16 MH z RC oscillator (HSI)

The high speed internal (HSI) clock is the default master clock line, generated by an internal RC oscillator and with nominal frequency of 16 MHz. It has the following major features:  RC architecture  Glitch-free oscillation  3-bit user calibration circuit.

5.5.2 Internal 153.6 kH z RC oscillator (LSI) The low speed internal (LSI) clock is a low speed clock line provided by an internal RC circuit. It drives both the independent watchdog (IWDG) circuit and the auto-wakeup unit (AWU). It can also be used as a low power clock line for the master clock fMASTER.

5.5.3 Internal 96 MHz PLL

The PLL provides a high frequency 96 MHz clock used to generate high frequency and accurate PWM waveforms. The input reference clock must be 16 MHz and may be sourced either by the internal HSI signal or by the external HSE auxiliary input crystal oscillator line. The internal PLL prescaled clock cannot be selected as fMASTER. Note: When the application requires a PWM signal with a custom defined long term stability, it is suggested to use an external clock source connected to the HSE auxiliary clock line as a PLL input reference clock. In this case, the external clock source accuracy determines the PWM output stability.

5.5.4 External clock input /crystal oscillator (HSE)

The high speed external clock (HSE) allows the connection of an external clock generated, for example, by a highly accurate crystal oscillator. The HSE is interconnected with the fMASTER clock line and to several peripherals. It allows users to provide a custom clock characterized by a high level of precision and stability to meet the application requirements. The HSE supports two possible external clock sources with a maximum of 24 MHz:  Crystal/ceramic resonator interconnected with the HseOscin/HseOscout signals  Direct drive clock interconnected with the HseOscin signal The HseOscin and HseOscout signals are multifunction pins configurable through the I/O multiplex mechanism; for further information refer to Section 7: I/O multifunction signal configuration on page 35. Note: When the HSE is configured as the f MASTER source clock, the HSE input frequency cannot be higher than 16 MHz. When the HSE is the PLL input reference clock, then the HSE input frequency must be equal to 16 MHz. If the HSE is the reference for the SMED or the ADC logic, the input frequency can be configured up to 24 MHz.

5.6 Power management

For efficient power management, the application can be put in one of four different low power modes. Users can configure each mode to obtain the best compromise between the lowest power consumption, the fastest startup time and available wakeup sources.  Wait mode: in this mode, the CPU is stopped, but peripherals are kept running. The wakeup is triggered by an internal or external interrupt or reset.  Active halt mode with regulator on: in this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto- wakeup unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in the active halt mode with the regulator off, but the

wakeup time is faster. The wakeup is triggered by the internal AWU interrupt, external interrupt or reset.  Active halt mode with regulator off: this mode is the same as active halt with the regulator on, except that the main voltage regulator is powered off, so the wakeup time is slower.  Halt mode: in this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, while the main voltage regulator is switched in power- off. Wakeup is triggered by an external event or reset. In all modes the CPU and peripherals remain permanently powered on, the system clock is applied only to selected modules. The RAM content is preserved and the brownout reset circuit remains enabled.

5.7 Communication interfaces

5.7.1 Digital addressable lighting interface (DALI)

The DALI (digital addressable lighting interface), standardized as the IEC 62386, is the new interface for lighting control solutions defined by the lighting industry. The DALI protocol is generally implemented in a DALI communication module (DCM): a serial communication circuit designed for controllable electronic ballasts. “Ballast” is a device or circuit used to provide the required starting voltage and operating current for the LED, fluorescent, mercury or other electronic-discharge lamps. The STLUX DALI driver has the following characteristics:  Speed line:1.2, 2.4 and 4.8 kHz transmission rate ± 10%  Forward payload: 16, 17, 18 and 24-bit message length  Backward payload: 8-bit message length.  Bidirectional communications  Monitor receiver line timeout 500 ms ± 10%  Polarity insensitive on DALI_rx, DALI_tx signal line  Interoperability with different message length  Maskable interrupt request line  DALI peripheral clock has slowed down to 153.6 kHz in low speed operating mode  Improved DALI noise rejection filter on DALI_rx input line (see Section : DALI noise rejection filter). DALI noise rejection filter The STLUX DALI interface includes a noise rejection filter interconnected on the RX channel capable to remove any bounce, glitch or spurious pulse from the RX line. The filter can be configured via three registers:  MSC_DALICKSEL: selects the source clock of filter timing  MSC_DALICKDIV: configures the clock prescaler value  MSC_DALICONF: configures the filter count and operating mode.

5.7.2 Universal asynchronous receiver/transmitter (UART)

UART is the asynchronous receiver/transmitter communication interface.  SW flow control operating mode  Full duplex, asynchronous communications  High precision baud rate generator system – Common programmable transmit and receive baud rates up to f MASTER/16  Programmable data word length (8 or 9-bit)  Configurable stop bit - support for 1 or 2 stop bit  Configurable parity control  Separate enable bits for transmitter and receiver  Interrupt sources: – Transmit events – Receive events – Error detection flags  2 interrupt vectors: – Transmitter interrupt – Receiver interrupt  Reduced power consumption mode  Wakeup from mute mode (by idle line detection or address mark detection)  2 receiver wakeup modes: – Address bit (MSB) – Idle line.

5.7.3 Inter-integrated circuit interface (I 2C)

The I2C (inter-integrated circuit) bus interface serves as an interface between the microcontroller and the serial I2C bus. It provides a multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast speed modes.  Parallel-bus/I2C protocol converter  Multimaster capability: the same interface can act as master or slave  I2C master features: – Clock generation – Start and stop generation  I 2C slave features: – Programmable I 2C address detection – Stop bit detection  Generation and detection of 7-bit/10-bit addressing and general call  Supports different communication speeds: – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz)

 Status flags: – Transmitter/receiver mode flag – End of byte transmission flag 2C busy flag  Error flags: – Arbitration lost condition for master mode – Acknowledgment failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/underrun if clock stretching is disabled  Interrupt sources: – Communication interrupt – Error condition interrupt – Wakeup from Halt interrupt  Wakeup capability: – MCU wakes up from low power mode on address detection in slave mode.

5.8 Analog-to-digital converter (ADC)

The STLUX family includes a 10-bit successive approximation ADC with 8 multiplexed input channels. The analog input signal can be amplified before conversion by a selectable gain of 1 or 4(a) times. The analog-to-digital converter can operate either in single or in continuous/circular modes. The ADC unit has the following main features:  8/6 ADC input channel(b)  10-bit resolution  Single and continuous conversion mode  Independent or fixed channel gain value x1 or x4 to extend dynamic range and resolution to 12-bit equivalent(a)  Interrupt events: – EOC interrupt asserted on end of conversion cycle – EOS interrupt asserted on end of conversion sequences – SEQ_FULL_EN interrupt assert on sequencer buffer full  ADC input voltage range dependent on selected gain value (b)  Selectable conversion data alignment  Individual registers for up to 8 successive conversions. a. The gain x4 is available only on the STLUX385A. b. The number of ADC input channels de pends of the STLUX device part number.

5.9 Analog comparators

The STLUX devices family includes four independent fast analog comparator units (COMP3-0). Each comparator has an internal reference voltage. The COMP3 can be also configured to use an external reference voltage connected to the CPM3 input pin. Each comparator reference voltage is generated by a dedicated internal-only 4-bit DAC unit. The main characteristics of the analog comparator unit (ACU) are the following:  Each comparator has an internally configurable reference  Internal reference voltages configurable in 16 steps with the 83 mV voltage grain from 0 V (GND) to 1.24 V (voltage reference)  Two stage comparator architecture is used to reach a high gain  Comparator output stage value accessible from processor interface  Continuous fast cycle comparison time.

6 Pinout and pin description

6.1 Pinout

Figure 7. TSSOP38 pinout of STLUX385A and STLUX383A

6.2 Pin description

Table 4. Pin description

7 I DIGIN[3] Digital input 3 - - -

1. The DIGIN3 and DGIN2 are connected together on the STLUX325A, DIGIN [3_2] pin.
2. Available only on the STUX325A.
3. Not available on the STUX285A.

Table 4. Pin description (continued)

Pinout and pin description STLUX

6.3 Input/output specifications

The STLUX family includes three different I/O types:  Normal I/Os configurable either at 2 or 10 MHz maximum frequency  Fast I/O operating up to 12 MHz.  High speed I/O operating up to 32 MHz The STLUX I/Os are designed to withstand current injection. For a negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA; further details are available in Section 12: Electrical characteristics on page 82.

7 I/O multifunction signal configuration

four different configurable ports: P0, P1, P2 and P3.

7.1 Multifunction configuration policy

and the multifunction pin functionality is configured through the miscellaneous registers. The warm configuration is volatile, thus not maintained after a device reset.

7.2 Port P0 I/O multifun ction configuration signal

The Port P0 multiplexes several input/output functionalities, increasing the device flexibility.

7.2.1 Alternate function P0 configuration signals

Table 5. Multifunction configuration registers

1 Cold AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2

respectively control the bits [5, 4], [3, 2] and [1, 0] of the Port P0.

7.2.2 Port P0 diagnostic signals

P [2:0] when the external comparator reference voltage is programmed on the Port P0 [1, 0]. The Port 0 I/O signal availability depends on the STLUX device. Table 6. P0 internal multiplexing signals

1. The Sel_p054, Sel_p032, Sel_p010 are register fields for both registers MSC_IOMXP0 and

related I/O port speed has to be configured at 10 MHz by programming the GPIO0 internal peripheral.

1. Available only on the STLUX385A and STLUX383A.

7.2.3 Port P0 I/O functi onal multiplexing signal

Figure 10 shows an outline view of the Port P0 multifunction multiplexing scheme. Figure 10. Port P0 I/O functional multiplexing scheme Note: Where the “A/F(s) in” and “A/F(s) out” signals are defined in Section 6.2 on page 32. Verify pin availability in Table 4: Pin description on page 32.  P0_ODR [1:0] bits must be keep clear. AFR_IOMXP2 [7] register bits - for further details refer to Section 7.4.  Port P0 [6] signal is controlled by P0_ODR [6] and P0_IDR [6] GPIO0 registers.  P0_ODR [1:0] bits must be keep clear.

7.2.4 P0 interrupt capability

on the port P0:[1:0] on STLUX285A. interrupt), AHalt (active Halt) and Halt power saving state.

7.2.5 P0 programmable pull-up and speed feature

the GPIO0 internal registers.

7.3 Port P1 I/O multifun ction configuration signal

 Cold configuration: AFR_IOMXP1 option byte register (refer to Section 10 on page 60). After reset the P1 signals are configured in line with AFR_IOMXP1 contents. reset the P1 signals are configured as PWM output lines. from the port P0s, the pins are configured as PWM output signals by default after reset. availability in Table 4 on page 32). Table 7. Port P1 I/O multiplexing signal(1)

1. The Sel_p15…Sel_p10 are common register fields of both registers MSC_IOMXP1 and AFR_IOMXP1.

In cold configuration the P1x are configured as defined by the AFR_IOMXP1 option byte. The PWM default polarity level is configured by the register option byte GENCFG. Verify pin availability in Table 4 on page 32.

7.3.1 Port P1 I/O multiplexing signal

Figure 11 shows an outline view of the port P1 signal multiplexing scheme. Figure 11. Port P1 I/O multiplexing scheme are configured as GPIO out or PWM signals. Verify pin availability in device pin Table 4 on page 32.

7.3.2 P1 programmable pull-up feature

7.4 Port P2 I/O multifun ction configuration signal

reset the P2 signals are configured as DIGIN input lines with the pull-up enabled. AFR_IOMXP2 [7] and MSC_IOMXP2 [7].

be prevented by SW configuration. the internal pull-up functionality is controlled by the MSC_INPP2AUX1 register. The GPIO0 [6] signal is selected when both Sel_SWIM = '0' and CFG_GCR [0] = '1'. SWIM signal function is selected when the CFG_GCR [0] = '0'. After reset by default the P2 [0] is configured as the DIGIN [0] signal. Verify pinout availability in Table 4: Pin description on page 32.

7.4.1 P2 interrupt capability

interrupt), AHalt (active Halt) and Halt power saving state.

7.4.2 P2 programmable pull-up feature

Table 8. Port P2 I/O multiplexing signal

7.5 Multifunction Port configuration registers

Verify pinout availability in Table 4: Pin description on page 32. during register write operations. Table 9. MSC_IOMXP0 (Port P1 I/O MUX control register)

1. Not available on the STLUX325A and STLUX285A.

Verify pinout availability in Table 4: Pin description on page 32. Table 10. MSC_IOMXP1 (Port P1 I/O MUX control register)

1. Not available on the STLUX285A; these bits are set to 1 after reset, must be cleared by SW during the IC

device initialization phase and during register write operations.

1. Not available on the STLUX325A; these bits are set to 1 after reset, must be cleared by SW during the IC

device initialization phase and during register write operations.

during register write operations. Check device feature availability. during register write operations. field of the register CFG_GCR is set. 0: SWIM pin is configured with GPIO0 [6] signal. 1: SWIM functionality is preserved. Table 11. MSC_IOMXP2 (Port P2 I/O MUX control register)

during register write operations. Note: The MSC_IOMXP2 and MSC_INPP2AUX1 are addressable in indirect mode.  DIGIN10 is controlled by register field NPP2_PULCTR[1:0].  DIGIN32 is controlled by register field INPP2_PULCTR[3:2].  DIGIN54 is controlled by register field INPP2_PULCTR[5:4]. Table 12. MSC_INPP2AUX1 (INPP aux register)

8 Memory and register map

8.1 Memory map overview

Table 13. Internal memory map

8.2 Register map

Section 8.2.1 shows the STLUX memory map.

8.2.1 General purpose I/O GPIO0 register map

8.2.2 General purpose I/O GPIO1 register map

Table 14. General purpose I/O GPIO0 register map Table 15. General purpose I/O GPIO1 register map

8.2.3 Miscellaneous registers

Table 16. Miscellaneous direct register address mode

1. Address not available for the STLUX285A and STLUX325A.

Table 17. Miscellaneous indirect register address mode

1. Register not available for the STLUX285A.

Table 16. Miscellaneous direct register address mode (continued)

8.2.4 Flash and E 2PROM non-volatile memories

8.2.5 Reset register

Table 18. Non-volatile memory register map 0x00.5062 FLASH_PUKR Write memory protection removal key reg. 0x00.5071 FLASH_WAIT Time access wait-state reg. Table 19. RST_SR register map

8.2.6 Clock and clock controller

Table 20. Clock and clock controller register map

8.2.7 WWDG timers

8.2.8 IWDG timers

8.2.9 AWU timers

Table 21. WWDG timer register map Table 22. IWDG timer register map Table 23. AWU timer register map

8.2.10 Inter-integrat ed circuit interface (I2C)

8.2.11 Universal asynchronous receiver/transmitter (UART)

Table 24. I2C register map Table 25. UART register map

8.2.12 System timer registers

8.2.13 Auxiliary timer registers

8.2.14 Digital addressable lighting interface (DALI)

Table 26. System timer register map Table 27. Auxiliary timer register map Table 28. DALI register map

8.2.15 DALI noise reject ion filter registers

8.2.16 Analog-to-digital converter (ADC)

Table 29. DALI filter register map Table 30. ADC register map and reset value

8.2.17 State machine event driven (SMEDs)

where <n> is the SMED instance number 0 - 5. Table 31. SMED register map

8.2.18 CPU register

Note: Register space access ible in debug mode only.

8.2.19 Global configuration register

Table 31. SMED register map (continued) Table 32. CPU register map Table 33. CFG_GCR register map

8.2.20 Interrupt controller

8.2.21 SWIM control register

Table 34. Interrupt software priority register map Table 35. SWIM register map

9 Interrupt table

Table 36 shows the STLUX internal controller's interrupt vector. Table 36. Interrupt vector exception table

0 NMI NMI (not maskable interrupt) Yes (1) Yes(1) 8008h

1 AWU Auto-wakeup from Halt Yes 800Ch

2 CKC Clock controller 8010h

3 PO GPIO0 [5:0] external interrupts Yes (1), (2) Yes((1), (2) 8014h

4 AUXTIM Auxiliary timer 8018h

5 P2 DIGIN [5:0] external interrupts Yes (1), (2) Yes(1), (2) 801Ch

6 SMED0 SMED-0 interrupt 8020h

7 SMED1 SMED-1 control logic 8024h

10 RFU (3) Reserved for future use 8030h

11 RFU (3) Reserved for future use 8034h

12 RFU (3) Reserved for future use 8038h

13 RFU (3) Reserved for future use 803Ch

14 RFU (3) Reserved for future use 8040h

15 SMED2 SMED-2 control logic 8044h

16 SMED3 SMED-3 control logic 8048h

17 UART Tx complete 804Ch

18 UART Receive register DATA FULL Indirect

19 I 2CI 2C interrupt Indirect (4) Yes 8054h

20 RFU (3) Reserved for future use 8058h

21 RFU (3) Reserved for future use 805Ch

22 ADC End of conversion 8060h

23 SYS-TMR Update/ overflow 8064h

24 FLASH EOP/WR_PG_DIS 8068h

25 DALI DALI interrupt line Indirect (4) Indirect(4) 806Ch

26 SMED4 SMED-4 control logic 8070h

27 SMED5 SMED-5 control logic 8074h

28 RFU (3) Reserved future use 8078h

29 RFU (3) Reserved future use 807Ch

1. The P [2, 0] [x] may be configured to generate a NMI requests.
2. The P [2, 0] [x] may be configured to generate an IRQ requests.
3. All RFU and unused interrupts should be initialized with 'IRET' for robust programming.
4. The P0 [x] may be configured to generate an IRQ and NMI request.

Table 36. Interrupt vector exception table (continued)

10 Option bytes

The user option byte is a memory E²PROM area allowing users to customize the IC device major functionalities:  ROP: readout protection control field  UBC: user boot code protection  PWM: configurable reset output value  WDG: internal watchdog HW configuration  AFR: alternate multifunction signals configuration  CKC: clock controller functionalities (PLL, HSE enable, AWU clock selection, etc.)  HSE: clock stabilization counter  WAIT: Flash and E²PROM wait state access time has to be configured with value 0x00  BOOT: configurable internal boot sources  BL: bootloader control sequences Except the ROP byte all the other option bytes are stored twice in a regular (OPT) and complemented format (NOPT) for redundancy. The option byte can be programmed in ICP mode through the SWIM interface or in IAP mode by the application with the exception of the ROP byte that can be only configured via the SWIM interface. For further information about Flash programming refer to the programming manual “How to program STM8S and STM8A Flash program memory and data EEPROM” (PM0051). For information on SWIM programming procedures refer to the “STM8 SWIM communication protocol and debug module” user manual (UM0470).

10.1 Option byte register overview

Table 37. Option byte register overview - STLUX385A

with the target application requirements. The predefined initialized bit-values (1 or 0) must be preserved during memory writing. An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence. Table 37. Option byte register overview - STLUX385A (continued)

Table 38. Option byte register overview - STLUX383A

with the target application requirements. The predefined initialized bit-values (1 or 0) must be preserved during memory writing. An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence. Table 38. Option byte register overview - STLUX383A (continued)

Table 39. Option byte register overview - STLUX325A

with the target application requirements. The predefined initialized bit-values (1 or 0) must be preserved during memory writing. An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence. Table 39. Option byte register overview - STLUX325A (continued)

Table 40. Option byte register overview - STLUX285A

with the target application requirements. The predefined initialized bit-values (1 or 0) must be preserved during memory writing. An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence. Table 40. Option byte register overview - STLUX285A (continued)

10.2 Option byte register description

The option byte registers are mapped inside the E²PROM data region. interface) is forbidden, whatever the write protection settings are. Table 41. ROP (memory readout protection register) Table 42. UBC (UBC user boot code register)

nUBC: not (UBC) EMC byte protection. AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2 (cold configuration). COMP1_2 enables the complete backward compatibility with the STLUX385 IC device. 1: PWM [n] output high level. then before the NRST is released it assumes its proper initial values. The Rst_PWM5 is not available only on the STLUX325A and must be kept 0. Table 43. nUBC (UBC user boot code register protection) Table 44. GENCFG (general configuration register)

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.

nGENCFG: not (GENCFG) EMC byte protection. is active 1: reset generated on Halt if WWDG is active. 0: independent watchdog activation by SW 1: independent watchdog activation by HW. 1: LSI cock is enabled for CPU. RFU reserved; must be kept 0 during register writing for future compatibility. RFU reserved; must be kept 1 during register writing for future compatibility. RFU reserved; must be kept 0 during register writing for future compatibility. Table 45. nGENCFG (general configuration register protection) Table 46. MISCUOPT (miscellaneous configuration register)

nMISCUOPT: not (MISCUOPT) EMC byte protection. 11: 4 MHz to 128 kHz prescaler. 1: external direct drive clock connected to the HseOscin. 11: reserved encoding value. RFU reserved; must be kept 0 during register writing for future compatibility. Table 47. nMISCUOPT (miscellaneous configuration register protection) Table 48. CLKCTL (CKC configuration register)

nCLKCTL: not (CLKCTL) EMC byte protection. nHSESTAB: not (HSESTAB) EMC byte protection. Table 49. nCLKCTL (CKC configuration register protection) Table 50. HSESTAB (HSE clock stabilization register) Table 51. nHSESTAB (HSE clock stabilization register protection)

RFU reserved; must be kept 0 during register writing for future compatibility. nWAITSTATE: not (WAITSTATE) EMC byte protection. Table 52. WAITSTATE (Flash wait state register) Table 53. nWAITSTATE (Flash wait state register)

RFU reserved; must be kept 0 during register writing for future compatibility. nAFR_IOMXP0: not (AFR_IOMXP0) EMC byte protection. Table 54. AFR_IOMXP0 (alternative Port0 configuration register)

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.

Table 55. nAFR_IOMXP0 (alternative Port0 configuration register protection)

RFU reserved; must be kept 0 during register writing for future product compatibility. nAFR_IOMXP1: not (AFR_IOMXP1) EMC byte protection. Table 56. AFR_IOMXP1 (alternative Port1 configuration register)

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.
2. Available only on the STLUX385A, STLU X383A and STLUX325A, otherwise keep 0.

Table 57. nAFR_IOMXP1 (alternative Port1 configuration register protection)

STLUX285A devices bit 6 must be kept to 1. nAFR_IOMXP2: not (AFR_IOMXP2) EMC byte protection. Table 58. AFR_IOMXP2 (alternative Port2 configuration register)

1. Available only on the STLUX325A, otherwise keep 0.
2. Not available on the STLUX285A, must be kept to 1.

Table 59. nAFR_IOMXP2 (alternative Port2 configuration register protection)

RFU reserved; must be kept 0 during register writing for future compatibility. ignored since the UART port is selected by the register AFR_IOXP0. schemes. This sequence is used when UART i/f position is not specified. i/f configured on P0 (3, 2) 11: boot sequence with UART i/f configured on P0 (5, 4). RFU reserved; must be kept 0 during register writing for future compatibility. nMSC_OPT0: not (MSC_OPT0) EMC byte protection. Table 60. MSC_OPT0 (miscellaneous configuration reg0) Table 61. nMSC_OPT0 (miscellaneous configuration reg0 protection)

0x008000 determine the bootloader SW flow execution sequence. nOPTBL: not (OPTBL) EMC byte protection. Table 62. OPTBL (option byte bootloader) Table 63. nOPTBL (option byte boot loader protection)

11 Device identification

11.1 Unique ID

signature not alterable by user.  Activating the secure boot sequence.

11.2 Device ID

Table 64. Unique ID register overview Table 65. Dev ID register overview

The RFU and nRFU value are reserved and the value may be changed within devices. Note: The mask DVD1 and nDVD1 register with 0x1F when read the Rev_ID [4:0] field. Table 66. Device revision model overview

12.1 Parameter conditions

12.1.1 Minimum and maximum values

the selected temperature range). are indicated according to each table specific notes and are not tested in production.

12.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD and VDDA = 3.3 V.

12.1.3 Typical curves

12.1.4 Typical current consumption

Figure 12. Supply current measurement conditions

12.1.5 Loading capacitors

Figure 13. Pin loading conditions

12.1.6 Pin output voltage

The input voltage measurement on a pin is described in Figure 14. Figure 14. Pin input voltage

12.2 Absolute maximum ratings

affect the device reliability. Table 67. Voltage characteristics

1. All power V DDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
2. I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.

1. V SS and VSSA signals must be interconnected together with a short wire loop.

Table 68. Current characteristics

1. Data based on characterization results, not tested in production.
2. All power V DDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external
3. I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.

1. Negative injection disturbs t he analog performance of the device.
2. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the

characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.

12.3 Operating conditions

Table 70. In addition, a full account must be taken for all physical capacitor characteristics Table 69. Thermal characteristics Table 70. General operating conditions

1. The external power supply can be within range fr om 3 V up to 5.5 V although IC performances are

optimized for a power supply equal to 3.3 V.

1. Internal core power supply voltage.
2. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,
3. To calculate P Dmax (TA), use the formula PDmax = (TJmax - TA)/JA.

12.3.1 VOUT external capacitor

(c) to the VOUT pin. The CVOUT is specified in Section 12.3: Operating conditions. Care should be taken to limit the series inductance to less than 15 nH. Figure 15. External capacitor CVOUT

12.3.2 Supply current characteristics

Table 74 on page 90 and Table Table 75 on page 92. Table 71. Operating conditions at power-up/power-down

1. Guaranteed by design, not tested in production.
2. Power supply ramp must be monotone.

c. ESR is the equivalent series resist ance and ESL is the equivalent inductance.

The total current consumption is given by Equation 1: Equation 1 IDD = IDD(Run2) + IDD(ADC2) + IDD(ACU) + IDD(PLL) + IDD(PWM) where IDD(PWM) = IDD(PWM1) * NPWM More generally, the PWM current consumption has to be individually evaluated for each fSMED clock grouping, using Equation 2. Equation 2 NfSMED where i = fSMED clock group index; Ni = PWM number of the i_th clock group; NfSMED = fSMED clock group number.

Electrical characteristics STLUX IC supply base current consumption Table 72 summarizes the current consumption measured on VDD/VDDA supply pins in relevant operative conditions. Table 72. Supply base current consumption at VDD/VDDA = 3.3/5 V

1. Data based on characterization results not tested in production.
2. “All” means: I2C, UART, DALI, ITC, GPIO0, SysTmr, WWDG and IWDG peripherals active.
3. The peripheral current consumption is supplied by the VCORE voltage (1.8 V).
4. Temperature operating: T A = 25 °C.

Description

Source MHz MHz Enb/Dis mA mA IDD(Run1) Flash HSI 2 2 All 2.3 2.77 Reset exit condition IDD(Run2) Flash HSI 16 16 All 9.4 11.3 IDD(Run3) RAM HSI 16 16 All 4.2 5.1 IDD(Run4) Flash HSE (5) 5. HSE frequency provided by external quartz. 16 16 All 10.0 12.1 V DD/VDDA = 3.3 V 10.6 12.74 V DD/VDDA = 5 V IDD(Run5) RAM HSE (5) 16 16 All 4.6 5.53 V DD/VDDA = 3.3 V 5.2 6.63 V DD/VDDA = 5 V IDD(SLOW1) Flash HSI 16 2 All 3.6 4.33 IDD(SLOW2) RAM HSI 16 2 All 2.9 3.5 IDD(SLOW3) Flash HSE (5) 16 2 All 3.9 4.7 V DD/VDDA = 3.3 V 4.5 5.5 V DD/VDDA = 5 V IDD(SLOW4) Flash HSI 16 0.125 All 2.7 3.3 IDD(SLOW5) Flash HSE (5) 16 0.125 All 3.0 3.7 V DD/VDDA = 3.3 V 3.6 4.4 V DD/VDDA = 5 V IDD(SLOW6) Flash LSI 0.153 0.153 All 1.5 1.9 IDD(WFI1) Flash HSI 16 16 All 2.6 3.2 IDD(WFI2) Flash HSE (5) 16 16 All 3.1 3.8 V DD/VDDA = 3.3 V 3.8 5.6 V DD/VDDA = 5 V

IC low power current consumption Table 73 summarizes the current consumption measured on VDD/VDDA supply pins in power saving conditions. Table 73. Supply low power consumption at VDD/VDDA = 3.3/5 V Source MHz Enable Enable mA mA IDD(AHLT1) Flash HSI 16 Enable Enable 0.23 0.32 AWU clocked by LSI IDD(AHLT2) Flash HSI 16 Enable Disable 0.085 0.12 AWU clocked by LSI IDD(AHLT3) Flash HSE (9), (10) 16 Enable Enable 0.73 0.90 V DD/VDDA = 3.3 V 1.4 1.7 V DD/VDDA = 5 V IDD(AHLT4) Flash HSE (9), (10) 16 Enable Disable 0.65 0.95 V DD/VDDA = 3.3 V 1.2 1.45 V DD/VDDA = 5 V IDD(HLT1) Flash HSI 16 Enable Disable 0.087 0.13 IDD(HLT2) Flash HSE (9), (10) 16 Enable Disable 0.075 0.11 V DD/VDDA = 3.3 V 0.090 0.15 V DD/VDDA = 5 V 1. Data based on characterization results not tested in production. 2. Active halt op. mode: all peripherals except AWU and IWDG are disabled (clock gated). 3. HALT op. mode: all peripheral s are disabled (clock gated). 4. E 2PROM is considered always enabled. 5. .VCORE main DC voltage regulator. 6. Temperature operating: T A= 25 °C. 7. All the analog input signals are connected to GND; the signals of the port P0, P1 and P2 are configured as input with the pull-up enabled. 8. Temperature operating: T A= 105 °C. 9. HSE frequency provided by external quartz. 10. AWU clocked by HSE source clock.

Table 74. Peripheral supply current consumption at VDD/VDDA = 3.3 V

1. Data based on characterization results not tested in production.

• 96 MHz and 6 MHz frequencies require the PLL enabled.
• Current table shows only a subset value of possible SMED frequencies.
• PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.
• 6 MHz frequency requires the PLL enabled.
• Current table shows only a subset value of possible ADC frequencies.

1. ADC configured in circular mode.
2. PWM pins are loaded with a CL (load capacitance) of 50 pF.
3. If enabled all DACs and comparator units are active.
4. Temperature operating: T A = 25 °C.

Table 74. Peripheral supply current consumption at VDD/VDDA = 3.3 V (continued)

Table 75. Peripheral supply current consumption at VDD/VDDA = 5 V

1. Data based on characterization results not tested in production.

• 96 MHz and 6 MHz frequencies require the PLL enabled.
• Current table shows only a subset value of possible SMED frequencies.
• PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.
• 6 MHz frequency requires the PLL enabled.
• Current table shows only a subset value of possible ADC frequencies.

1. ADC configured in circular mode.
2. PWM pins are loaded with a CL (load capacitance) of 50 pF.
3. If enabled all DACs and comparator units are active.

Table 75. Peripheral supply current consumption at VDD/VDDA = 5 V (continued)

12.3.3 External clock sources and timing characteristics

Subject to general operating conditions for VDD and TA. Table 76. Wake-up times

1. Data based on characterization results, not tested in production.
2. Measured from the interrupt event to interrupt vector fetch.

WU(WFI) = 2 x 1/fMASTER + 7 x 1/fCPU.

1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
3. Plus 1 LSI clock depending on synchronization (f

Table 77. HSE user external clock characteristics

1. In case f HSE is configured as a direct clock for the SMED logics the maximum frequency can be 24 MHz.
2. Data based on characterization results, not tested in production.

Figure 20. HSE external clock source (frequency, package, accuracy, etc.). Table 78. HSE crystal/ceramic resonator oscillator

1. In case f HSE is configured as a direct clock for the SMED logic the maximum frequency can be 24 MHz.
2. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load

built-in load capacitors, CL1 and CL2.

1. The oscillator selection can be optimized in terms of supply current using a high quality resonator with
2. t SU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz

with the crystal manufacturer.

Figure 21. HSE oscillator circuit diagram d. Refer to the application crystal specification.

12.3.4 Internal clock source s and timing characteristics

Subject to general operating conditions for VDD and TA. Subject to general operating conditions for VDD and TA. Table 79. HSI RC oscillator

1. Data based on characterization results, not tested in production.
2. Variation referred to f HSI nominal value.

Table 80. LSI RC oscillator

1. Guaranteed by design, not tested in production.

Table 81. PLL internal source clock

1. Data based on characterization results, not tested in production.
2. PLL maximum input frequency 16 MHz.

3.3 V  VDD  5 V

12.3.5 Memory characteristics

General conditions: TA = -40 °C to 105 °C. Table 82. Flash program memory/data E2PROM memory

1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cy cling is performed on 4 bytes even when a write/erase operation

12.3.6 I/O port pin characteristics

input pins should not be left floating. Table 83. Voltage DC characteristics

1. Data based on characterization result, not tested in production.
2. All signals are not 5 V tolerant (input signals can't be exceeded VDDX (VDDX = VDD, VDDA).
3. A high sink selectable by high s peed configuration; the parameter applicable to signals: GPIO0 [5:0]
4. The parameter applicable to signals: GP IO1 [5:0]/PWM [5:0] (product depending).
5. Electrical threshold voltage not yet characterized at -40 ºC.
6. The parameter applicable to the signal: SWIM.
7. The parameter applicable to the signal: DIGIN [0]/CCO_clk.
8. Applicable to any digital inputs.

Table 84. Current DC characteristics

1. Data based on characterization result, not tested in production.
2. A high sink selectable by high speed conf iguration; the parameter applicable to signals: GPIO0 [5:0] (product depending).
3. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending).
4. The parameter applicable to the signal: SWIM.
5. The parameter applicable to the signal: DIGIN [0]/CCO_clk.
6. Applicable to any digital inputs.
7. Maximum value must never be exceeded.
8. Negative injection current on the ADCIN [7:0] signals (produc t depending) have to avoid since impact the ADC conversion

Table 85. Operating frequency characteristics

1. Data based on characterization result, not tested in production.
2. A high sink selectable by high speed configuration; parameter applicable to signals: GPIO0 [5:0] (product depending).
3. The parameter applicable to the signal: SWIM.
4. The parameter applicable to signals: DIGIN [5:1] (product depending).
5. The parameter applicable to signals: GPIO0 [3:2] when configured as HSE_Oscin/Oscout.
6. The parameter applicable to any analog signals: ADCIN [7:0], CPP [3:0] and CPM3 (product depending).
7. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending).
8. The parameter applicable to the signal: DIGIN [0]/CCO_clk.

12.3.7 Typical output level curves

for the three pad family present in the STLUX family. CPM3 and ADCIN [7:0] when available. Figure 22. VOH standard pad at 3.3 V Figure 23. VOL standard pad at 3.3 V

12.3.8 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

12.3.9 I 2C interface characteristics

Table 86. NRST pin characteristics

1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.

Table 87. I2C interface characteristics

1. f MASTER, must be at least 8 MHz to achieve maximum fast I2C speed (400 kHz).
2. Data based on standard I 2C protocol requirement, not tested in production.
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
4. I 2C multifunction signals require the high sink pad configuration and the interconnection of 1 K pull-up
5. 50 pF is the maximum load capacitance value to meet the I 2C std timing specifications.

Table 88. ADC characteristics

1. Frequency generated selecting the PLL source clock.
2. Maximum input analog voltage cannot exceed V DDA.
3. Exceeding the maximum voltage on the ADCIN [7 :0] signals (product depending) for the related

conversion scale must be avoided since the ADC conversion accuracy can be impacted.

1. ADC reference voltage at T A = 25 °C.

Table 89. ADC accuracy characteristics at VDD/VDDA 3.3 V

1. Measured with RAIN < 10 k  (RAIN external series resistance interconnected between the AC signal generator and the
2. Temperature operating: T A = 25 °C.
3. Data based on characterization results, not tested in production.
4. ADC accuracy vs. negative injection current. Injecting negati ve current on any of the analog input pins should be avoided
5. Results in manufacturing test mode.
6. Data aligned with trimming voltage parameters.
7. Gain error evaluation with the two point method.
8. Temperature operating range: 0 ºC  T
9. Temperature operating range: -25 ºC  TA  105 ºC.
10. Temperature operating range: -40 ºC  TA  105 ºC.

Table 90. ADC accuracy characteristics at VDD/VDDA 5 V

1. Measured with RAIN < 10 k  (RAIN external series resistance interconnected between the AC signal generator and the
2. Temperature operating: T A = 25 °C.
3. Data based on characterization results, not tested in production.
4. ADC accuracy vs. negative injection current. Injecting negativ e current on any of the analog input pins should be avoided
5. Results in manufacturing test mode.
6. Data aligned with trimming voltage parameters.
7. Gain error evaluation with the two point method.
8. Temperature operating range: 0 ºC  T
9. Temperature operating range: -25 ºC  TA  105 ºC.
10. Temperature operating range: -40 ºC  TA  105 ºC.

Figure 35. ADC conversion accuracy  EO = offset error: deviation between the first actual transition and the first ideal one. the deviation of the characteristic slope).

12.3.11 Analog comparator characteristics

12.3.12 DAC characteristics

Table 91. Analog comparator characteristics(1)

1. The comparator logic accuracy parameters may be also impacted exceeding the VCPP and VCPM3
2. Data based on characterization results, not tested in production.
3. Maximum analog input voltage cannot exceed V DDA.
4. The comparator 3 can be configured with th e external reference voltage signal CPM3.
5. The overdrive voltage is ± 50 mV.
6. This parameter doesn't consider the delay time of comparator signal synchronization stages and SMED

Table 92. DAC characteristics

1. Data based on characterization results, not tested in production.

12.4 EMC characteristics

12.4.1 Electrostatic discharge (ESD)

depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). Data based on characterization results, not tested in production.

12.4.2 Static latch-up

conforms to the EIA/JESD 78 IC latch-up standard. Table 93. ESD absolute maximum ratings Table 94. Electrical sensitivity

13 Thermal characteristics

maximum chip junction temperature (TJmax). taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level. Table 95. Package thermal characteristics

1. Thermal resistance is based on the JEDEC JESD51- 2 with the 4-layer PCB in a natural convection

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

14.1 TSSOP38 package information

Figure 36. TSSOP38 package outline

Table 96. TSSOP38 package mechanical data(1)

1. TSSOP stands for “Thin Shrink Small Outline Package”.
2. Dimensions “D” and “E1”do not include the mold flash or protrusions. The mold flash or protrusions shall not exceed

14.2 VFQFPN32 package information

Figure 37. VFQFPN32 package outline

Table 97. VFQFPN32 package mechanical data(1)

1. VFQFPN stands for “Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead”.

Very thin profile: 0.80  A  1.00 mm. Package outline exclusive of any mold flash dimensions and metal burrs.

14.3 TSSOP28 package information

Figure 38. TSSOP28 package outline

Table 98. TSSOP28 package mechanical data(1)

1. TSSOP stands for “Thin Shrink Small Outline Package”.
2. Dimension “D” does not include mold fl ash, protrusions or gate burrs. Mold flash, protrusions or gate burrs

shall not exceed 0.15 mm per side.

1. Dimension “E1” does not include interlead flash or pr otrusions. Interlead flash or protrusions shall not

15 STLUX development environment

bypassing the need to generate software code.  Peripheral libraries: open source drivers necessary to drive each hardware block. access. Order code: STEVAL-ILL068V1. with the SMED without any software. probes using the SWIM interface (USB/SWIM). the code editing, compilation, optimization and debugging. Figure 39. STLUX development tools workflow

16 Order codes

Table 99. Ordering information Table 100. Document revision history 13-May-2015 1 Initial release.