STIR4200 ETC1 | Alldatasheet
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Integrated Mixed-Signal Solutions Copyright © 2003 SigmaTel, Inc. All rights reserved. All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc. SigmaTel, the SigmaTel logo, and combinations thereof are registered trademarks of SigmaTel, Inc. Other product names used in this pub- lication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or com- pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any t ime without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and spec ifically disclaims any and all liability, including without limitation special, consequential, or incidential damages. STIr4200 USB/IrDA Bridge Controller Version 2.0 April ‘03 OFFICIAL PRODUCT DOCUMENTATION 3-4200-D1-2.0-0403
2 3-4200-D1-2.0-0403 STIr4200 USB/IrDA Bridge Controller OFFICIAL PRODUCT DOCUMENTATION 1. TABLE OF CONTENTS
4 3-4200-D1-2.0-0403 STIr4200 USB/IrDA Bridge Controller OFFICIAL PRODUCT DOCUMENTATION 2. PRODUCT OVERVIEW 2.1. Features
- Low-power CMOS design IrDA data rates from 2.4 Kbps to 4 Mbps Obtains power from USB port Uses standard IrDA transceivers Optional LED driver for additional flexibility – LED driver capable of > 650 ma @ 5V, 25% duty cycle Full compliance to IrDA 1.3 and USB 1.1 specifications 4 Kbyte FIFO buffer memory Requires a single 12 Mhz crystal Windows 98/98SE/ME/2000/XP™ NDIS/USB driver Low-profile 28-Pin SSOP package 2.2. Description The SigmaTel STIr4200 is a low cost, low power, USB/IrDA Bridge Controller inte- grated circuit for enabling IrDA wireless data communications through a standard PC USB port. The STIr4200 directly interfaces to both single path and dual path receive IrDA transceiver module architectures and contains a USB controller, IrDA controller, interface logic, and memory buffer for full IrDA 1.3, 4 Mbps data transfer rates. A block diagram is hown in Figure 1. The STIr4200 is bundled with a Windows 98/98SE/ME/2000/XP™ NDIS/USB driver for enabling the implementation of a cost effective USB/IrDA Adapter solution for wireless data communications. 2.3. Ordering Information Part Number Package Temp Range Supply Range STIr4200S 28-Pin SSOP 0° C to +70° C Vdd = 3.1 - 3.6V Infrared Communication Transmission Infrared Transceiver SigmaTel USB/ IrDA Bridge Controller Data Transfer USB Connection to the PC
- CHARACTERISTICS AND SPECIFICATIONS
TJ Lead Solder Temperature 260 °C for 10 sec max. (HBM) requirements of +/- 2KV on all pins, except the TXDIODE pin (Pin 2), where the limit is +/1.5KV. Table 1. Absolute Maximum Ratings Table 2. Recommended Operating Conditions
12 Mhz
Figure 1. STIr4200 Block Diagram
matic of this arrangement is shown in Figure 2. Table 3. Electrical Characteristics Figure 2. Typical USB-IR Application
Digital IR Transceiver and ROM in the USB controller. that command at all, and this does NOT cause any problem of any kind in operation. during USB conformance testing. the data phase supplies the data for those registers. register to the Digital IR Transceiver.
1 Brequest 1 0x00 Write multiple registers
2 Wvalue 2 Not used (0x0000)
4 Windex 2 0x0001 –0x000f First register to write
6 Wlength 2 0x0001 –0x000f Number of registers to write
Table 4. Write Multiple Registers
1 Brequest 1 0x03 Write one register
2 Wvalue 2 LSB contains data The data to write the register
4 Windex 2 0x0001 – 0x000f Register to write
6 Wlength 2 Not used (0x0000)
Table 5. Write One Register
command is also used for the case of reading only one register. clear stall request is also supported.
1 BRequest 1 0x01 Read multiple registers
4 Windex 2 0x0001 – 0x000f First register to read
6 Wlength 2 0x0001 – 0x000f Number of registers to read
Table 6. Read Multiple Registers
0 BmRequestType 1 0xc0 Device to host, vendor type, device recipient
1 Brequest 1 0x02 Read ROM
4 Windex 2 0x0000 –0x00ff Base ROM address
6 Wlength 2 0x01 –0x0040 Number of ROM locations to read (64 bytes
Table 7. Read ROM
0 BmRequestType 1 0x42 Device to host, vendor type, endpoint
1 Brequest 1 0x01 Clear endpoint stall
4 Windex 2 0x0000 – 0x0002 Endpoint on which to clear stall
Table 8. Vendor Clear Stall
etc. The FIFO is 4K bytes in size. demodulator is filling the FIFO. Table 9. IrLAP Frame Figure 3. Block Diagram of Digital IR Transceiver
fashion as shown in Figure 4. Figure 4. SIR Transmit Frame Format
3-4200-D1-2.0-0403 11 STIr4200 USB/IrDA Bridge Controller OFFICIAL PRODUCT DOCUMENTATION 5.1.2. FIR Transmit Frame The FIR rate is 4 Mbps The frame organization is detailed in Figure 5. 0x55 0xAA LSB size MSB size 0x7E 0x7E BOF = Beginning of frame Header ID Data Data Data Data Data Data A CI Address/Control/Information Fields Special characters must be escaped Original Data Escaped Data 0x7D 0x7D 0x5D 0x7E 0x7D 0x5E 0x7F 0x7D 0x5F LSB CRC MSB CRC FCS : 32 bit CRC-IEEE802 0x7E EOF - End of frame Number of following bytes Data 0x7E 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F PREAMBLE : These characters cause the STIr4200S to generate the preamble sequence used by the receiving device for synchronization. There must be exactly 16 characters. /c130/c130/c130 /c130/c130/c130 /c130/c130/c130
acquired in the next bulk read. bility of the host software to reconstruct the frame. Figure 6. SIR Receive Frame Format
FIR receive frame format encoding scheme. Figure 7. FIR Receive Frame Format
- DIGITAL IR TRANSCEIVER REGISTERS
0 FIFO Data R/W Reserved
1 Mode Register R/W FIR Reserved SIR ASK FASTRXEN FFRSTEN FFSPRST PDCLK(8)
2 Baud Rate Register R/W PDCLK(7: 0)
3 Control Register R/W SDMODE RXSLOW DLOOP1 TXPWD RXPWD TXPWR(1: 0) SRESET
4 Sensitivity Register RXDSNS(2: 0) BSTUFF
5 Status Register EOFRAME
6 FIFO Count (Note 1)
7 FIFO Count (Note 1)
8 DPLL Tune Register RO DPCNT(5: 0) LONGP(1: 0)
9 IRDIG Setup Register R/W RXHIGH TXLOW Reserved Reserved Reserved Reserved Reserved Reserved
10 Reserved R/W Reserved
11 Reserved R/W Reserved
12 Reserved R/W Reserved
13 Reserved R/W Reserved
14 Reserved R/W Reserved
15 Test Register R/W PLLDWN LOOPIR LOOPUSB TSTENA TSTOSC(3: 0)
Table 10. Ir Transceiver Registers accessed during normal operation. Table 11. FIFO Data Register
be mutually exclusive with the SIR bit. 6 Reserved RO Reserved. Write as zero. mutually exclusive with the FIR bit.
4 ASK R/W When set, puts the infrared modulators into amplitude shift keying infrared
3 FASTRXEN R/W Enables simultaneous reads and writes to/from the FIFO. 2 FFRSTEN R/W Allows the FIFO receive shift register to be automatically reset in FIR mode. 0 PDCLK(8) R/W MSB of baud rate register. Table 12. Mode Register 7:0 PDCLK (7 : 0) R/W Sets the divide ratio of the PLL for the infrared modulator/demodulator. Table 13. Baud Rate Register
115.2 Kbps 0x20 0x09
57.6 Kbps 0x20 0x13
38.4 Kbps 0x20 0x1D
19.2 Kbps 0x20 0x3B
9.6 Kbps 0x20 0x77
2.4 Kbps 0x21 0xDF
Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation
7 SD/MODE R/W Use this bit only when the STIr4200 is connected to a TEMIC style infrared
down state or toggle the transceiver between high and low speed. POWER DOWN STATE: Set the SD/MODE bit to enter the power down state. Clear the SD/MODE bit to exit the power down state. set SD/MODE bit, then clear SD/MODE bit. set the SD/MODE bit, then clear the SD/MODE bit. and UOUT (SD/MODE) pins on the STIr4200. RXFAST as the receive input.
5 Reserved R Reserved
4 TXPWD R/W When set, powers down the infrared transmitter (modulator). 3 RXPWD R/W When set, powers down the infrared receiver (demodulator). 0 SRESET R/W When set, performs soft reset of the infrared modulator/demodulator. Table 15. Control Register
digital detector to declare the presence of a valid IrDA pulse.
101 Illegal 24
110 Illegal 28
111 Illegal Illegal
4 Reserved RO Reserved. Write as zero. 2-0 ID(2: 0) (Note 1) RO Revision ID of the chip. Table 16. Sensitivity Register 4 FFDIR RO When set, the FIFO is in transmit mode. When cleared, the FIFO is in receive mode. prohibit operation of the FIFO. The state of the bit can not be read. 2 FFEMPTY RO When set, indicates there is no data in the FIFO. Table 17. Status Register
Table 18. FIFO Count LSB 7-5 Reserved RO Write as zeros. Table 19. FIFO Count MSB default setting is proper for normal operation. used for chip debug purposes only. Table 20. DPLL Tune Register
7 RXHIGH R/W When set, this bit inverts the polarity of the data received by the
digital interface on the RXFAST and RXSLOW pins.
6 TXLOW R/W When set, this bits inverts the polarity of the data transmitted by
the digital interface on the TXDATA pin. Table 21. IRDIG Setup Register 7 PLLDWN R/W When set, powers down the secondary infrared transceiver PLL. PLL in this mode of operation.
6 LOOPIR R/W When set, puts the infrared transceiver into internal loop back
5 LOOPUSB R/W When set, puts the USB interface into loop back mode using the
4 TSTENA R/W Enables the oscillator to be powered down while in USB Suspend
should be used for chip debug purposes only. Table 22. Test Register
3 NC No connect
4 NC No connect
9 DGND PWR Digital power supply ground
10 V DD PWR Digital power supply (+)
11 AGND PWR USB transceiver power supply ground
12 D NEG I/O USB interface negative (-) data
13 NC No connect
14 NC No connect
15 NC No connect
16 NC No connect
18 V DA PWR USB transceiver power supply (+)
19 U IN I/O Test
20 TST-CLK I Test clock input
21 TSTD I/O Test data input/output
22 TST_EN I Test enable
23 RESETZ I Master reset, active low
24 GNDD PWR Power supply ground
25 XTALI I 12Mhz crystal/clock input
26 XTALO O 12Mhz crystal/clock output
27 NC No connect
28 NC No connect
Table 23. Pin Descriptions for STIr4200S 28-Pin SSOP Package Figure 8. STIr4200S 28-Pin SSOP Pin Assignment Drawing
Figure 9. 28-Pin SSOP Package Drawing