STLQ50XX STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 18
Technical content
Datasheet sections
- 1 Diagram
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Typical application
- 6 Typical characteristics
- 7 Application information
- 7.1 External components
- 7.2 Power dissipation
- 7.3 Protection
- 8 Package mechanical data
- 9 Revision history
Features
■ 2.3 V to 12 V input voltage range ■ 50 mA maximum output current ■ 3 µA quiescent current ■ Available in 1.8 V, 2.5 V, 3.3 V, 5.0 V and adjustable ■ 200 mV dropout voltage at 25 mA output current ■ Internal thermal protection ■ Available in SOT323-5L package, and SOT23- 5L package (upon request)
Applications
■ Portable/battery powered equipments ■ Electronic sensors ■ Microcontroller power ■ Real time clock backup power
Description
The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environment with very low power consumption constraints. Due to the very low quiescent current (3 µA) the device is suitable for those application that have very long stand-by time allowing extension of battery life. The P-MOS pass element allows also a very good drop-out figure (200 mV at 25 mA I O and 350 mV at full load) without affecting the consumption characteristics. Housed in the very small SOT323-5L or SOT23- 5L, it fulfils the space saving requirements in battery powered equipments. SOT23-5LSOT323-5L (available on request) Table 1. Device summary
1 Diagram
Figure 1. Block diagram
2 Pin configuration
Figure 2. Pin connections (top view) Table 2. Pin description
2 GND Ground
3 N/C Not connected
4 IN Input voltage
5 OUT Output voltage
3 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 3. Absolute maximum ratings Table 4. Thermal data
- This value is referred to a 4-layer PCB, JEDEC standard test board.
4 Electrical characteristics
Table 5. Electrical characteristics
- The maximum power dissipation must not be ex ceeded, see application information for details.
5 Typical application
Figure 3. Fixed versions: STLQ50 18- STLQ5025- STLQ5033- STLQ5050 Figure 4. Adjustable version STLQ50ADJ
6 Typical characteristics
Figure 5. V O vs TJ Figure 6. V O vs VI Figure 7. I Q vs TJ Figure 8. V DROP vs IO Figure 9. V DROP vs TJ Figure 10. Stability
7 Application information
The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environment with very low power consumption constraints. The very low quiescent current of 3 µA is obtained with use of CMOS technology that makes the device suitable for those application that have very long stand-by time. The very low power consumption allows extending the battery life and the tiny packages (SOT323-5L or SOT23-5L) fulfil the space saving requirements of battery powered equipments. Moreover the STLQ50 provides wide input voltage operation from 2.5 V up to 12 V. The P-MOS pass element allows also a very good drop-out figure: 0.7 V at full load and at 125 °C without affecting the consumption characteristics.
7.1 External components
The typical application schematic of STLQ50 is shown in Figure 1 - Figure 2, a 1 µF input and output capacitors placed close to the device are needed in order to provide proper operation. The device is stable with electrolytic and ceramic output capacitors having values higher than 1 µF (see figure typical characteristics for stability details). In the adjustable version (STLQ50) the output voltage is programmed using an external resistor divider as shown in Figure 2. The output voltage can be adjusted from 1.22 to 11 V and it can be calculated using the following formula: V O = VFB x (1+R1/R2) where VFB=1.222 V is the internal reference voltage; The sum between R1 and R2 resistors should be chosen in order to guarantee 1 µA of divider current at least. Lower value resistors will improve the noise performances but the quiescent current will increase. Higher value resistors should be avoided because the ADJ leakage current will influence the voltage set by the resistor divider making the above formula no more valid. The suggested design procedure is to choose R2 = 1 MΩ and then calculate R1 using the following formula: R1 = (VO/VFB-1) x R2
7.2 Power dissipation
In order to ensure proper operation, the STLQ50 junction temperature should never exceed 125 °C, this limits the maximum power dissipation the regulator can sustain in any application. The maximum power dissipation can be calculated as: P DMAX = (TJMAX - TA)/RthJA where TJMAX = 125 °C; TA is the ambient temperature; RthJA is the junction to ambient thermal resistance of the package (seeTable 4 thermal data). The power dissipation can be calculated simply as: P D = (VI - VO) x IO In every application condition, PD must be lower than PDMAX.
7.3 Protection
The P-MOS pass element has an internal diode with anode connected to VO and cathode to VI. In case VO > VI the current will flow from output to the input without any limitation. In this case proper limiting network is recommended. The current limitation is automatically provided by the characteristics of the PMOS pass element (see typical characteristics), so the short circuit current is dependent on the input voltage. When considering the short circuit current take care, in any case, to not exceed the maximum power dissipation sustainable by the device. The STLQ50 features an internal thermal protection that linearly reduces the output current when the internal temperature increases, consequently, at a given load, also the output voltage decreases. The action of the thermal protection starts at 125 °C when the output voltage slightly decreases, while close to 163 °C the output voltage drops to 0 V. Since this is a linear control, sudden over current conditions can quickly rise the chip temperature without time for the thermal protection to act, so it cannot be used as a limitation for the output current.
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Dim. mm. mil s. A0 . 80 1.10 31.5 4 3.3 A1 0.00 0.10 0.0 3.9 A2 0. 80 1.00 31.5 39.4 b 0.15 0. 305 . 9 11.8 C 0.10 0.1 83 .9 7.1 D1 . 80 2.20 70. 98 6.6 E1 . 80 2.40 70. 99 4.5 E1 1.15 1. 35 45. 3 53.1 e 0.65 25.6 e1 1. 3 51.2 L 0.10 0. 30 3.9 11.8 SOT323-5L mechanical data
Dim. mm. mil s. A0 . 90 1.45 35.4 57.1 A1 0.00 0.10 0.0 3.9 A2 0. 901 . 30 35.4 51.2 b 0.35 0.50 1 3.7 1 9.7 C0 . 0 9 0.20 3.5 7. 8 D2 . 80 3.00 110.2 11 8.1 E 1.50 1.75 5 9.0 6 8.8 e0 . 95 37.4 H 2.60 3.00 102. 3 118.1 L 0.10 0.60 3.9 23.6 SOT23-5L mechanical data 7049676D
Dim. mm. inch. A 175 1 801 856 . 889 7.086 7.2 83 D 20.2 0.7 95 N5 9.5 60 60.5 2. 362 T 14.4 0.567 Ao 2.25 0.0 88 Bo 2.7 0.106 Ko 1.2 0.047 Tape & reel SOT323-xL mechanical data
Dim. mm. inch. A1 80 7.0 86 D 20.2 0.7 95 N6 0 2 . 362 T 14.4 0.567 Tape & reel SOT23-xL mechanical data
9 Revision history
Table 6. Document revision history 07-Feb-2007 1 Initial release. 06-Jul-2007 3 Added part number. 14-Nov-2007 4 Added Table 1.