STLQ020 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 31
Technical content
Datasheet sections
- 1 Block diagrams
- 2 Pin configuration
- 3 Typical application
- 4 Maximum ratings
- 5 Electrical characteristics
- 6 Typical characteristics
- 7 Application information
- 7.1 External capacitors
- 7.2 Output voltage adjustment (adjustable version)
- 7.3 Enable pin operation
- 7.4 Power dissipation
- 7.5 Protection features
- 8 Package information
- 8.1 SOT323-5L package information
- 8.1.1 SOT323-5L tape and reel information
- 8.2 Flip-Chip4 package information
- 8.2.1 Flip-Chip4 reel information
- 8.3 DFN6 2x2 package information
- 8.3.1 DFN6 2x2 reel information
- 9 Ordering information
Features
- Operating input voltage range: 2 V to 5.5 V
- Output current up to 200 mA
- Ultra-low quiescent current: – 300 nA typ. at no load – 100 μA typ. at 200 mA load
- Controlled I q in dropout conditions
- Very low-dropout voltage: 160 mV at 200 mA
- Output voltage accuracy: 2% at room temperature, 3% in full temperature range
- Output voltage versions: from 0.8 V to 4.5 V, with 50 mV step and adjustable
- Logic-controlled electronic shutdown
- Output discharge feature (optional)
- Internal overcurrent and thermal protections
- Temperature range: from -40 °C to +125 °C
- Packages: DFN6-2x2, SOT323-5L, Flip-Chip4
Applications
- Smartphones/tablets
- Image sensors
- Wearable accessories
- Healthcare devices
- Metering
Description
The STLQ020 is a 200 mA low-dropout voltage regulator, able to work with an input voltage ranging from 2 V to 5.5 V. The typical dropout voltage at maximum load is 160 mV. The ultra-low quiescent current, which is just 0.3 μA at no load, extends battery-life of applications requiring very long standby time. Even though the device intrinsic consumption is ultra-low, STLQ020 is able to provide fast transient response and good PSRR performance, thanks to its adaptive biasing circuit. Enable pin puts the STLQ020 in shutdown mode, reducing total current consumption to 5 nA. The STLQ020 is designed to keep the quiescent current under control and at a low value also during dropout operation, helping to extend even more the operating time of battery- powered devices. It also includes short-circuit constant-current limiting and thermal protection. Several small package options are available. Maturity status link STLQ020 200 mA ultra-low quiescent current LDO STLQ020 Datasheet DS12072 - Rev 3 - June 2019 For further information contact your local STMicroelectronics sales office.
1 Block diagram
Figure 1. Block diagram (fixed version) Figure 2. Block diagram (adjustable version) Note: (*) output discharge function is optional.
2 Pin configuration
Figure 3. Pin configuration Table 1. Pin description pulled-up, don’t leave floating.
3 Typical application diagram
Figure 4. Typical application diagram (fixed version) Figure 5. Typical application diagram (adjustable version) Note: R 1 and R2 are calculated according to the following formula: R1 = R2 x (VOUT / VADJ - 1).
4 Maximum ratings
Table 2. Absolute maximum ratings Table 3. Thermal data
5 Electrical characteristics
TJ = 25 °C, VIN = VOUT + 0.5 V or 2 V, whichever is greater; VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA. Table 4. Electrical characteristics (fixed version)
- V IN = VOUT + 0.5 V or 2 V, whichever is greater.
- Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
- V IN = VOUT + 0.5 V or 2 V, whichever is greater.
- On specific version only.
- The thermal protection is not active when the load current is lower than 1 mA.
Electrical characteristics
TJ = 25 °C, VIN = 2 V, VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA. Table 5. Electrical characteristics (adjustable version)
- Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
- The thermal protection is not active when the load current is lower than 1 mA.
- On specific version only.
6 Typical characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C. Figure 6. Output voltage vs. temperature Figure 7. Output voltage vs. temperature Figure 8. Output voltage vs. temperature Figure 9. Output voltage vs. temperature
7 Application information
7.1 External capacitors
The STLQ020 voltage regulator requires external low ESR capacitors to assure the control loop stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance defined in the following chapters. Input and output capacitors should be located as close as possible to the relevant pins. Input capacitor An input capacitor, with a minimum value of 1 μF, must be located as close as possible to the input pin of the device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps to ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection. Capacitance higher than 1 µF can be chosen in case of fast load transients in application. Output capacitor STLQ020 requires a low-ESR capacitor connected on its output, to keep the control loop stable and reduce the risk of ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor (such as X5R/X7R types) with a minimum value of 1 µF and equivalent series resistance in the [3 – 500 mΩ] range. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the expected stability region. There is no maximum limit to the output capacitance, provided that the above conditions are respected.
7.2 Output voltage adjustment (adjustable version)
In the adjustable version, available on the DFN6-2x2 and SOT323-5L packages, the output voltage can be adjusted to any voltage, starting from 0.8 V (VADJ) up to the input voltage minus the voltage drop (VDROP) across the internal power pass element, by connecting a resistor divider between the ADJ pin and the output, allowing the remote voltage sensing. The resistor divider should be selected using the following equation: Equation 1 VOUT = VADJ (1 + R1 / R2) with VADJ = 0.8 V (typ.) and VOUT < VIN-VDROP(MAX) For best accuracy and stability the resistor divider should be designed in order to allow that a current of at least 500 nA flows across it. The current flowing into the ADJ pin is typically less than 1 nA, therefore causing negligible change in final the output voltage.
7.3 Enable pin operation
This is a logic control pin, CMOS level-compatible, which can be used to turn On/Off the regulator.It is active high, so when it is pulled down, the device enters the shutdown mode, drastically reducing the current consumption, to less just few nA. Since it is not internally pulled-up, when the enable feature is not used, this pin must not be left floating. It can be tied to VIN to keep the regulator output in ON state all the time. To assure reliable operation, the signal source used to drive the EN pin, must be able to swing above and below the specified thresholds listed in the electrical characteristics table (VEN).
7.4 Power dissipation
A proper PCB design is recommended, to ensure that the device internal junction temperature is kept below 125°C, in all the operating condition. Depending on the package option, the thermal energy generated by the device flows from the die surface to the PCB copper area through the package leads, solder bumps and/or exposed pad. STLQ020
Application information
DS12072 - Rev 3 page 13/31
The PCB copper area acts as a heat sink. The footprint copper pads should be as wider as possible to spread and dissipate the heat to the surrounding environment. Thermal vias to the inner or backside copper layers improve the overall thermal performance of the device. The power dissipation of the LDO depends on the input voltage, output voltage and output current, and is given by: Equation 2 PD = (VIN -VOUT) IOUT The junction temperature of the device is: Equation 3 TJ_MAX = TA + RthJA x PD where: TJ_MAX is the maximum junction of the die, 125 °C; TA is the ambient temperature; RthJA is the thermal resistance junction-to-ambient. With the above equation it is possible to calculate the maximum allowable power dissipation, therefore the maximum load current for a certain voltage drop. Appropriate de-rating of the operating condition can be applied accordingly.
7.5 Protection features
The STLQ020 embeds a constant-current limit circuit, which acts in case of overload or short-circuit on the output, clamping the load current to a safe value (typ. 380 mA). Normal operation is restored if the overload disappears, but prolonged operation in current limit may lead to high power dissipation inside the LDO and subsequently to thermal shutdown. Thermal protection An internal thermal feedback loop disables the output voltage if the die temperature reaches approximately 160 °C. This feature protects the device from excessive temperature that could lead to permanent damage to the LDO. Once the thermal protection is triggered and the device is shut down, normal operation is automatically recovered if the die temperature falls below 140 °C (thermal protection hysteresis of 20 °C typically) Important note: to keep the device power consumption below 500 nA in low load/no load condition, the internal thermal protection is kept disabled for load current below 1 mA. Current and thermal limit protections are designed to protect the LDO from excessive power dissipation and not intended to replace a proper thermal and electrical design of the application. Continuous operation above the maximum ratings may lead to permanent damage to the device. STLQ020 Protection features DS12072 - Rev 3 page 14/31
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
8.1 SOT323-5L package information
Figure 34. SOT323-5L package outline
Package information
DS12072 - Rev 3 page 15/31
Table 6. SOT323-5L package mechanical data Figure 35. SOT323-5L recommended footprint
8.1.1 SOT323-5L tape and reel information
Figure 36. SOT323-5L tape outline
Figure 37. SOT323-5L reel outline
8.2 Flip-Chip4 package information
Figure 38. Flip-Chip4 package outline Table 7. Flip-Chip4 mechanical data
Figure 39. Flip-Chip4 recommended footprint
8.2.1 Flip-Chip4 reel information
Figure 40. Flip-Chip4 reel outline
Figure 41. Flip-Chip4 tape outline
8.3 DFN6 2x2 package information
Figure 42. DFN6 2x2 package outline
Table 8. DFN6 2x2 package mechanical data Figure 43. DFN6 2x2 recommended footprint
8.3.1 DFN6 2x2 tape information
Figure 44. DFN6 2x2 tape outline
9 Ordering information
Table 9. Order codes Figure 45. Marking composition (flip-chip)
Ordering information
DS12072 - Rev 3 page 26/31
Revision history
Table 10. Document revision history 27-Mar-2017 1 Initial release. 05-Dec-2017 2 Added: Section 6 Typical characteristics and Section 7 Application information. information and Section 8.3.1 DFN6 2x2 tape information.