STLD1

STLD1 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

• Dual line driver suitable for differential or single-ended configuration
• Up to 18 V p-p single-ended, 36 V p-p differential output range
• Very high linearity for EMC compliance
• Externally configurable power amplifier topology
• Up to 1.5 A RMS max. current
• Embedded overtemperature protection
• Suitable for any narrow-band power-line communication (PLC) applications
• Available in QFN24 (4x4x1 mm) package
• -40 °C to +105 °C temperature range

Applications

• Smart metering, smart grid and Internet of Things applications
• Suitable for application designs compliant with CENELEC, FCC and ARIB regulations

Description

The STLD1 line driver is a low-distortion, high-current dual power amplifier specifically designed for power-line communication applications, where high output current drives the AC power-line loads. Operating on a single 8-18 V supply, the STLD1 can deliver high output current up to

1.5 ARMS and an output voltage swing-up to 18 V peak-to-peak single-ended / 36 V

peak-to-peak differential. The STLD1 features a very low output impedance (down to 0.1 Ω in the typical configuration) to ensure efficient transfer of power to very low impedance loads, typically between 5 Ω and 100 Ω. The device has very low in-band and out-of-band two-tone intermodulation distortion (IM3) as well as very high spurious-free dynamic range (SFDR) to guarantee and meet CENELEC, ARIB and FCC emission requirements. It also features thermal shutdown as well as current sense output. Product status link STLD1 Order code Package Packing STLD1 QFN24 (4x4 x1 mm) Tray STLD1TR Tape and reel Power-line communication dual line driver STLD1 Datasheet DS12339 - Rev 2 - June 2018 For further information contact your local STMicroelectronics sales office.

1 Block diagram

Figure 2. STLD1 basic block diagram

2 Pin configuration

Figure 3. Pin connections Table 1. Pin descriptions

1 PGND Power amplifier ground

6 PGND Power amplifier ground

7 PVCC 8-18 V power amplifier supply input

8 VCC

8-18 V analog supply input for 5 V internal regulator and analog circuitry.

9 AGND

10 CSF_OUT Power amplifier current feedback output

11 AVDD_5V

5 V internal regulator output

12 RSV0 Reserved - connect to AGND

13 PA1_INN Power amplifier 1 negative input

14 PA1_INP Power amplifier 1 positive input

15 PA2_INP Power amplifier 2 positive input

16 PA2_INN Power amplifier 2 negative input

17 RSV1 Reserved - leave floating

18 RSV2 Reserved - connect to AGND

19 RSV3 Reserved - connect to AGND

20 THERM Thermal feedback current output

21 IBIAS_IN Reference current input

22 TX_ON_2

Enable for power amplifier 2 (active high) Force low to set PA2_OUT to Hi-Z ( approx. 30 kΩ )

23 TX_ON_1

Enable for power amplifier 1 (active high) Force low to set PA1_OUT to Hi-Z ( approx. 30 kΩ )

24 PVCC Power amplifier supply input

25 Exposed pad It has to be connected to an AGND ground plane on PCB

3 Absolute maximum ratings

Table 2. Absolute maximum ratings Table 3. Thermal characteristics Table 4. Thermal data

4 Electrical characteristics

T(AMB) = -40 to +105 °C, T(J) < 125 °C unless otherwise specified. Typical values are at T(AMB) = 25 °C. Table 5. Power supply characteristics Table 6. Line driver characteristics V(PAx_OUT) BIAS Power amplifier output. V(PA_IN) BIAS Power amplifier input. V(PA_OUT) HD2 Power amplifier output. V(PAx_OUT) HD3 Power amplifier output. V(PAx_OUT) THD Power amplifier output. V(PAx_OUT) HD2 Power amplifier output. V(PAx_OUT) HD3 Power amplifier output. V(PAx_OUT)THD Power amplifier output.

Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit C(PAx_INP), C(PAx_INN) Power amplifier input capacitance PA_IN+ vs. AGND, see (1) 10 pF PA_IN- vs. AGND, see (1) 10 pF PSRR Power supply rejection ratio

50 Hz -100 dB

CSF_RATIO Ratio between PA_OUT and CSF output current 106 A/A IBIAS_IN Reference current input Typical conditions 16 or 32 μA IM3 in-band In band 3rd order intermodulation distortion VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz (2) -72 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -71 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -67 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) -74 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -72 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -68 dB IM3 out-of-band Out-of-band third-order intermodulation distortion VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz (2) -71 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -68 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -65 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) -75 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -73 dB VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -68 dB STLD1

Symbol Parameter Test conditions Min. Typ. Max. Unit SFDR Spurious-free dynamic range VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) 71 dBc VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) 68 dBc VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) 65 dBc VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) 69 dBc VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) 68 dBc VCC = 15 V, Vout = 12 V p-p (single- ended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) 67 dBc V(TX_ON_x) IL TX_ON_x pin input low level voltage AGND 0.95 V V(TX_ON_x) IH TX_ON_x pin input high level voltage 1.85 AVDD_5V V V(TX_ON_x) HYST TX_ON_x pin input voltage hysteresis 500 mV T1 Thermal sensor threshold see (2) 70 °C T2 Thermal sensor threshold see (2) 100 °C T3 Thermal sensor threshold see (2) 125 °C T4 Thermal sensor threshold see (2) 170 °C T_HYST Thermal sensor hysteresis see (2) 10 °C 1. Not tested in production, guaranteed by design. 2. Characterization data, not tested in production. Figure 4. Line driver test circuit (single-ended configuration)

Figure 5. Line driver test circuit (differential)

5 Device characteristics

5.1 Thermal protection

current, according to the relationship described in the following table. Table 7. Thermal current level vs. junction temperature

5.2 Current feedback

5.3 Power management

Figure 6. Power supply scheme

8 V to

6.1 QFN24L (4x4x1 mm) package information

Figure 7. QFN24L (4x4 mm) package outline Table 8. QFN24L (4x4 mm) package mechanical data

Revision history

Table 9. Document revision history 25-Oct-2017 1 Initial release.