STLC60135 STMICROELECTRONICS | Alldatasheet
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Technical content
DTM modem for ADSL, compatible with the following standards: – ANSI T1.413 Issue 2 – ITU-T G.992.1 (G.dmt) – ITU-T G.992.2 (G.lite) Same chip for both ATU-C and ATU-R Supports either ATM (Utopia level 1 & 2) or bit- stream interface 16 bit multiplexed microprocessor interface (lit- tle and big endian compatibility) Analog Front End management Dual latency paths: fast and interleaved ATM’s PHY layer: cell processing (cell deline- ation, cell insertion, HEC) ADSL’s overhead management Reed Solomon encode/decode Trellis encode/decode(Viterbi) DMT mapping/ demapping over 256 carriers Fine (2ppm) timing recover using Rotor and Adaptative Frequency Domain Equalizing Time Domain Equalization Front end digital filters 0.35µm HCMOS6 Technology 144 pin PQFP package Power Consumption 1 Watt at 3.3V
Applications
ATU-C: DSLAM, Routers at Central Office ATU-R: Routers at SOHO, stand-alone mo- dems, PC mother boards General Description The STLC60135 is the DMT modem and ATM framerof theSTMicroelectronics Tosca chipset. When coupled with STLC60134 analog front-end and an external controller running dedicated firm- ware, the product fulfils ANSI T1.413 “Issue 2” DMT ADSL specification. The STLC60135 may be used at both ends of ADSL loop: ATU-C and ATU-R. The chip sup- ports UTOPIA level 1 and UTOPIA level 2 inter- face and a non ATM synchronous bit-stream in- terface. September 1999 PQFP144 ORDERING NUMBER: STLC60135 STLC60135 TOSCA ADSL DMT TRANSCEIVER TEST MODULE DATA SYMBOL TIMING UNIT VCXO DSP FRONT-END FFT/IFFT ROTOR TRELLIS CODING MAPPER/ DEMAPPER GENERIC TC REED/ SOLOMON ATM SPECIFIC TC INTERFACE MODULE CONTROLLER INTERFACEAFE CONTROL INTERFACE TEST SIGNALS CLOCK STM UTOPIA AFE INTERFACE D98TL315 AFE CONTROL CONTROLLER BUS GENERAL PURPOSE I/Os Figure 1. Block Diagram
ing, bit interleaving and 4D trellis coding. with and without interleaving. carries out the consequent adaptationoperations. for the Charged Device Model (CDM). is limited to 100mA to prevent latch-up. Figure 2. Pin Connection
Pin Name Type Supply Driver BS Function
1 VSS 0V Ground
2 AD_0 B VDD BD8SCR B Data 0
3 AD_1 B VDD BD8SCR B Data 1
4 AD_2 B VDD BD8SCR B Address / Data 2
5 VDD (V
SS + 3.3V) Power Supply
6 AD_3 B VDD BD8SCR B Address / Data 3
7 AD_4 B VDD BD8SCR B Address / Data 4
8 VSS 0V Ground
9 AD_5 B VDD BD8SCR B Address / Data 5
10 AD_6 B VDD BD8SCR B Address / Data 6
11 VDD (V
SS + 3.3V) Power Supply
12 AD_7 B VDD BD8SCR B Address / Data 7
13 AD_8 B VDD BD8SCR B Address / Data 8
14 AD_9 B VDD BD8SCR B Address / Data 9
15 VSS 0V Ground
16 AD_10 B VDD BD8SCR B Address / Data 10
17 AD_11 B VDD BD8SCR B Address / Data 11
18 VDD (V
SS + 3.3V) Power Supply
19 AD_12 B VDD BD8SCR B Address / Data 12
20 VSS 0V Ground
21 PCLK I VDD IBUF I Processor clock
22 VDD (V
SS + 3.3V) Power Supply
23 AD_13 B VDD BD8SCR B Address / Data 13
24 AD_14 B VDD BD8SCR B Address / Data 14
25 AD_15 B VDD BD8SCR B Address / Data 15
26 VSS 0V Ground
27 BE1 I VDD IBUF I Address 1
28 ALE I VDD IBUF C Address Latch
29 VDD (V
SS + 3.3V) Power Supply
30 CSB I VDD IBUF I Chip Select
31 WR_RDB I VDD IBUF I Specifies the direction of the access cycle
32 RDYB OZ VDD BT4CR O Controls the ATC bus cycle termination
33 OBC_TYPE I-PD VDD IBUF I ATC Mode Selection (0 = i960; 1 = generic)
34 INTB O VDD IBUF O Requests ATC interrupt service
35 RESETB I VDD IBUF I Hard reset
36 VSS 0V Ground
37 VDD (V
SS + 3.3V) Power Supply
38 U_RxData_0 OZ VDD BD8SRC B Utopia RX Data 0
39 U_RxData_1 OZ VDD BD8SRC B Utopia RX Data 1
40 VSS 0V Ground
41 U_RxData_2 OZ VDD BD8SRC B Utopia RX Data 2
42 U_RxData_3 OZ VDD BD8SRC B Utopia RX Data 3
43 VDD (V
SS + 3.3V) Power Supply STLC60135
PIN FUNCTIONS (continued) Pin Name Type Supply Driver BS Function
44 U_RxData_4 OZ VDD BD8SRC B Utopia RX Data 4
45 U_RxData_5 OZ VDD BD8SRC B Utopia RX Data 5
46 VSS 0V Ground
47 U_RxData_6 OZ VDD BD8SRC B Utopia RX Data 6
48 U_RxData_7 OZ VDD BD8SRC B Utopia RX Data 7
49 VDD (V
SS + 3.3V) Power Supply
50 U_RxADDR_0 I VDD IBUF I Utopia RX Address 0
51 U_RxADDR_1 I VDD IBUF I Utopia RX Address 1
52 U_RxADDR_2 I VDD IBUF I Utopia RX Address 2
53 U_RxADDR_3 I VDD IBUF I Utopia RX Address 3
54 VSS 0V Ground
55 U_RxADDR_4 I VDD IBUF I Utopia RX Address 4
56 GP_IN_0 I-PD VDD IBUFDQ I General purpose input 0
57 VDD (V
SS + 3.3V) Power Supply
58 GP_IN_1 I-PD VDD IBUFDQ I General purpose input 1
59 VSS 0V Ground
60 U_RxRefB O VDD IBUF O 8kHz clock to ATM device
61 U_TxRefB I VDD BT4CR I 8kHz clock from ATM device
62 VDD (V
SS + 3.3V) Power Supply
63 U_Rx_CLK I VDD IBUF Utopia RX Clock
64 U_Rx_SOC OZ VDD BD8SCR Utopia RX Start of Cell
65 U_RxCLAV OZ VDD BD8SCR Utopia RX Cell Available
66 U_RxENBB I VDD IBUF Utopia RX Enable
67 VSS 0V Ground
68 U_Tx_CLK I VDD IBUF Utopia TX Clock
69 U_Tx_SOC I VDD IBUF Utopia TX Start of Cell
70 U_TxCLAV OZ VDD BD8SCR Utopia TX Cell Available
71 U_TxENBB I VDD IBUF Utopia TX Enable
72 VDD (V
SS + 3.3V) Power Supply
73 VSS 0V Ground
74 U_TxData_7 I VDD IBUF I Utopia TX Data 7
75 U_TxData_6 I VDD IBUF I Utopia TX Data 6
76 VDD (V SS + 3.3V) Power Supply
77 U_TxData_5 I VDD IBUF I Utopia TX Data 5
78 U_TxData_4 I VDD IBUF I Utopia TX Data 4
79 U_TxData_3 I VDD IBUF I Utopia TX Data 3
80 U_TxData_2 I VDD IBUF I Utopia TX Data 2
81 VDD (V
SS + 3.3V) Power Supply
82 U_TxData_1 I VDD IBUF I Utopia TX Data 1
83 U_TxData_0 I VDD IBUF I Utopia TX Data 0
84 U_TxADDR_4 I VDD IBUF I Utopia TX Address 4
85 U_TxADDR_3 I VDD IBUF I Utopia TX Address 3
86 VDD (V
SS + 3.3V) Power Supply
87 U_TxADDR_2 I VDD IBUF I Utopia TX Address 2
88 U_TxADDR_1 I VDD IBUF I Utopia TX Address 1
89 U_TxADDR_0 I VDD IBUF I Utopia TX Address 0
90 SLR_ FRAME_F O VDD BT4CR Frame Identifier Fast
91 VSS 0V Ground
PIN FUNCTIONS (continued) Pin Name Type Supply Driver BS Function
92 SLR_FRAME_S O VDD BT4CR Receive Frame Identifier Interleaved
93 SLR_DATA_S_1 O VDD BT4CR Receive Data Interleave 1
94 SLR_DATA_S_0 O VDD BT4CR Receive Data Interleave 0
95 VDD (V
SS + 3.3V) Power Supply
96 SLR_VAL_S O VDD BT4CR Receive Data Valid Indicator Interleaved
97 SLR_DATA_F_1 O VDD BT4CR Receive Data Fast 1
98 SLR_DATA_F_0 O VDD BT4CR Receive Data Fast 0
99 SLR_VAL_F O VDD BT4CR Receive Data Valid Indicator Fast
100 SLAP_CLOCK O VDD BT4CR Clock for SLAP I/F
101 SLT_FRAME_F O VDD BT4CR Transmit Start of frame Indicator Fast
102 VSS 0V Ground
103 SLT_DATA_F_1 I VDD IBUFDQ Transmit Data Fast 1
104 SLT_DATA_F_0 I VDD IBUFDQ Transmit Data Fast 0
105 SLT_DATA_S_1 I VDD IBUFDQ Transmit Data Interleave 1
106 SLT_DATA_S_0 I VDD IBUFDQ Transmit Data Interleave 0
107 SLT_REQ_F O VDD BT4CR Transmit Byte Request Fast
108 VDD (V
SS + 3.3V) Power Supply
109 VSS 0V Ground
110 SLT_REQ_S O VDD BT4CR Transmit Byte Request Interleaved
111 STL_FRAME_S O VDD BT4CR Transmit Start of frame Indication Interleaved
112 TDI I-PU VDD IBUFUQ JTAG I/P
113 TDO OZ VDD BT4CR JTAG O/P
114 TMS I-PU VDD IBUFUQ JTAG Made Select
115 VDD (V
SS + 3.3V) Power Supply
116 TCK I-PD VDD IBUFDQ JTAG Clock
117 VSS 0V Ground
118 TRSTB I-PD VDD IBUFDQ JTAG Reset
119 TESTSE I VDD IBUF none Enables scan test mode
120 GP_OUT O VDD BD8SCR O General purpose output
121 PDOWN O VDD BT4CR O Power down analog front end (Reset)
122 VDD (V
SS + 3.3V) Power Supply
123 AFRXD_0 I VDD IBUF I Receive data nibble
124 AFRXD_1 I VDD IBUF I Receive data nibble
125 AFRXD_2 I VDD IBUF I Receive data nibble
126 AFRXD_3 I VDD IBUF I Receive data nibble
127 VSS 0V Ground
128 CLWD I VDD IBUF I Start of word indication
129 MCLK I VDD IBUF C Master clock
130 CTRLDATA O VDD BT4CR O Serial data Transmit channel
131 VDD (V
SS + 3.3V) Power Supply
132 AFTXED_0 O VDD BT4CR O Transmit echo nibble
133 AFTXED_1 O VDD BT4CR O Transmit echo nibble
134 VSS 0V Ground
135 AFTXED_2 O VDD BT4CR O Transmit echo nibble
136 AFTXED_3 O VDD BT4CR O Transmit echo nibble
137 VDD (V
SS + 3.3V) Power Supply
138 IDDq I VDD IBUF none Test pin, active high
PIN FUNCTIONS (continued) Pin Name Type Supply Driver BS Function
139 AFTXD_0 O VDD BT4CR O Transmit data nibble
140 AFTXD_1 O VDD BT4CR O Transmit data nibble
141 VSS 0V Ground
142 AFTXD_2 O VDD BT4CR O Transmit data nibble
143 AFTXD_3 O VDD BT4CR O Transmit data nibble
144 VDD (V
SS + 3.3V) Power Supply I/O DRIVER FUNCTION Driver Function BD4CR CMOS bidirectional, 4mA, slew rate control BD8SCR CMOS bidirectional, 8mA, slew rate control, Schmitt trigger IBUF CMOS input IBUFDQ CMOS input, pull down, IDDq control IBUFUQ CMOS input, pull up, IDDq control PIN SUMMARY Mnemonic Type BS Type Signals Function Power Supply VDD (V SS + 3.3V) Power Supply VSS 0V Ground ATC Interface ALE I C 1 Used to latch the address of the internal register to be accessed PCLK I I 1 Processor clock CSB I I 1 Chip selected to respond to bus cycle BE1 I I 1 Address 1 (not multiplexed) WR_RDB I I 1 Specifies the direction of the access cycle RDYB OZ O 1 Controls the ATC bus cycle termination INTB O O 1 Requests ATC interrupt service AD IO B 16 Multiplexed Address/Data bus OBC_TYPE I-PD I 1 Select between i960 (0) or generic (1) controller interface Test Access Part Interface TDI I-PU 1 refer to section TDO OZ 1 TCK I-PD 1 TMS I-PU 1 TRSTB I-PD 1 Analog Front End Interface AFRXD I I 4 Receive data nibble AFTXD O O 4 Transmit data nibble AFTXED O O 4 Transmit echo nibble CLWD I I 1 Start of word indication PDOWN O O 1 Power down analog front end CTRLDATA O O 1 Serial data transmit channel MCLK I C 1 Master clock STLC60135
PIN SUMMARY (continued) Mnemonic Type BS Type Signals Function ATM UTOPIA Interface U_RxData OZ B 8 Receive interface Data U_TxData I I 8 Transmit interface Data U_RxADDR I I 5 Receive interface Address U_TxADDR I I 5 Transmit interface Address U_RxCLAV OZ O 1 Receive interface Cell Available U_TxCLAV OZ O 1 Transmit interface Cell Available U_RxENBB I-TTL I 1 Receive interface Enable U_TxENBB I-TTL I 1 Transmit interface Enable U_RxSOC OZ O 1 Receive interface Start of Cell U_TxSOC I-TTL I 1 Transmit interface Start of Cell U_RxCLK I-TTL C 1 Receive interface Utopia Clock U_TxCLK I-TTL C 1 Transmit interface Utopia Clock U_RxRefB O O 1 8kHz reference clock to ATM device U_TxRefB I-TTL I 1 8kHz reference clock from ATM device ATM SLAP Interface SLR_VAL_S O 1 SLR_VAL_F O 1 SLR_DATA_S O 2 SLR_DATA_F O 2 SLT_REQ_S O 1 SLT_REQ_F O 1 SLT_DATA_S I 2 SLT_DATA_F I 2 SLAP_CLOCK O 1 SLR_FRAME_I O 1 SLT_FRAME_I O 1 SLR_FRAME_F O 1 SLT_FRAME_F O 1 Miscellaneous GP_IN I-PD I 2 General purpose input GP_OUT O O 1 General purpose output RESETB I I I Hard reset TESTSE I none none Enable scan test mode IDDq I none none Test pin, active high I = Input, CMOS levels I-PU = Input with pull-up resistance, CMOS levels I-PD = Input with pull-down resistance, CMOS levels I-TTL = Input TTL levels O = Push-pull output OZ = Push-pull output with high-impedance state IO = Input / Tristate Push-pull output BS cell = Boundary-Scan cell I = Input cell O = Output cell B = Bidirectional cell C = Clock STLC60135
symbol from frequency domain to time domain. by the firmware running on an external controller. tation of the received code constellation (Rotor). likely constellationsubset to be used. where n < 15 for all carriers. Figure 6. Generic TC Layer Functions
lation and from the loop after demodulation. tion module) or a byte stream (from the deframer). dumped on the bitstream interface (with no fifo). the Utopia PHY address register. Utopia Level 1 supports only one PHY device. Utopia Level 2 specifications). directionsfor Fast and Interleaved channel). Figure 14. Waveforms All AC characteristics are indicated for a 100pF capacitive load.
on the rising edge of RxClk. Figure 18. Timing (Utopia 1 Transmit Interface)
Pin Description Utopia 2 (Receive Interface) Name Type Meaning Usage Remark RxClav O Receive Cell available Signals to the ATM chip that the STLC60135 has a cell ready for transfer Remains active for the entire cell transfer RxEnb* I Receive Enable Signals to the physical layer that the ATM chip will sample and accept data during next clock cycle RxData and RxSOC could be tri- state when RxEnb* is inactive (high) RxClk I Receive Byte Clock Gives the timing signal for the transfer, generated by ATM layer chip. RxData O Receive Data (8 bits) ATM cell data, from physical layer chip to ATM chip, byte wide. RxSOC O Receive Start Cell Identifies the cell boundary on RxData Indicate to the ATM layer chip that RxData contains the first valid byte of a cell. RxAddr I Receive Address (5 bits) Use to select the port that will be active or polled RxRef * O Reference Clock 8kHz clock transported over the network *Active low signal Utopia Level 2 Signals The physical chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the fifo of the physical layer chip. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting RxEnb*. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled RxEnb* active. It also advances the off- set in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. STLC60135 Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The STLC60135 sup- ports only the required mode, this mode is re- ferred to as ”Operation with 1 TxClav and 1 RxClav”. PHY Device Identification The STLC60135 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register. Beware that an incorrect address con- figuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Uto- pia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface control register. STLC60135
Table 3: Master Clock (MCLK) AC Electrical Characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit F Clock Frequency 35.328 MHz Tper Clock Period 28.3 ns Th Clock Duty Cycle 40 60 % Table 4: AFTXD, AFTXED, CLWD AC Electrical Characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit Tv Data Valid Time 0 10 ns Tc Data Valid Time 0 10 ns Table 5: AFRXD AC Electrical Characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit Ts Data setup Time 5 ns Th Data hold Time 5 ns Tests, Clock, JTAG Interface - Mclk: Master Clock (35.328MHz) generated by VCXO - ATM receive interface, asynchronous clock gen- erated by Utopia Master - ATM transmit interface, asynchronous clock generated by Utopia Master - ATC clock (Pclk): external asynchronous clock (synchronous with ATC in case of i960 specific in- terface) JTAG TP interface: Standard Test Access Port, Used with the boundary scan for chip and board testing. This JTAG TAP interface consists in 5 signals: TDI, TDO, TCK & TMS. TSRTB: Test Reset, reset the TAP controller. TRSTB is an active low signal. Table 6: Boundary Scan Chain Sequence Sequence Number Mnemonic Pin BS Type
2 AD_0 B
3 AD_1 B
4 AD_2 B
6 AD_3 B
7 AD_4 B
9 AD_5 B
10 AD_6 B
12 AD_7 B
13 AD_8 B
14 AD_9 B
16 AD_10 B
17 AD_11 B
19 AD_12 B
21 PCLK I
23 AD_13 B
24 AD_14 B
25 AD_15 B
27 BE1 I
28 ALE C
30 CSB I
31 WR_RDB I
32 RDYB O
33 OBC_TYPE I
34 INTB O
35 RESETB I
38 U_RxData_0 B
39 U_RxData_1 B
41 U_RxData_2 B
42 U_RxData_3 B
44 U_RxData_4 B
45 U_RxData_5 B
46 VSS
47 U_RxData_6 B
48 U_RxData_7 B
50 U_RxADDR_0 I
51 U_RxADDR_1 I
52 U_RxADDR_2 I
53 U_RxADDR_3 I
55 U_RxADDR_4 I
56 GP_IN_0 i
58 GP_IN_1 I
60 U_RxRefB O
Table 6:(continued) Sequence Number Mnemonic Pin BS Type
61 U_TxRefB I
63 U_RxCLK
64 U_RxSOC
65 U_RxCLAV
66 U_RxENBB
68 U_TxCLK
69 U_TxSOC
70 U_TxCLAV
71 U_TxENBB
74 U_TxData_7 I
75 U_TxData_6 I
77 U_TxData_5 I
78 U_TxData_4 I
79 U_TxData_3 I
80 U_TxData_2 I
82 U_TxData_1 I
83 U_TxData_0 I
84 U_TxADDR_4 I
85 U_TxADDR_3 I
87 U_TxADDR_2 I
88 U_TxADDR_1 I
89 U_TxADDR_0 I
90 SLR_FRAME_F
92 SLR_FRAME_S
93 SLR_DATA_S_1
94 SLR_DATA_S_0
96 SLR_DATA_S
97 SLR_DATA_F_1
98 SLR_DATA_F_0
99 SLR_VAL_F
100 SLAP_CLOCK
101 SLT_FRAME_F
103 SLT_DATA_F_1
104 SLT_DATA_F_0
105 SLT_DATA_S_1
106 SLT_DATA_S_0
107 SLT_REQ_F
110 SLT_REQ_S
111 SLT_FRAME_S
112 TDI
113 TDO
114 TMS
116 TCK
118 TRSTB
119 TESTSE none
120 GP_OUT O
121 PDOWN O
123 AFRXD_0 I
124 AFRXD_1 I
125 AFRXD_2 I
126 AFRXD_3 I
128 CLWD 1 I
129 MCLK 1 C
130 CTRLDATA 1 O
132 AFTXED_0 O
133 AFTXED_0 O
135 AFTXED_0 O
136 AFTXED_0 O
138 IDDq none
139 AFTXD_0 O
140 AFTXD_1 O
142 AFTXD_0 O
143 AFTXD_1 O
General purpose I/O register 2 generalPurpose Register (0x040) Field Type Position bits Length Function GP_IN R [0,1] 2 Sampled level on pins GP_IN GP_OUT RW [2] 1 Output level on pins GP_OUT bits from 3 to 15 are reserved Reset Initialization The STLC60135 supports two reset modes: - A ’hardware’ reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to guarantee a correct reset operation. All clocks and power supplies must be stable for 200ns prior to the rising edge of the RESETB signal. - ’Soft’ reset activated by the controller write ac- cess to a soft reset configuration bit. The reset process takes less than 10000 MCLK clock cy- cles. ELECTRICAL SPECIFICATIONS Generic The values presented in the following table apply for all inputs and/or outputs unless specified oth- erwise. Specifically they are not influenced by the choice between CMOS or TTL levels. STLC60135
(All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device) IO Buffers Generic DC Characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit IIN Input Leakage Current V IN =V SS ,VDD no pull up / pull down -10 10 µA IOZ Tristate Leakage Current V IN =V SS ,VDD no pull up / pull down -10 10 µA IPU Pull up Current V IN =V SS -25 -66 -125 mA IPD Pull Down Current V IN =V DD 25 66 125 mA R PU Pull up Resistance V IN =V SS 50 K Ω R PD Pull Down Resistance V IN =V DD 50 K Ω IO Buffers Dynamic DC Characteristics Important for transient but measured at (near) DC Symbol Parameter Test Condition Min. Typ. Max. Unit C IN Input Capacitance @f = 1MHz 5 pF dl/dt Current Derivative 8mA driver, slew rate control 23.5 mA/ns 8mA driver, no slew rate control 89 -125 mA/ns Ipeak Peak Current 8mA driver, slew rate control 85 mA 8mA driver, no slew rate control 100 mA C OUT Output Capacitance (also bidirectional and tristate drivers) @f = 1MHz 7 pF Input / Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/or outputs unless specified otherwise. CMOS IO Buffers Generic Characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit V IL Low Level Input Voltage 0.2 x V DD V VIH High Level Input Voltage 0.8 x V DD V VHY Schmitt trigger hysteresis slow edge < 1V/ms, only for SCHMITx 0.8 V V OL Low Level Output Voltage I OUT = XmA* 0.4 V VOH High Level Output Voltage IOUT = XmA* 0.85 x V DD V * The reference current is dependen t on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA. Input/ Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified oth- erwise Symbol Parameter Test Condition Min. Typ. Max. Unit V IL Low Level Input Voltage 0.8 V VIH High Level Input Voltage 2.0 V VILHY Low Level Threshold, falling slow edge < 1V/ms 0.9 1.35 V VIHHY High Level Threshold, rising slow edge < 1V/ms 1.3 1.9 V VHY Schmitt Trigger Hysteresis slow edge < 1V/ms 0.4 0.7 V V OL Low Level Output Voltage I OUT = XmA* 0.4 V VOH High Level Output Voltage IOUT = XmA* 2.4 V * The reference current is dependen t on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA. STLC60135
PQFP144 PACKAGE MECHANICAL DATA DIM. mm inch A 4.07 0.160 A1 0.25 0.010 B 0.22 0.38 0.009 0.015 C 0.13 0.23 0.005 0.009 D3 22.75 0.896 e 0.65 0.026 E3 22.75 0.896 L1 1.60 0.063 K 0°(min.), 7°(max.) A A1B C 73108 109 144 E D e K B PQFP14 4 L Sea ting Plan e 0. 10mm .004 STLC60135
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics Tosca is trademark of STMicroelectronics 1999 STMicroelectronics and Alcatel Alsthom, Paris – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com STLC60135