STLC3055

STLC3055 STMICROELECTRONICS | Alldatasheet

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MONOCHIP SLIC OPTIMISED FOR WLL & ISDN-TA APPLICATIONS IMPLEMENT ALL KEY FEATURES OF THE BORSHT FUNCTION SINGLE SUPPLY (5.5 TO 15.8V) BUILT IN DC/DC CONVERTER CONTROL- LER. SOFT BATTERY REVERSAL WITH PRO- GRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR THRESHOLD METERING PULSE GENERATION AND FIL- TER INTEGRATED RINGING INTEGRATED RING TRIP PARALLEL CONTROL INTERFACE (3.3V LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT FEED SURFACE MOUNT PACKAGE INTEGRATED THERMAL PROTECTION -40 TO +85°C OPERATING RANGE

DESCRIPTION

The STLC3055 is a SLIC device specifically de- signed for WLL (Wireless Local Loop) and ISDN- Terminal Adaptors. One of the distinctive charac- teristic of this device is the ability to operate with a single supply voltage (from +5.5V to +15.8V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic for October 1999 D0 D1 D2 DET RTTX CAC ILTF RD IREF RLIM RTH CSVR CVCC VPOS BGND TIP RING VBA T AGND TX RX ZAC1 ZAC RS ZB CTTX1 CTTX2 FTTX CKTTX SUPERVISION TTX PROC AC PROC REFERENCE STAGE LINE DRIVER CREV INPUT LOGICAND DECODER OUTPUT LOGIC VOL T . Vcc Vss Agnd OUTPUT REG. Status and functions CLK RSENSE GATE VF DC/DC CONV. DC PROC Vbat BLOCK DIAGRAM TQFP44 ORDERING NUMBERS: STLC3055Q STLC3055QTR STLC3055 WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT

these applications is the integrated ringing gener- ator. The control interface is a parallel type with open drain output and 3.3V logic levels. The metering pulses are generated on chip start- ing from two logic signals (0, 3.3V) one define the metering pulse frequency and the other the me- tering pulse duration. An on chip circuit then pro- vides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external compo- nents. A dedicated cancellation circuit avoid pos- sible CODEC input saturation due to Metering pulse echo. Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is program- mable from 5mA to 9mA. The device, developed in BCD100II technology (100V process), operates in the extended tem- perature range and integrates a thermal protec- tion that sets the device in power down when Tj exceeds 140°C. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vpos Positive Supply Voltage -0.4 to +17 V A/BGND AGND to BGND -1 to +1 V Vdig Pin D0, D1, D2, DET, CKTTX -0.4 to 5.5 V Tj Max. junction Temperature 150 °C Vbtot (1) Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). 100 V (1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10) 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 N.C. RES PD CTTX2 CTTX1 CKTTX N.C. DET RTTX FTTX RX ZAC1 RS ZAC ZB CAC TX VF CLK VBAT1 CREV N.C. TIP N.C. N.C. N.C. RING N.C. VBAT BGND RLIM AGND CVCC RSENSE GATE VPOS CSVR ILTF RD IREF RTH D97TL279A 12 13 14 15 16 PIN CONNECTION DESCRIPTION (continued) STLC3055

Symbol Parameter Value Unit R th j-amb Thermal Resistance Junction to Ambient Typ. 60 °C/W PIN DESCRIPTION N. Name Function 25 VPOS Positive supply input ranging from 5.5V to 15.8V. 34 BGND Battery Ground, must be shorted with AGND. 27 AGND Analog Ground, must be shorted with BGND. 16 ZAC AC impedance synthesis. 15 ZAC1 RX buffer output, the AC impedance is connected from this node to ZAC. 17 RS Protection resistors image (the image resistor is connected from this node to ZAC).

18 ZB Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this

node to AGND. ZA impedance is connected from this node to ZAC1). 20 TX 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. 14 RX 4 wire input port (RX input); 300K Ω input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. 19 CAC AC feedback input, AC/DC split capacitor (CAC). 32 ILTF Transversal line current image output. 41 TIP 2 wire port; TIP wire (Ia is the current sourced from this pin). 37 RING 2 wire port; RING wire (Ib is the current sunk into this pin). 28 RLIM Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and PCB layout should avoid noise injection on this pin. 30 RTH Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and PCB layout should avoid noise injection on this pin. 29 IREF Internal bias current setting pin. RREF should be connected close to this pin and PCB layout should avoid noise injection on this pin. 43 CREV Reverse polarity transition time control. One proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the ”trapezoidal ringing” during ringing injection. 31 RD DC feedback and ring trip input. RD should be connected close to this pin and PCB layout should avoid noise injection on this pin. OPERATING RANGE Symbol Parameter Value Unit Vpos Positive Supply Voltage 5.5 to +15.8 V A/BGND AGND to BGND -100 to +100 V Vdig Pin D0, D1, D2, DET, CKTTX, PD -0.25 to 5.25 V Top Ambient Operating Temperature Range -40 to +85 °C Vbat (1) Self Generated Battery Voltage -74 max. V (1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10) STLC3055

for WLL and ISDN-TA applications. ISDN-TA design requirements. ling and transmission functions. carried out on the DET pin (active low). interfacing with both 3.3V and 5V logic levels. Table 1. SLIC operating modes. TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0. 26 CVCC Internal positive voltage supply filter. 23 GATE Driver for external Power MOS transistor. 21 VF Feedback input for DC/DC converter controller. internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. pin. The PCB layout should minimize the extra resistance introduced by the copper tracks. 1 D0 Control Interface: input bit 0. 2 D1 Control Interface: input bit 1. 3 D2 Control interface: input bit 2. 8 DET Logic interface output of the supervision detector (active low). 33 CSVR Battery supply filter capacitor. 12 RTTX Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used should be left open. 13 FTTX Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering. 10 CTTX1 Metering burst shaping external capacitor. 11 CTTX2 Metering burst shaping external capacitor. 9 CKTTX Metering pulse clock input (12 KHz or 16KHz square wave). 44 VBAT1 Frame connection. Must be shorted to VBAT. 5 RES Reserved, must be connected to AGND.

with an external CLK (125KHZtyp.). age current consumption from Vpos < 700mA. age is set to a predefined value. is selected this value is increased to -70V typ. mising in this way the power dissipation. fore the off-hook condition cannot be detected. thermal overload (Tj > 140°C). crease under the hysteresis threshold. to the self generated battery voltage (-50V typ). value as programmed in ACTIVE mode. vides both DC feeding and AC transmission. transmission; the self generated Vbat is -50V typ. equal to the protection resistors 2xRp (typ. the typical DC characteristic in ACTIVE mode. Figure 1. DC Characteristicin HI-Z Mode.

shaping by the capacitor CS. first, second and third order filters (see fig.4). related to the simple first order filter. TIP/RING pins at the TTX frequency. ferred from the line to the TX output. to get differentcrest factor values. Required external components vs. filter order. Figure 4. Metering pulse generation circuit.

1 X 13%

2 XXXX 6 %

A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground con- nection and in this case the star configuration al- lows surely to avoid possible problems (see Appli- cation Diagram Fig. 7). The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point PGND. This point should show a resis- tance as low as possible, that means it should be a ground plane. Noise sources can be identified in not enough good grounds, not enough low impedance sup- plies and parasitic coupling between PCB tracks and high impedance pins of the device. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: decoupling the center of the star from the ana- log ground of STLC3055 using small chokes. adding a capacitor in the range of 100nF be- tween VPOS and AGND in order to filter the switch frequency on VPOS. External Components List In order to properly define the external compo- nents value the following system parameters have to be defined: The AC input impedance shown by the SLIC at the line terminals ”Zs” to which the return loss measurement is referred. It can be real (typ. 600Ω ) or complex. The AC balance impedance, it is the equiva- lent impedance of the line ”Zl” used for evalu- ation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The line impedance at the TTX frequency ”Zlttx”. The metering pulse level amplitude measured at line termination ”V LOTTX ”. In case of low or- der filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency compo- nent. (typ 12 or 16KHz). Pulse metering envelope rise and decay time constant ”τ”. The slope of the ringing waveform ”ΔVTR /ΔT ”. The value of the constant current limit current ”Ilim”. The value of the off-hook current threshold ”ITH ”. The value of the ring trip rectified average threshold current ”IRTH ”. The value of the required self generated nega- tive battery ”VBATR ” in ring mode (max value is 70V). This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak sunk from Vpos ”IPK”. STLC3055

Name Function Formula Typ. Value RREF Bias setting current RREF = 1.3/Ibias Ibias = 50µA 26kΩ 1% CSVR Negative Battery Filter CSVR = 1/(2 π ⋅fp⋅1.8MΩ ) fp = 50Hz 1.5nF 10% 100VL RD Ring Trip threshold setting resistor RD = 100/IRTH 2KΩ <R D<5 K Ω 4.12kΩ 1% @ IRTH = 24mA CAC AC/DC split capacitance 22 µF 20% 15VL @ RD = 4.12kΩ RP Line protection resistor Rp > 30 Ω 41Ω 1% RS Protection and series switches resistance image RS = 100⋅(Rp + 9Ω )5 k Ω @R p=4 1 Ω ZAC Two wire AC impedance ZAC = 50 ⋅(Zs - 2Rp - 18Ω ) 25k Ω 1% @ Zs = 600Ω ZA (1) SLIC impedance balancing network ZA = 50⋅Zs 30k Ω 1% @ Zs = 600Ω ZB (1) Line impedance balancing network ZB = 50⋅Zl 30k Ω 1% @ Zl = 600Ω CCOMP AC feedback loop compensation CCOMP = 1/(2 π⋅fo⋅100⋅(RP+9Ω )) fo = 250kHz 120pF 10% 10VL @R p=4 1 Ω CH Trans-Hybrid Loss frequency compensation CH = CCOMP 120pF 10% 10VL RLIM Current limiting programming RLIM = 1300/Ilim 32.5kΩ < RLIM < 65kΩ 52.3kΩ 1% @ Ilim = 25mA RTH Off-hook threshold programming (ACTIVE mode) RTH = 260/ITH 27kΩ < RTH < 52kΩ 28.7kΩ 1% @I TH = 9mA CREV Reverse polarity transition time programming CREV = (1/3750)⋅Δ T/Δ VTR ) 22nF 10% 10V @ 12V/ms RTTX (3) Pulse metering cancellation resistor RTTX = 50Re[(Zlttx+2Rp+18Ω )] 15k Ω @Zlttx = 200Ω real CTTX (3) Pulse metering cancellation capacitor CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]} 100nF 10% 10V (2) @ Zlttx = 200Ω real RLV Pulse metering level resistor RLV = 63.3 ⋅103⋅α ⋅VLOTTX α = (|Zlttx + 2Rp + 18Ω |/|Zlttx|) 27kΩ 1% @V LOTTX = 275mVrms CS Pulse metering shaping capacitor CS = τ/(2⋅RLV) 100nF 10% 10V @ τ = 6ms, RLV = 27.1kΩ CFL Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV) 1nF 10% 10V @fttx = 12kHz RLV = 27kΩ RDD Pull up resistors 100k Ω CVCC Internally supply filter capacitor 100nF 20% 10V CVpos Positive supply filter capacitor with low impedance for switch mode power supply 100µF(4) CV Battery supply filter capacitor with low impedance for switch mode power supply 100µF 20% 100V (5) CVB High frequency noise filter 470nF 20% 100VL STLC3055

Name Function Formula Typ. Value CRD (6) High frequency noise filter 100nF 10% 15VL Q1 DC/DC converter switch P ch. MOS transistor RDS(ON) ≤1.2Ω ,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA Possible choiches: IRF9510 or IRF9520 or IRF9120 or equivalent D1 DC/DC converter series diode Vr > 100V, t RR ≤ 50ns SMBYW01-200 or equivalent RSENSE DC/DC converter peak current limiting RSENSE = 100mV/IPK 110m Ω @I PK = 900mA L (8) DC/DC converter inductor DC Resistance ≤ 0.1Ω (9) L=125 µH RFP1304PV (Manuf.: All Inductive) or SUMIDA CDRH125 or equivalent CF1 DC/DC converter feedback loop stability 220pF to 470pF (10) RF1 Negative battery programming level 250KΩ <RF1<300K Ω (7) 300kW 1% @V BATR = -70V RF2 Negative battery programming level 9.1kΩ 1% (1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. (2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz). (3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp+18Ω ). (4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (5) For low ripple application use 2x47µF in parallel. (6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows: 267kΩ 280kΩ 294kW 300k Ω VBAT(ACTIVE) -46V -48V -49V -50V VBATR(RING) -62V -65V -68V -70V VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration. (8) Core: MICROMETALS T50-26C IRON POWDER, AL-VALUE 61nH/N2 Current rating: 2A (50/60Hz) Operating Temperature -25° to +60° Centigrades Inductance: 14µH +/-15% at 1KHz, 1mA DC resistance of winding: MAX.100 mOhm Code: RFY1303 Wire: UEW2, 0,60 mm Turns: 50 Inductance (f=1KHz): >125µH (9) For high efficiency in HI-Z mode coil resistance @125kHz must be <3ohm (10) Function of this capacitor is to introduce a zero at the resonance frequency for loop stability. In case some parasitic resistance are already present in the loop (Coil, CVBAT, PCB layout), the presence of this capacitor can degrade the device noise performances; in this case CF1 should be removed being the loop stability already guaranteed by the parasitic resistance. EXTERNAL COMPONENTS (continued) STLC3055

ELECTRICAL CHARACTERISTICS

Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb =2 5°C. External componentsas listed in the ”Typical Values” column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the oper- ating range: -40 to +85°C. DC CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) Tamb = 0 to 85°C 44 50 V Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) Tamb = -40 to 85°C 42 48 V Vloa Line voltage Il = 0, ACTIVE Tamb = 0 to 85°C 33 40 V Vloa Line voltage Il = 0, ACTIVE Tamb = -40 to 85°C 31 37 V Ilim Lim. current programming range ACTIVE mode 20 40 mA Ilima Lim. current accuracy ACTIVE mode. Rel. to programmed value 20mA to 40mA -10 10 mA Rfeed HI Feeding resistance HI-Z (High Impedance feeding) 2.4 3.6 k Ω Zrx RX port input impedance 280 k Ω AC CHARACTERISTICS L/T Long. to transv. (see Appendix for test circuit) Rp = 41Ω , 1% tol., ACTIVE N. P., RL = 600Ω (*) f = 300 to 3400Hz 48 50 dB T/L Transv. to long. (see Appendix for test circuit) Rp = 41Ω , 1% tol., ACTIVE N. P., RL = 600Ω (*) f = 300 to 3400Hz 40 45 dB T/L Transv. to long. (see Appendix for test circuit) Rp = 41Ω , 1% tol., ACTIVE N. P., RL = 600Ω (*) f = 1kHz 48 53 dB 2WRL 2W return loss 300 to 3400Hz, ACTIVE N. P., RL = 600Ω (*) 22 26 dB THL Trans-hybrid loss 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., RL = 600Ω (*) 30 dB Ovl 2W overload level at line terminals on ref. imped. ACTIVE N. P., RL = 600Ω (*) 10 dBm TXoff TX output offset ACTIVE N. P., R L = 600Ω (*) -150 150 mV G24 Transmit gain abs. 0dBm @ 1020Hz, ACTIVE N. P., RL = 600Ω (*) -6.4 -5.6 dB G42 Receive gain abs. 0dBm @ 1020Hz, ACTIVE N. P., RL = 600Ω (*) -0.4 0.4 dB G24f TX gain variation vs. freq. rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., R L = 600Ω (*) -0.12 0.12 dB STLC3055

Symbol Parameter Test Condition Min. Typ. Max. Unit G42f RX gain variation vs. freq. rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600Ω (*) -0.12 0.12 dB V2Wp Idle channel noise at line psophometric filtered ACTIVE N. P., RL = 600Ω (*) Tamb = 0 to +85°C -73 -68 dBmp V2Wp Idle channel noise at line psophometric filtered ACTIVE N. P., RL = 600Ω (*) Tamb = -40 to +85°C -68 dBmp V4Wp Idle channel noise at line psophometric filtered ACTIVE N. P., RL = 600Ω (*) Tamb = 0 to +85°C -75 -70 dBmp V4Wp Idle channel noise at line psophometric filtered ACTIVE N. P., RL = 600Ω (*) Tamb = -40 to +85°C -75 dBmp Thd Total Harmonic Distortion ACTIVE N. P., R L = 600Ω (*) -46 dB VTTX Metering pulse level on line ACTIVE - TTX Zl = 200Ω fttx = 12kHz 200 250 mVrms CLKfreq CLK operating range -10% 125 10% kHz RING Vring Line voltage RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF T amb = 0 to +85°C 45 49 Vrms Vring Line voltage RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF T amb = -40 to +85°C 44 48 Vrms DETECTORS IOFFTHA Off/hook current threshold ACT. mode, RTH = 28.7k Ω 1% (Prog. ITH = 9mA) 10.5 mA ROFTHA Off/hook loop resistance threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 3.4 k Ω IONTHA On/hook current threshold ACT. mode, RTH = 28.7k Ω 1% (Prog. ITH = 9mA) 6m A RONTHA On/hook loop resistance threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 8k Ω IOFFTHI Off/hook current threshold Hi Z mode, RTH = 28.7k Ω 1% (Prog. ITH = 9mA) 10.5 mA ROFFTHI Off/hook loop resistance threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 800 Ω IONTHI On/hook current threshold Hi Z mode, RTH = 28.7k Ω 1% (Prog. ITH = 9mA) 6m A RONTHI On/hook loop resistance threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 8k Ω ELECTRICAL CHARACTERISTICS (continued) (*) RL: Line Resistance STLC3055

Symbol Parameter Test Condition Min. Typ. Max. Unit Irt Ring Trip detector threshold range RING 20 50 mA Irta Ring Trip detector threshold accuracy RING -15 15 % Trtd Ring trip detection time RING TBD ms Td Dialling distortion ACTIVE -1 1 ms Rlrt (1) Loop resistance 500 Ω ThAl Tj for th. alarm activation 160 °C DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET Vih In put high voltage 2 V Vil Input low voltage 0.8 V Iih Input high current -10 10 µA Iil Input low current -10 10 µA Vol Output low voltage Iol = 1mA 0.45 V PSRR AND POWER CONSUMPTION PSERRC Power supply rejection Vpos to 2W port Vripple = 100mVrms 50 to 4000Hz 26 36 dB Ivpos Vpos supply current @ ii = 0 HI-Z On-Hook ACTIVE On-Hook, RING (line open) 120 115 140 mA mA mA Ipk Peak current limiting accuracy RING Off-Hook RSENSE = 110m Ω -20% 950 +20% mApk ELECTRICAL CHARACTERISTICS (continued) (1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection. STLC3055

Referring to the application diagram shown in fig. 7 of the STLC3055 datasheet and using as external components the Typ. Values specified in the ”External Components” Table (page 13) find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using ”Wandel & Goltermann DC Loop Holding Circuit GH-1” or equivalent. TIP RING RX TX STLC3055 application circuit W&G GH1 Zref E Vs 1Kohm 1Kohm 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm 100µF Figure A1. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs) TIP RING RX TX STLC3055 application circuit W&G GH1 Vrx Vtx100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm Figure A2. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx| STLC3055

W&G GH1 E Vtx100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm Figure A3. G24 Transmit Gain G24 = 20Log|2Vtx/E| TIP RING RX TX STLC3055 application circuit W&G GH1 Vrx Vl 100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm Figure A4. G42 Receive Gain G42 = 20Log|VI/Vrx| TIP RING RX TX STLC3055 application circuit W&G GH1 Vl 100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm Vn VPOS Figure A5. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl| STLC3055

W&G GH1 Vcm Vl 100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 300ohm 100µF 300ohm 100µF Impedan ce match ing better than 0.1% Figure A6. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl| 600ohm TIP RING RX TX STLC3055 application circuit Vcm W&G GH1 100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 300ohm 100µF 300ohm 100µF Impedancematching better than 0.1% Vrx Figure A7. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm| TIP RING RX TX STLC3055 application circuit fttx (12 or 16kHz) Vlttx 200ohm CKTTX Figure A8. VTTX Metering Pulse level on line STLC3055

W&G GH1 Vl psophometric filtered 100µF 100µF 100mA DC max Zin = 100K 200 to 6kHz 600ohm Vtx psophometric filtered Figure A9. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|;V4Wp = 20Log|Vtx/0.774l| APPENDIX B STLC3055 Overvoltage Protection TIP RING BGND VBA T RP1 RP2 RP1 RP2 RP2: Fuse or PTC SM4T39RX STLC3055 TIP RING Figure B1. Simplified configuration for indoor overvoltage protection TIP BGND VBA T RP1 RP2 RP2: Fuse or PTC SM4T39RX STLC3055 TIP RING RP1 RP2 RING LCP1511 Figure B2. Standard overvoltage protection configuration for K20 compliance STLC3055

TYPICAL STATE DIAGRAM FOR STLC3055 OPERATION Tj>Tth PD=0, D0=D1=0 PD=1, D0=D1=0 Power Down HI-Z Feeding Off Hook Detection Active Off Hook On Hook Detection for T>Tref Active On Hook Ringing Ring Burst D0=1, D1=0, D2=0/1 Ring Trip Detection Normally used for On Hook Transmission Ring Pause D0=0, D1=1, D2=0 Ring Burst Off Hook DetectionD0=0, D1=1, D2=0 On Hook Condition Note: all state transitions are under the microprocessor control. Figure C1. STLC3055

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