STLC1 STMICROELECTRONICS | Alldatasheet
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Technical content
■ FULLY MONOLITHIC FIXED FREQUENCY SMPS ■ THREE LOW SIDE DRIVERS FOR STOP TAIL AND TURN LED LAMPS ARRAYS DRIVING ■ PROGRAMMABLE LOW SIDE DRIVER OVER CURRENT LIMIT PROTECTION ■ UNDER CURRENT DIAGNOSTIC ■ INPUT OVERVOLTAGE PROTECTION ■ VERY LOW STAND-BY CURRENT ■ THERMAL PROTECTION WITH HYSTERESIS
DESCRIPTION
The STLC1, a device realized with the well established BCD technology, is a fixed frequency fully monolithic SMPS, with three independent smart low side driver, primarily intended for automotive rear led lamps driving. The output voltage is set using a simple resistor divider. Thermal shutdown with hysteresis, input over-voltage and overcurrent protections give robust design solutions. STLC1 LED LAMPS CLUSTER DRIVER ST -LTL -L TR -L TURN STOP TAIL OSCILLATOR PWM SWITCH CONTOLLER 1.24V THERMAL PROTECTION CNTL TS -PWM LAMP OUTAGE DETECT PULSE WIDTH CONTROLLER P-OU T TR -DRV REF FDBK ST -DRV TL -DRV REF GND LMP -OUT OSC COMP1 R s ERR AMP I N P U T PWM COMP SCHEMATIC DIAGRAM PowerSO-20 TM
CONNECTION DIAGRAM (top view) Symbol Parameter Value Unit VB+ Transient Supply Voltage (load dump) 60 V VB+ Operating Supply Voltage 24 V VTURN, VSTOP , VTAIL TURN, STOP and TAIL input pins voltage V B+ + 0.3 V ITURN, ISTOP , ITAIL TURN, STOP and TAIL pins current ± 10 mA ITR-DRV, ITL-DRV, IST-DRV TR-DRV, TL-DRV and ST-DRV pins sink current 1.5 A ILMP-OUT LMP-OUT pin sink current 120 mA VP-OUT P-OUT DC Voltage 60 V IP-OUT P-OUT pin sink current Internally Limited A Tstg Storage Temperature Range -55 to +150 °C TJ Operating Junction Temperature Range -40 to +125 °C Symbol Parameter PowerSO-20 TM Unit Rthj-case Thermal Resistance Junction-case 2 °C/W Rthj-amb Thermal Resistance Junction-Ambient 50 °C/W PowerSO-20 TM
ORDERING INFORMATION
Pin N° Symbol Name and Function
1 GND Ground
2 TR-DRV The Low Side Driver drain pin for the TURN LED array
3 TR-L The Low Side Driver source pin, used to detect either a lamp outage or an
over-current condition for the TURN LED array
4 ST-DRV The Low Side Driver drain pin for the STOP LED array
5 ST-L The Low Side Driver source pin, used to detect either a lamp outage or an
over-current condition for the STOP LED array
6 TL-DRV The Low Side Driver drain pin for the TAIL LED array
7 TL-L The Low Side Driver source pin, used to detect either a lamp outage or an
over-current condition for the TAIL LED array
8 CNTL Determines, according to a percentange of VREF, the Pulse Width Controller
internal oscillator duty cycle
9 REF Stable Reference Voltage
10 GND Ground
11 GND Ground
12 B+ Power Supply
13 TAIL TAIL input pin. When brought high, TAIL activates the IC and drives the TAIL led array. 14 STOP STOP input pin. When brought high, STOP activates the IC and drives the STOP led array. 15 TURN TURN input pin. When brought high, TURN activates the IC and drives the TURN led array.
16 FDBK Internal Error Amplifier Inverting Pin
17 P-OUT Power MOSFET drain pin
18 TS-PWM A Three State Input. It determine the control logic for TAIL and STOP Low Side Drivers.
19 LMP-OUT A weak pulled up signal during lamps No Fault condition and an active pulldown
when a Fault condition is detected.
20 GND Ground
TYPICAL APPLICATION CIRCUIT ELECTRICAL CHARACTERISTICS FOR SMPD SECTION (TJ=-40 to 125°C unless otherwise specified. Typical values are referred at TJ=25°C, VB+=14V) Symbol Parameter Test Conditions Min. Typ. Max. Unit VB+ Supply Operating Voltage Normal Operating Range 9 24 V Normal Operating Range - TAIL only 6 24 VSD B+ Input Overvoltage Shutdown 28 30 32 V ISQ Total Off State Quiescent Current VB+ =1 4 V , VTURN =V STOP =V TAIL =0V 120 180 µA fosc PWM Oscillator Frequency VB+ = 14V 140 180 240 kHz R P(on) Static drain to ground SMPS N-channel switch on resistance V B+ =9 V , IP-OUT =4A 180 m Ω V B+ =1 4 V , IP-OUT =4A 170 m Ω ID(off) P-OUT Off State leakage Current VB+ = 16V, 20 µA ILIMIT IP-OUT Current Limit V B+ =1 4 V , VFDBK = 1V 8 12 16 A tSMPS-ON SMPS Turn On Delay C REF =1 µF (see note 1,4 and Fig 1, 2) 1.6 ms VLOAD Load Regulation V B+ =1 4 V , IOUT = 0.6 to 3A V OUT =1 0 V 60 mV V LINE Line Regulation V B+ = 9 to 16V, IOUT = 1.5A V OUT =1 0 V 15 mV GND LMP-OUT TS-PWM P-OUT FDBK TURN STOP TAIL GND Iout TURNTAIL STOP RLR RLS RLT GND TR-DRV TR-L ST-DRV ST-L TL-DRV TL-L CNTL REF GND R TR R TS RTT RC1 RC2 C REF IP-OUT C SEPIC COUT OUT RF1 RF2
ELECTRICAL CHARACTERISTICS FOR LOW SIDE DRIVER SECTION (TJ=-40 to 125°C unless otherwise specified. Typical values are referred at TJ=25°C, VB+ =14V) Symbol Parameter Test Conditions Min. Typ. Max. Unit R (on) Static drain to source LSD N-channel switch on resistance VB+ =9 V , V TURN =V B+ VTR-L =0 V ITR-DRV =1A 500 m Ω VSTOP =V B+ VST-L =0 V IST-DRV =1A 500 m Ω VTAIL=V B+ VTL-L=0 V ITL-DRV =1A 500 m Ω ILSD(off) OFF State LSD’S leakage current VTURN =V STOP =V TAIL=0V V TR-DRV =V ST-DRV =V TL-DRV =V B+ 10 µA tLSD-ON LSD Turn On Delay C REF =1 µFC OUT = 220µF (see note 2,4 and Fig 1, 2) 2m s V LS-ON FDBK Voltage over which LSD’s are enabled 0.95VFB V VLS-OFF FDBK Voltage over which LSD’s are disabled 0.5VFB V fLSD Pulse Width Controller Internal Oscillator Frequency VTAIL=V B+ VTS-PWM =V REF /2 200 380 500 Hz VIN(ON) Input Threshold voltage to enable LSD VB+ = 9 to 16V 0.6VB+ V V IN(OFF) Input Threshold voltage to disable LSD VB+ = 9 to 16V 0.4VB+ V
ELECTRICAL CHARACTERISTICS FOR FEEDBACK AND CONTROL (TJ=-40 to 125°C unless otherwise specified. Typical values are referred at TJ=25°C, VB+ =14V) Note 1: The device is powered. If only one of the three inputs is enabled (the remaining inputs are shorted to ground), tSMPS-ON is the time required for the OUT voltage to reach the10% of its own steady state value Note 2: The device is powered. If only one of the three inputs is brought high (the remaining inputs are shorted to ground), TLSD-ON is the time required for the current to flow in the enabled LSD Note 3: The device is powered and at least one input is enabled. If this input is disabled, TLSD-OFF is the time required for the current to be- come zero in the previously enabled LSD. Note 4: Guaranteed by design, not tested in production. FUNCTIONAL DESCRIPTION SMPS The N-channel Power MOSFET is source grounded, thus it is possible to use any converter configuration with the power switch connected to ground. A SEPIC topology (Single Ended Primary Inductor Current) is shown in the typical application schematic. INPUTS PINS The IC’s inputs are TURN, STOP and TAIL. If all inputs are disabled, SMPS and most of the internal control and diagnostic circuitry are not active. This is done in order to maintain the stand-by quiescent current at very low values. When only one of these inputs is put high (e.g connected to V B+ ), a device start-up phase begins. First the CREF capacitor is charged and, once the voltage on it has reached about 95% of its steady state value (V REF ), the SMPS is enabled. In order to allow the output to reach the regulated voltage value faster, the LSD corresponding to the input enabled will conduct Symbol Parameter Test Conditions Min. Typ. Max. Unit VLOUT Lamp Outage Detect Threshold Voltage TJ=25°C 150 200 250 mV VH-SHORT Output Overcurrent Threshold Voltage TJ=25°C 1.2 1.3 1.6 V VREF External Voltage Reference VTURN =V STOP =V TAIL=V B+ IREF =5 0 0µA 3.6 3.8 4 V VFB Internal Band-gap Voltage Reference (see schematic diagram) V TURN =V STOP =VTAIL=V B+ 1.15 1.24 1.3 V V LH(en) Device Enabled Lamp Outage no fault High Voltage VB+ = 9 to 16V, ILMP-OUT <- 4 m A A t least one input enabled. No fault condition. VB+-2 V B+ V VLH(dis) Device Disabled Lamp Outage no fault High Voltage VB+ = 9 to 16V, ILMP-OUT <- 2 m A VTURN =V STOP =V TAIL=0 V VB+-2 V B+ V VLL Lamp Outage fault Low Voltage VB+ = 9 to 16V ILMP-OUT < 100mA At least one input enabled. Fault condition. 1.5 V R (IN) TURN, STOP and TAIL Input Resistance VB+ = 12V, 18.5 k Ω TSHDN Thermal Shutdown Threshold (see Note 4) 150 °C THYST Thermal Shutdown Hysteresis (see Note 4) 10 °C tF(on) Time to Fault Indication ON 60 µs tF(off) Time to Fault Indication OFF 8m s VTS-PWM(L) TS-PWM Low State Voltage (see table 1) 0.1VREF V VTS-PWM(M) TS-PWM Mid State Voltage (see table 1) 0.21VREF 0.79VREF V VTS-PWM(H) TS-PWM High State Voltage (see table 1) 0.98VREF V
only when the OUT voltage is about 95% of its final value. Such a start-up phase takes place when only one input is enabled. LOW SIDE DRIVER: The purpose of the low side drivers is to connect the LED cluster to ground, creating a path for the current. Using external resistors, current flowing into the LED cluster is set according to the following formula: where (see typical application schematic): R L =R LT,R LS,o rRLR R T =R TT,R TS ,o rRTR R (on)= Static drain to source LSD on resistance VOUT = Output Voltage VARRAY = Expected LED array voltage drop. LSD over-current protection and under-current diagnostic (see LAMP OUTAGE DETECTION section) is performed by sensing the voltage on resistors, when the corresponding LSD are enabled. If the voltage on exceeds V H-SHORT ,t h e over-current protection acts by reducing the LSD average current by switching ON and OFF the LSD itself. LAMP OUTAGE DETECTION Resistors are used to sense the LED array current. In case one or more LEDs fail (open circuit) the current on the corresponding resistor will drop due to the increased LED array resistance. As soon as the voltage drop on is lower than V LOUT , a LED lamp fault condition is detected and the LMP-OUT pin becomes active (low). The LAMP-OUTAGE functionality is AND-ed with each input, that is a fault condition can be detected only when the LED arrays are enabled. DIMMING The dimming of the LED lamps can be obtained by using the internal PULSE WIDTH controller (it drives the LSD TAIL and STOP gates). The duty cycle of this internal oscillator (whose frequency is 380Hz typical) can be set, forcing the voltage of t h eC N T Lp i nt ob eaf r a c t i o no fV REF ,b yu s i n ga simple resistor divider (as shown in the typical application scheme). In this case the duty cycle percentage can be calculated with the following approximated formula: The TS-PWM pin voltage, according to the TABLE1 determines which LSD is PULSE WIDTH CONTROLLER driven. Internal dimming can only be performed on the TAIL and STOP arrays. The TURN array can be externally dimmed (as well as TAIL and STOP) by driving the corresponding input witha a square pulse signal whose maximum frequency must be 200Hz. I ARRAY V OUT V ARRAY– DC% 3.8 if R C1 V REF R C1
Figure 1 :Start-up phase and input signal timing diagram (with TS-PWM floating) TYPE INPUTS ACTIVATED DRIVE TYPE TAIL ARRAY STOP ARRY LOW (VTS-PWM <0.1VREF ) TAIL PWM PWM STOP OFF ON TAIL AND STOP PWM ON MID (VTS-PWM <0.1VREF /2 or floating) TAIL PWM OFF STOP OFF ON TAIL AND STOP PWM ON HIGH (VTS-PWM >0.98VREF ) TAIL PWM PWM STOP ON ON TAIL AND STOP ON ON
L1, L2 VK200 C4, C5, C6 22 µF-35V Electrolytic Capacitor Low ESR C16 220nF-35V Ceramic Capacitor X7R Dielectric C7 47 µF-35V Electrolytic Capacitor C1, C2 4.7nF-35V Ceramic Capacitor X7R Dielectric C8, C9 220 µF-35V Electrolytic Capacitor Low ESR C14 560pF C18 560pF-50V C11 1 µF-35V Tantalium Capacitor C12 220pF Ceramic Capacitor R10 9.1k Ω Resistor 125mW 0.1% R11 1.3k Ω Resistor 125mW 0.1% R15 4.7k Ω Resistor 125mW 5% R16 56 Ω Resistor 125mW 5% R18 10 Ω Resistor 250mW 5% R12, R13, R14 1.2k Ω Resistor 125mW 5% R4, R6, R8 2.2 Ω Resistor 1W 5% R5, R7, R9 1 Ω Resistor 1W 5% TR1 10k Ω Trimmer RLP 1.5k Ω Resistor 125mW 5% D1 Schottky Diode STPS3L40S DLP Led Diode T1 SEPIC inductor, Toroid Horizontal THT 20 µH@10ADC, 200-250KHz JP1, JP2, JP3 Jumper
DIM. mm. inch A 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039 b 0.40 0.53 0.0157 0.0209 c 0.23 0.32 0.0090 0.0013 D (1) 15.80 16.00 0.6220 0.630 E 13.90 14.50 0.5472 0.5710 e 1.27 0.0500 e3 11.43 0.4500 E1 (1) 10.90 11.10 0.4291 0.4370 E2 2.90 0.1141 G 0 0.10 0.0000 0.0039 h 1.10 0.0433 L 0.80 1.10 0.0314 0.0433 N0 ˚ 1 0 ˚ S0 ˚ 8 ˚0 ˚ 8 ˚ T 10.0 0.3937 PowerSO-20 MECHANICAL DATA 0056635 e a2 A E PSO20MEC DETAILA T D 11 0 1120 E1E2 hx45˚ DETAILAlead sluga3 S Gage Plane 0.35 L DETAILB R DETAILB (COPLANARITY) GC -C- SEATING PLANE b c NN (1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)
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