STLBC01 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 General description
- 2 Block diagram
- 3 Typical application diagram and pin description
- 4 Electrical
- 4.1 Absolute maximum ratings
- 4.2 Handling procedures
- 4.3 General operating conditions
- 4.4 Electrical characteristics
- 4.4.1 Current consumption
- 4.5 I/O characteristics
- 4.6 RF characteristics
- 4.7 Timing characteristics
- 5 Functional description
- 5.1 STBLC01 startup
- 5.1.1 Startup
- 5.1.2 End of the boot-up procedure
- 5.2 STBLC01 power modes
- 5.2.1 Standby mode
- 5.2.2 Xtreme mode
- 5.2.3 OFF mode
- 5.3 STBLC01 functional modes
- 5.3.1 State diagram
- 5.3.2 Idle mode
- 5.3.3 Sleep mode
- 5.3.4 Off mode
- 5.3.5 BLE active
- 5.3.6 BLE sleep (only for SPI transport layer)
- 5.4 STBLC01 reset structure
- 6 Host controller interface (HCI)
Datasheet sections
- 9.5 STBLC_POWER_MODE-CONFIGURATION
- 9.5.3 Returned events for STBLC_POWER_MODE-CONFIGURATION
- 9.6 STBLC_SET_UART_BAUD_RATE
- 9.6.1 Command parameters for STBLC_SET_UART_BAUD_RATE
- 9.6.2 Return parameters for STBLC_SET_UART_BAUD_RATE
- 9.6.3 Returned events for STBLC_SET_UART_BAUD_RATE
- 10 Vendor HCI events
- 10.1 STBLC_POWER_MODE_IDLE
- 10.1.1 Event parameters
- 10.2 Hardware error event codes
- 11 Related documents
- 12 Package mechanical data
- 13 Revision history
Features
- Bluetooth specification v4.0 compliant master and slave BLE controller
- Bluetooth protocol stack for STM32L and profiles provided separately
- Operating supply voltage from 1.9 to 3.6 V
- 13 mA maximum peak current allows standard coin cell battery usage
- Low power physical layer
- Link layer with embedded security engine
- UART and SPI available as HCI transport layers
- SPI interface allows proprietary low power mode to further reduce the power consumption
- ISM 2.4 GHz frequency band
- 1 Mbps on-air data rate
- Wide spread and low cost 26 MHz Xtal
- 200 Ω differential impedance of antenna port
- Very small number of external discrete components
- Programmable output power from -18 dBm to +3 dBm
- Digital RSSI
- Power management with integrated linear regulator
- Battery level detector function to keep control of the battery level detection
- Compliant with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15, ARIB STD-T66
- QFN 24 5x5 mm RoHS package
- Operating temp. range from -40 °C to 85 °C
Applications
- Watches
- Fitness, wellness and sports
- Consumer medical
- Security/proximity
- Remote control
- Remote sensing
- Home and industrial automation
- Assisted living
- Mobile phone peripherals
- PC peripherals
Description
The STBLC01 is a very low power Bluetooth low energy (BLE) controller compliant with Bluetooth specification 4.0. The STBLC01 integrates a low power physical layer, a link layer with an embedded security engine, a host controller interface (HCI), and a power management. The STBLC01 allows the meeting of the tight advisable peak current requirements imposed by the use of standard coin cell batteries, and even in worst-case operating conditions 13 mA is the maximum current that is drawn from the input voltage source. Yet ultra low power sleep modes and very short transition time between operating modes allow a very low average current consumption to be achieved, which results in longer battery life. The STBLC01 offers the possibility of interfacing with several external microcontrollers using either UART or SPI as the transport layer for HCI communications. VFQFPN 24L Table 1. Device summary
1 General description
simplified application schematic is shown in Figure 2. Figure 1. BLE stack Figure 2. Simplified application diagram the STM32L. BLE qualified profiles are available separately. optimize the current consumption for a wide set of applications.
adaptation of antenna impedance to the STBLC01 differential 200 Ω real impedance.
2 Block diagram
A simplified block diagram of the STBLC01 is shown in Figure 3. Figure 3. Simplified block diagram
3 Typical application diagram and pin description
Figure 4. Suggested application schematic
Figure 5. STBLC01 pinout top view Table 2. External components of the typical application diagram
Table 3. STBLC01 pinout description
1 UART_TX / SPI_MISO Digital output UART TX / SPI data output (SDO)
2 UART_RX / SPI_MOSI Digital input UART RX / SPI data input (SDI)
3 SPI_CLK Digital input SPI clock input (SCK)
4 VDD Power Positive supply for the digital part
- For proper operation of the chip, this terminal must not be loaded by any external circuitry.
5 AVSS Ground Negative supply for the digital part (2)
- For proper operation of the chip, this term inal must be connected to a common ground plane.
6 AVSS1 Ground Ground (2)
7 AVSS2 Ground Ground (2)
8 AVSS3 Ground Ground (2)
9 VBAT Analog Ground (2)
10 WU/CSN Digital input UART wake up from sleep/off mode / SPI chip
11 SEL Digital input Interface selection (0 = UART, 1 = SPI).
12 AVSS_PLL2 Ground Negative supply of PLL (2)
13 AVDD_PA Power Regulated output voltage for the power amplifier (1)
14 AVSS_PA Ground Negative supply for the power amplifier (2)
15 ANTN RF
16 ANTP RF
17 AVSS_RF Ground Negative supply of RF part (2)
18 VCC Power Main supply for the chip
19 BIAS_R Analog Pin for bias setting resistor
20 AVSS_PLL1 Ground Negative supply of PLL
21 XTAL1 Analog
22 XTAL2 Analog
23 RST Digital input Reset
24 IRQ Digital input SPI interrupt request
4 Electrical
4.1 Absolute maximum ratings
soldering conditions are specified as in the JEDEC J-STD-020C standard.
4.2 Handling procedures
4.3 General operating conditions
The general operating conditions for both STBLC01 versions are summarized in Table 5. Table 4. Absolute maximum ratings Table 5. STBLC01 general operating conditions
4.4 Electrical characteristics
4.4.1 Current consumption
This section summarizes the estimated current consumption of the STBLC01 at pin VCC. are defined in Section 5.3. Unless otherwise specified, the voltage VCC is set to 2.5 V.
4.5 I/O characteristics
This section summarizes the I/O characteristics.
4.6 RF characteristics
exceptions for some parameters are compliant to that described in [2], volume 6, part A. Table 6. Typical current consumption Table 7. I/O characteristics
Table 8. General RF characteristics
- Frequency accuracy includes initial tolerance, stab ility over temperature range and aging of the quartz.
Table 9. Transmitter characteristics
- Frequency deviation corresponding to a 10101010 sequence is at least 80% of the frequency deviation
- Measuring conditions and signal s pecifications are described in [3], [4] and [5]. These parameters are
highly related to a correct matching network and PCB design. Refer to Section 8 for design guidelines.
4.7 Timing characteristics
Table 10. Receiver characteristics
- Measuring conditions and signal s pecifications are described in [3], [4] and [5]. These parameters are
highly related to a correct matching network and PCB design. Refer to Section 8 for design guidelines. Table 11. Timing characteristics
- This time is dominated by the Xtal oscillator startup.
- This time is dominated by the Xtal oscillator startup.
Functional description STLBC01
5 Functional description
5.1 STBLC01 startup
This section describes the STBLC01 startup procedure. The description is intended to be informational only, as it is independent of any external actions. That application does however select the preferred communication interface by setting the pin SEL (a) (SEL = 1 SPI, SEL = 0 UART).
5.1.1 Startup
When a 3 V battery is connected to the STBLC01, an internal RC oscillator starts up, providing a clock with fixed duty-cycle to the power check circuit. After the power check indicates enough voltage on VDD, the Xtal oscillator is enabled and when its startup procedure is completed, the main logic can use the Xtal clock as reference.
5.1.2 End of the boot-up procedure
Once the XTAL oscillator clock is available to the digital part of the controller, the STBLC01 enters idle state and an event is sent to the host through the selected communication interface. Refer to Section 6 for a complete description of how to send commands and read events from the STBLC01. At the end of the boot sequence, the STBLC01 returns an event STBLC_POWER_MODE_IDLE to the host to notify that the system has entered in Idle mode. If for any reason the first HCI event is corrupted after start-up, for example if the host needs a long time to initialize or if the SEL signal is not stable at start-up time, it is recommended that the host generates an additional reset to ensure a proper start-up.
5.2 STBLC01 power modes
The STBLC01 can be configured to work in three main power modes which are automatically chosen based on the selected chip state described in Section 5.3. These modes are, however, not directly selectable by application. For this reason this section is intended to be informational.
5.2.1 Standby mode
In this mode the Xtal is up and running and is the main clock source of the system. The internal RC oscillator is active.
5.2.2 Xtreme mode
In Xtreme mode, the Xtal oscillator is turned off but the internal RC is kept on. The supply voltage of the logic is lowered to reduce the effect of leakage. The complete controller status is kept. a. In order to avoid issues at boot-up due to interface selection, it is advisable to pull up (SPI) or pull down (UART) the pin SEL with a 10 kΩ.
STLBC01 Functional description
5.2.3 OFF mode
In this mode, all internal oscillators are off. The supply voltage of the logic is lowered to reduce the effect of leakage. The complete controller status is kept.
5.3 STBLC01 functional modes
5.3.1 State diagram
This part describes in which modes the STBLC01 can operate and how to switch from one mode to another. Figure 6 shows a simplified state diagram of the STBLC01. The arrows indicate how the transaction from one state to the other can be achieved. Note that some operations in some states are only allowed for HCI over SPI transport layer, some others are achieved only by firmware. As described in Section 5.1, after this initial step, the STBLC01 automatically enters Idle mode. Change of state is allowed through the HCI commands. In Section 4.7 the time required to switch from one state to the other is defined.
Figure 6. STBLC01 state diagram
5.3.2 Idle mode
internal logic is in Halt mode, waiting for a HCI command from the host.
5.3.3 Sleep mode
STLBC01 Functional description is exited, the STBLC01 goes into Idle mode. The HCI system is available but with limited functionality depending on the transport layer chosen:
- If UART has been chosen as transport layer, no HCI commands are accepted. The system can be woken up by setting the pin WU to high. Once this is done, the system restarts all internal oscillators and automatically goes into idle state asserting the STBLC_POWER_MODE_IDLE event.
- If SPI has been chosen as the transport layer, the STBLC01 is capable of executing a limited set of HCI commands with a limited speed. In particular, all commands which enable RF communications are not allowed in this mode. The flow control described in Section 6.2.2 ensures that no overflow occurs in the communication. The HCI command STBLC_SET_POWER_MODE can be used to go into Standby mode.
5.3.4 Off mode
Off mode is the lowest STBLC01 power consumption mode. The power mode for this configuration is OFF as defined in Section 5.2.3. RF cannot be activated from this state. The HCI system is available but only to wake up the system. No HCI commands are accepted. When the system wakes up, the default mode is Idle. Depending on the transport layer chosen, the system can be woken up as follows:
- If UART has been chosen as the transport layer, the system can be woken up by setting the WU pin to '1'. Once this is done, the system restarts all internal oscillators and automatically goes into idle state, asserting the STBLC_POWER_MODE_IDLE event.
- If SPI has been chosen as the transport layer, the system can be woken up by sending any HCI command. Only a limited set of HCI commands are supported in this mode and with limited speed. In particular, all commands which enable RF communications are not allowed in this mode. Once the command has been received, the STBLC01 switches automatically in Sleep mode and tries to execute the command. The command STBLC_SET_POWER_MODE can be used to either go into Idle or into Off mode. In the first case the system restarts all internal oscillators and automatically goes into idle state asserting the STBLC_POWER_MODE_IDLE event. In the second case no special HCI event is sent but the STBLC01 returns in Off mode.
5.3.5 BLE active
BLE active is the mode where the STBLC01 is able to communicate to other BLE devices. This mode can be entered only from Idle mode. This mode represents the starting state for any Bluetooth low energy operation (scanning, advertisement, connection). The power mode for this configuration is Standby, as defined in Section 5.2.1. The HCI system is available and the host can communicate with the controller using the selected transport layer. HCI is able to receive and decode any command sent by the host as well as send any event back to the host using either UART or SPI transport layers, according to the value of the SEL pin. Xtal is the clock source of STBLC01 logic. Internal RC is calibrated during this phase. The RF core can be activated and controlled in order to optimize power consumption. The internal logic is in Halt mode, waiting for a HCI command from the host. In order to avoid possible noise coupling, it is highly recommended to reduce the host- controller communications when the on-air link is active.
Functional description STLBC01
5.3.6 BLE sleep (only for SPI transport layer)
BLE sleep mode is a special low power mode available only when the SPI transport layer is used. This mode can be enabled by the HCI command. The STBLC01 offers two possible configurations for this mode: one employing the Xtal oscillator and another using the RC oscillator. When the Xtal oscillator is used, the high precision of the Xtal allows the STBLC01 to act as a master, slave, advertiser or scanner device. When the STBLC01 is a slave, advertiser or scanner device, the RC oscillator can be chosen, and the power consumption can be significantly reduced because the Xtreme power mode is used in that case. The STBLC01 controls automatically the transitions between BLE Active and this mode; the host cannot influence them directly. The use of the RC oscillator can be enabled using the HCI command STBLC_POWER_MODE_CONFIGURATION. In this configuration, the RF core is turned off and the HCI system is active and able to receive any command.
- If UART has been chosen as transport layer, only the Xtal oscillator can be selected.
- If the transport layer is SPI, the Xtal oscillator or the RC oscillator can be selected.
5.4 STBLC01 reset structure
The STBLC01 has the following reset sources: 1. Power On Reset (POR). This occurs after each power-up of the STBLC01. Once the boot-up procedure described in Section 5.1 is completed, an STBLC_POWER_MODE_IDLE event is reported to the host, indicating that the STBLC01 has entered Idle mode. During POR, the RST pad is pulled to logic 0. 2. RST pad. The host can reset the STBLC01 by pulling up the RST pin for at least 5 ms. In this situation the STBLC01 reboots the firmware and an event STBLC_POWER_MODE_IDLE is sent as soon as the STBLC01 has entered Idle mode. The RST pad is pulled to logic 0 during POR. 3. HCI reset. Sending the standard BT command HCI_RESET, the host can reset the BLE functions of the STBLC01 as described in [2].
6 Host controller interface (HCI)
The STBLC01 includes a host controller interface as defined in [2], volume 2; part E. information can be found in [2]. Table 12. HCI command format
4 Parameter_Total_Le
Table 13. HCI ACL data format 4 Data_Total_Length 2 Length of data measured in octets.
list of supported proprietary HCI commands is available in Section 7.
- SEL = 0: UART interface as defined in [ 2], volume 4, part A.
- SEL = 1: SPI interface with proprietary flow control.
6.1 HCI UART transport layer
HCI command (refer to Section 7). The default baud rate is 115.2 kbps.
6.1.1 UART interface
- UART_RX: UART receiver line
- UART_TX: UART transmitting line
6.1.2 UART settings
- Baud rate: configurable via HCI
- The default baud rate is 115.2 kbps. The default value is only set by POR or the RST pin
- Number of data bits: 8
- Parity bit: no parity
- Start bit: 1 start bit
- Stop bit: 1 stop bit
- Flow control: not used
Table 14. HCI event format
2 Event_Code 1
where 0xFF is reserved for Vendor specific events.
3 Parameter_Total_Le
an integer number of octets in size.
STLBC01 Host controller interface (HCI)
6.2 HCI SPI transport layer
The STBLC01 features a proprietary HCI SPI transport level which may allow the host/controller system to reach lower power consumption by using lower clock frequencies. HCI commands sent and events received over the SPI transport layer are identical to the ones sent/received over the UART transport level. The STBLC01 supports only slave mode SPI. The maximal SPI speed is 10 MHz. STBLC01 HCI events are signalled to host thought the assertion of the IRQ pin. When this occurs, the host sends a clock so that event can be read. Pin IRQ is also used to inform the host that the STBLC01 has data coming from RF communication to send. The procedures to read events or data are exactly the same.
6.2.1 SPI interface
The STBLC01 includes a 5-wire, 8-bit, MSB first, Motorola compatible with CPOL=0, CPHA=0 SPI interface. Only half-duplex transport is supported. The SPI interface is defined through the following pins:
- CSN: chip select signal. This signal is active low and it is mandatory, even when only 1 slave device is connected to the host
- SPI_SCK: SPI clock signal. When CSN is active, the host sends to the controller a number of clock cycles in multiples of 8 bits during each SPI transaction. When CSN is not active, the STBLC01 ignores any signal sent to this pin. This allows the host to set a clock signal to serve other devices
- SPI_MOSI: Host to controller transfer data line. The host generates data on the negative edge and samples data on the positive edge of the SPI_SCK signal. SPI data is sent in byte format, with the most significant bit (MSB) first.
- SPI_MISO: Controller to the host transfer data line. When CSN is active, controller generated data on the negative edge and sample data on the positive edge of the SPI_SCK signal. When CSN is inactive, the controller sets this output in tristate mode. SPI data is sent in byte format, with the most significant bit (MSB) first.
- IRQ: Interrupt request. This signal is set by the controller when an event needs to be sent to the host.
6.2.2 SPI flow control
The STBLC01 features a proprietary flow control for all communications over SPI both from the host to the controller and from the controller to the host. Each SPI transaction is done for 8 bits of data. Host to controller flow When the host needs to communicate with the controller, the following flow is followed: 1. Host sets the MOSI signal to '1'. 2. Host activates CSN after 100 ns. 3. Host polls MISO line. The first polling is done at least 100 ns after CSN is activated. 4. If MISO = '0' then the controller reception buffer is full and the host is not allowed to start the transaction. 5. If MISO = '1' then the controller reception buffer is not full and the host can start the transaction. After each set of 8 rising edges of SPI_SCK, the host polls the MISO line to check whether the controller reception buffer is not full. The first polling can be done on the first SPI_SCK falling edge.
Host controller interface (HCI) STLBC01 Controller to host flow When the controller needs to communicate with the host, the following flow is followed: 1. Controller sets IRQ line to '1'. This means that the controller has at least 1 byte of data to transmit. 2. Host pulls down the MOSI signal. 3. Host activates CSN after 100 ns. 4. Host starts an SPI transaction by sending a data byte equal to 0x00. 5. Host reads data sent by the controller on the MISO line. 6. If IRQ is set to '0' during an SPI transaction, then the controller has no other data to transmit. Once all bits of the transaction are read, the host can stop sending a clock.
7 Peripherals information
The STBLC01 includes several peripherals to fulfil all the requirements of the BLE standard. description of STBLC01 internal peripherals to provide a better overview of the system.
7.1 AES
refer to the official page of NIST (http://csrc.nist.gov/CryptoToolkit/aes/).
- BLE encryption key calculation
- BLE message integrity code (MIC) calculation
- BLE encryption stream generation
7.2 Random number generator (RNG)
stream as required in [2]. The result of this block is a non-deterministic 32-bit stream.
7.3 Battery level detector (SVLD)
measurement is completed, an event is reported to the host, as described in Section 9.3.2. All voltages specified in Table 15 must be considered with a precision of ±10%. Table 15. SVLD reference
2.05 V Battery low detection
2.25 V Battery low early warning
8 Application design guidelines
This section provides some design guidelines and constraints are given for proper application designs. In particular, antenna port and antenna design guidelines, XTAL oscillator and power supply connections are described. Furthermore, PCB guidelines are stated in order to achieve an optimum RF-performance.
8.1 Antenna port
The STBLC01 features a fully differential 200 +j0 Ω antenna port for the received or emitted signals at the pins ANTP and ANTN. The selected input/output impedance allows the implementation of a folded dipole antenna directly connectable to the antenna port which does not require any external matching components. Use of other types of antenna is granted by the implementation of a matching network with few external components. The following general guidelines can be used to achieve the best results in terms of RF performance: 1. Use at least a 2-layer PCB, dedicating the bottom layer to one common ground plane covering all external components and the chip itself. Connect the attached area pin of the package to the ground plane. 2. Keep the STBLC01 ANTN/ANTP symmetry on the PCB by keeping symmetry in components and via placement as well as line-routing. 3. Use only 100 Ω transmission lines between the STBLC01 RF output pins and the antenna / matching network input. 4. Try to minimize RF trace lengths. 5. Respect also a 3 mm clearance to ground close to RF transmission lines and/or matching network components. In particular, respect clearance to ground for antenna structure (varies with antenna topology). 6. Do not put a ground plane below the antenna structure to avoid gain loss and directivity modification. 8.1.1 50 Ohm matching The STBLC01 antenna impedance can be converted to 50 Ω termination to allow interfacing with a standard measurement system or with a standard 50 Ω antenna structure. In this case, a matching circuit which ensures the conversion from the differential 200 Ω antenna port of the STBLC01 and the single-ended 50 Ω of the instruments, is required. Figure 7 shows an example circuit to implement a matching network. In order to achieve the best RF performance, the layout around the antenna port - both for the chip and attached antenna connector - needs to be done while keeping RF guidelines in mind.
Figure 7. Matching circuit for 50 Ohm antenna
8.2 Xtal oscillator
diagram of the amplitude regulated oscillator used in the STBLC01.
50 Ohm200 Ohm
Figure 8. Xtal block diagram injection. Connect each capacitor of the XTAL oscillator to ground by a separate via. resistor can be added at the cost of extra current consumption.
8.3 Power supplies
In order to avoid any interference on the RF communication, all STBLC01 power supplies need to be properly decoupled. In general, all decoupling capacitors defined in Figure 4 need to be as close as possible to the relative pin. Special caution needs to be taken for the decoupling on AVDD_PA (power supply for PA) and VDD (power supply for digital part). It is mandatory to put the decoupling capacitors as close as possible to the pin. All ground connections must be as short as possible using vias directly to the ground plane. Avoid sharing vias between different signals.
9 Vendor HCI commands
9.1 STBLC_SET_PUBLIC_ADDRESS
9.1.1 Command parameters for STBLC_SET_PUBLIC_ADDRESS
9.1.2 Return parameters for STBLC_SET_PUBLIC_ADDRESS
Table 16. HCI commands Table 17. Command parameters for STBLC_SET_PUBLIC_ADDRESS Table 18. Return parameters for STBLC_SET_PUBLIC_ADDRESS
9.2 STLBC_SET_POWER_MODE
9.2.1 Command parameters for STLBC_SET_POWER_MODE
9.2.2 Return parameters for STLBC_SET_POWER_MODE
9.2.3 Returned events for STLBC_SET_POWER_MODE
- From Idle mode to Sleep/Off mode, only the command completed event is returned.
- From Sleep/Off mode to Idle mode, a command status is sent after checking the
9.3 STBLC_SVLD_MEASUREMENT
9.3.1 Command parameters for STBLC_SVLD_MEASUREMENT
Table 19. Command parameters for STLBC_SET_POWER_MODE Table 20. Return parameters for STLBC_SET_POWER_MODE Table 21. Command parameters for STBLC_SVLD_MEASUREMENT
9.3.2 Return parameters for STBLC_SVLD_MEASUREMENT
9.3.3 Returned events fo r STBLC_SVLD_MEASUREMENT
9.4 STBLC_SET_RF_POWER_LEVEL
9.4.1 Command parameters for STBLC_SET_RF_POWER_LEVEL
9.4.2 Return parameters for STBLC_SET_RF_POWER_LEVEL
9.4.3 Returned events for STBLC_SET_RF_POWER_LEVEL
Table 22. Return parameters for STBLC_SVLD_MEASUREMENT Table 23. Command parameters for STBLC_SET_RF_POWER_LEVEL Table 24. Return parameters for STBLC_SET_RF_POWER_LEVEL
9.5 STBLC_POWER_MODE-CONFIGURATION
9.5.1 Command parameters for STBLC_POWER_MODE-CONFIGURATION
9.5.2 Return parameters for STBLC_POWER_MODE-CONFIGURATION
9.5.3 Returned events for STBLC_POWER_MODE-CONFIGURATION
9.6 STBLC_SET_UART_BAUD_RATE
9.6.1 Command parameters for STBLC_SET_UART_BAUD_RATE
Table 25. Command parameters for STBLC_POWER_MODE-CONFIGURATION Table 26. Return parameters for STBLC_POWER_MODE-CONFIGURATION Table 27. Command parameters for STBLC_SET_UART_BAUD_RATE
9.6.2 Return parameters for STBLC_SET_UART_BAUD_RATE
9.6.3 Returned events for STBLC_SET_UART_BAUD_RATE
strongly recommended to use this command only after power-up or reset. Table 28. Return parameters for STBLC_SET_UART_BAUD_RATE
10 Vendor HCI events
10.1 STBLC_POWER_MODE_IDLE
after watchdog or bus error resets. This event is sent after POR and HCI resets. The associated event code is 0xFF.
10.1.1 Event parameters
10.2 Hardware error event codes
Table 29. Event parameters for STBLC_POWER_MODE_IDLE Table 30. Hardware error event codes
11 Related documents
- Bluetooth Low Energy RF-PHY Test Specifications, Version 4.0, Bluetooth SIG, 15.12.2009. 5. ETSI EN 300 328, Version 1.7.1, May 2006. 6. FCC Rules 15.247, FCC, Sept. 2009.
specifications, grade definitions and product status are available at: www.st.com. Table 31. VFQFPN 5X5X0.9 24 leads mechanical dimensions
Figure 9. VFQFPN 5X5X0.9 24 leads mechanical drawing
Table 32. Document revision history 10-Jan-2013 1 Initial release. 22-Apr-2013 2 Document status promoted from preliminary data to production data.