STL8N65M2 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 15
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics curves
- 3 Test circuits
- 4 Package information
- 4.1 PowerFLAT 5x6 HV package information
- 4.2 PowerFLAT 5x6 packing information
Features
Order code VDS RDS(on ) max. ID STL8N65M2 650 V 1.25 Ω 4 A
- Extremely low gate charge
- Excellent output capacitance (C OSS) profile
- 100% avalanche tested
- Zener-protected
Applications
- Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL8N65M2 Product summary Order code STL8N65M2 Marking 8N65M2 Package PowerFLAT 5x6 HV Packing Tape and reel N-channel 650 V, 1 Ω typ., 4 A MDmesh M2 Power MOSFET in a PowerFLAT 5x6 HV package STL8N65M2 Datasheet DS13016 - Rev 1 - May 2019 For further information contact your local STMicroelectronics sales office.
1 Electrical ratings
Table 1. Absolute maximum ratings
- Pulse width is limited by safe operating area.
Table 2. Thermal data
- When mounted on 1 inch² FR-4, 2 Oz copper board
Table 3. Thermal data
2 Electrical characteristics
TC = 25 °C unless otherwise specified Table 4. On/off-state
- Defined by design, not subject to production test.
Table 5. Dynamic
- C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
Table 6. Switching times
Electrical characteristics
Table 7. Source-drain diode Figure 15. Test circuit for
- Pulse width is limited by safe operating area
- Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2.1 Electrical characteristics curves
Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Normalized V(BR)DSS vs temperature Figure 6. Source-drain diode forward characteristics
3 Test circuits
Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior Figure 15. Test circuit for inductive load switching and Figure 16. Unclamped inductive load test circuit Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. STL8N65M2
Package information
4.1 PowerFLAT 5x6 HV package information
Figure 19. PowerFLAT 5x6 HV package outline
Table 8. PowerFLAT 5x6 HV mechanical data Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)
4.2 PowerFLAT 5x6 packing information
Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) Figure 22. PowerFLAT 5x6 package orientation in carrier tape
Figure 23. PowerFLAT 5x6 reel
Revision history
Table 9. Document revision history