STL8DN10LF3 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 15

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package information
  • 5 Packing information
  • 6 Revision history

Features

  • Designed for automotive applications and AEC-Q101 qualified
  • Logic level VGS(th)
  • 175 °C maximum junction temperature
  • 100% avalanche rated
  • Wettable flank package

Applications

  • Switching applications

Description

This device is a dual N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. 3RZHU)/$7Œ[GRXEOHLVODQG Order code V DS RDS(on) max I D STL8DN10LF3 100 V 35 m Ω 7.8 A Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Specified by design. Not subject to production test.
  2. Current is limited by bonding, with an R thJC = 2.1 °C/W the chip is able to carry 32 A at 25 °C.
  3. Pulse width limited by safe operating area.
  4. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec

Table 3. Thermal resistance

  1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec

2 Electrical characteristics

Table 4. On/off states Table 5. Dynamic Table 6. Switching times

Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration= 300 µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized V(BR)DSS vs temperature Figure 7. Static drain-source on-resistance

3 Test circuits

Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test circuit Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform

4 Package information

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. PowerFLAT™ 5x6 double island WF type R package outline

Table 8. PowerFLAT™ 5x6 double island WF type R mechanical data

Figure 19. PowerFLAT™ 5x6 double island recommended footprint (dimensions are

5 Packing information

Figure 20. PowerFLAT 5x6 WF tape(a) Figure 21. PowerFLAT™ 5x6 package orientation in carrier tape hole to centreline of pocket.

Figure 22. PowerFLAT™ 5x6 reel

6 Revision history

Table 9. Document revision history 28-Mar-2012 1 First release. 20-Jun-2012 2 Added Section 2.1: Electrical characteristics (curves). Updated Section 4: Package information and title on the cover page. 26-Jun-2012 3 Updated Figure 9: Capacitance variations. Document status promoted from preliminary to production data. 10-Jul-2015 6 – Updated title and description in cover page. – Updated Section 4: Package information.