STL7N80K5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 17

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

  • Outstanding RDS(on)*area
  • Worldwide best FOM (figure of merit)
  • Ultra low gate charge
  • 100% avalanche tested
  • Zener protected

Applications

  • Switching applications

Description

This N-channel Zener-protected Power MOSFET is designed using ST's revolutionary avalanche- rugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. AM15540v1 5678 12 34 Top View D(5, 6, 7, 8) G(4) S(1, 2, 3) PowerFLAT™ 5x6 VHV Order code V DS RDS(on)max. ID STL7N80K5 800 V 1.2 Ω 3.6 A Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according to R thj-case and limited by package.
  2. Pulse width limited by safe operating area.
  3. Pulse width limited by T jmax
  4. Starting T j=25 °C, ID=IAR, VDD=50 V

Table 3. Thermal data

  1. When mounted on 1inch² FR-4 board, 2 oz Cu.

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. time related is defined as a constant equivalent capacitance giving the same charging
  2. C oss eq. energy related is defined as a constant equivalent capacitance giving the same stored

voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. Table 6. Switching times Table 7. Source drain diode

  1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

Table 8. Gate-source Zener diode

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance

Figure 8. Capacitance variations Figure 9. Output capacitance stored energy Figure 10. Normalized gate threshold voltage Figure 11. Normalized on-resistance vs. Figure 12. Drain-source diode forward Figure 13. Normalized VDS vs. temperature

0 VDS(V)

Figure 14. Maximum avalanche energy vs.

3 Test circuits

Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test circuit Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Table 9. PowerFLAT™ 5x6 VHV mechanical data

Figure 21. PowerFLAT™ 5x6 VHV

Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm)

5 Packaging mechanical data

Figure 23. PowerFLAT™ 5x6 tape Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape. hole to centerline of pocket.

Figure 25. PowerFLAT™ 5x6 reel

6 Revision history

Table 10. Document revision history 19-Nov-2013 1 First release.