STL6NM60N STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

Features

■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance Application ■ Switching applications

Description

This series of devices implements the second generation of MDmesh™ Technology. This revolutionary Power MOSFET associates a new vertical structure to the Company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Figure 1. Internal schematic diagram

  1. The value is rated according Rthj-case

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according Rthj-case
  2. Pulse width limited by safe operating area.
  3. When mounted on FR-4 board of 1inch², 2oz Cu

0.02 W/°C

Table 3. Thermal resistance

  1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec

Table 4. Avalanche characteristics

  1. Pulse width limited by Tjmax
  2. Starting Tj = 25 °C, I D= IAS, VDD = 50 V

2 Electrical characteristics

Table 5. On/off states

  1. Characteristics value at turn off on inductive load

Table 6. Dynamic

  1. Pulsed: pulse duration= 300 µs, duty cycle 1.5%
  2. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

Table 7. Switching times Table 8. Source drain diode

  1. Pulse width limited by safe operating area
  2. When mounted on FR-4 board of 1inch², 2oz Cu
  3. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance

3 Test circuit

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test Figure 18. Unclamped inductive wavefo rm Figure 19. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A1 0.02 0.05 0.0007 0.002 A3 0.24 0.009 D 5.00 0.19 E 5.00 0.19 e 1.27 0.05 PowerFLAT™ (5x5) MECHANICAL DATA

5 Revision history

Table 9. Document revision history