STL50DN6F7 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 15

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics(curve)
  • 3 Test circuits
  • 4 Package information
  • 4.1 PowerFLAT 5x6 double island type R package information
  • 4.2 PowerFLAT™ 5x6 packing information
  • 5 Revision history

Features

Order code VDS RDS(on) max. ID STL50DN6F7 60 V 11 mΩ 57 A  Among the lowest RDS(on) on the market  Excellent figure of merit (FoM)  Low Crss/Ciss ratio for EMI immunity  High avalanche ruggedness

Applications

 Switching applications

Description

This dual N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packaging STL50DN6F7 50DN6F7 PowerFLAT™ 5x6 double island Tape and reel

1 Electrical ratings

Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate source voltage ±20 V ID(1) Drain current (continuous) at TC = 25 °C 57 A Drain current (continuous) at TC = 100 °C 41 IDM(1)(2) Drain current (pulsed) 228 A ID(3) Drain current (continuous) at Tpcb = 25 °C 15 A Drain current(continuous) at Tpcb =100 °C 11 IDM(2)(3) Drain current (pulsed) 60 A PTOT Total dissipation at TC = 25 °C 62.5 W Total dissipation at Tpcb = 25 °C 4.8 TJ Operating junction temperature -55 to 175 °C Tstg Storage temperature Notes: (1)This value is rated according to Rthj-c (2)Pulse width limited by safe operating area. (3)This value is rated according to Rthj-pcb Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.4 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W Notes: (1)When mounted on FR-4 board of 1inc2, 2oz Cu, t < 10 sec

2 Electrical characteristics

(TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID= 1 mA 60 V IDSS Zero gate voltage drain current VDS= 60 V,VGS= 0 V 1 µA IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 2 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 7.5 A 9 11 mΩ Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 30V, f = 1 MHz,VGS= 0 V - 1035 - pF Coss Output capacitance - 450 - pF Crss Reverse transfer capacitance - 53 - pF Qg Total gate charge VDD = 30 V, ID = 15 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 17 - nC Qgs Gate-source charge - 5.7 - nC Qgd Gate-drain charge - 5.7 - nC Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 30V, ID =7.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" - 14.5 - ns tr Rise time - 15.3 - ns td(off) Turn-off delay time - 19.4 - ns tf Fall time - 8 - ns Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit VSD(1) Forward on voltage ISD = 15 A, VGS = 0 V - 1.2 V trr Reverse recovery time ISD = 15 A, di/dt = 100 A/µs, VDD = 48 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 26.8 ns Qrr Reverse recovery charge - 14.2 nC IRRM Reverse recovery current - 1.06 A Notes: (1)Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteristics(curve)

Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance

3 Test circuits

Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

4.1 PowerFLAT 5x6 double island type R package information

Figure 19: PowerFLAT™ 5x6 double island type R package outline 8256945_D.I._typeR_R14

Table 8: PowerFLAT™ 5x6 double island type R mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 1.68 1.88 D3 4.80 5.00 5.20 D4 4.05 4.20 4.35 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 1.27 E 5.95 6.15 6.35 E2 3.50 3.70 E3 0.20 0.325 0.45 E4 0.55 0.75 E5 0.08 0.28 E6 2.35 2.55 E7 0.40 0.60 E8 0.75 0.90 1.05 L 0.60 0.80 L1 0.05 0.15 0.25 K 1.275 1.575 θ 0° 12°

Figure 20: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)

4.2 PowerFLAT™ 5x6 packing information

Figure 21: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape

Figure 23: PowerFLAT™ 5x6 reel

5 Revision history

Table 9: Document revision history Date Revision Changes 17-Jul-2015 1 First release. 13-Nov-2015 2 Document status promoted from preliminary to production data. Updated title and features in cover page. Updated Table 2: "Absolute maximum ratings" and Section 4: "Electrical characteristics". Added Section 4.1: "Electrical characteristics(curve)" Minor text changes.